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variable names and `include'
From: |
Tom Bachmann |
Subject: |
variable names and `include' |
Date: |
Sat, 24 Jun 2006 14:24:09 +0200 |
User-agent: |
Mail/News 1.5 (X11/20060403) |
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Hi,
[please cc me as I'm not registered to the list]
I'm currently digging into how to extend automake. As make can do
(nearly) everything automake can, I suppose I'll end up at a stage where
everyone who wants the new stuff includes a Makefile snippet into the
Makefile.am.
In this included snippet I do someting like
define FOO
...
endef
$(foreach foo,$(FOOS),$(eval $(call FOO,$(foo))))
Now I'm utilizing the output of a shell command in FOO multiple times.
Currently, I do:
bar = $(shell ... $(1))
define FOO
...
$(bar): ...
...
endef
...
(actually $(bar) is used about 10 times.) This works, because bar is
recursively evaluated, but this also means the shell command is called
about 10 times. I cannot do bar := ..., because $(1) is not known in the
context of bar's definition. I'd like to do:
NAME = $(subst ... $(1))
define FOO
$(NAME)_bar := $(shell ... $(1))
...
endef
...
But automake complains "bad characters in variable name". I could work
around this by stopping automake from processing the file (make allows
it), but I could not find a way to do this but $(eval include bar.mk),
which is, uhm, a bit ugly.
- --
- -ness-
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- variable names and `include',
Tom Bachmann <=