dynamically define variables?

[Daniel Neuberger]

All,

I'm afraid that what I want to do might be impossible, but I'm hoping 
you all can help me think of a way.  What I have is something like:

----------------Makefile.am----------------
# specific to this Makefile.am
bin_PROGRAMS = foo bar

foo_SOURCES = foo.cpp
bar_SOURCES = bar.cpp

# I'd get rid of having to define empty versions of these
foo_CPPFLAGS =
bar_CPPFLAGS =

# things that should be done globally
foo_SOURCES += global.cpp
foo_CPPFLAGS += -DEXECUTABLE_NAME=foo

bar_SOURCES += global.cpp
bar_CPPFLAGS += -DEXECUTABLE_NAME=bar
----------------Makefile.am----------------

What I  want is to replace the global section at the end with an include 
.am file that iteratively adds global.cpp to the SOURCES list and the 
define to the flags for each program in the Makefile.am.

Put another way, I have a bunch of programs.  There's one source file 
that I need to compile and link to each program using a different flag 
based on the program name.

Also note that the global section above currently requires that the 
variables being appended to already exist.  I'd like to find a way 
around that too.

Any ideas?

Thanks.

- Daniel