2007-08-31 Michael Meissner Dwarakanath Rajagopal * NEWS: Add note about SSE5 being added on i386. 2007-08-31 Michael Meissner Dwarakanath Rajagopal Tony Linthicum * NEWS: Add SSE5 support to NEWS file. * config/tc-i386.h (drex_byte): Add fields to allow process_drex and build_modrm_byte to communicate. (DREX_OC0): New SSE5 macro. (DREX_OC0_MASK): Ditto. (DREX_OC1): Ditto. (DREX_OC1_MASK): Ditto. (DREX_XMEM_X1_X2_X2): Ditto. (DREX_X1_XMEM_X2_X2): Ditto. (DREX_X1_XMEM_X2_X1: Ditto. (DREX_X1_X2_XMEM_X1: Ditto. (DREX_XMEM_X1_X2): Ditto. (DREX_X1_XMEM_X2): Ditto. (drex_byte): New structure to describe the DREX byte. * config/tc-i386.c (process_drex): New function to handle SSE5 DREX bits. (build_modrm_byte): Use the information cached away in process_drex in the case of DREX instructions. (i386_insn): Add drex field. (pi): Add debugging of drex field. (md_assemble): Treat SSE5 like SSE3 in instructions with an immediate byte. Move REX field to DREX if this is a DREX instruction. (process_operands): Add SSE5 support. (build_modrm_byte): Ditto. (output_insn): Ditto. (cpu_arch): Ditto. (i386_align_code): Ditto. 2007-08-31 Michael Meissner Dwarakanath Rajagopal Tony Linthicum * gas/i386/i386.exp (x86-64-sse5): Run SSE5 64-bit tests. (sse5): Do not currently run 32-bit tests. * gas/i386/x86-64-sse5.s: New file for SSE5 support. * gas/i386/x86-64-sse5.d: Ditto. 2007-08-31 Michael Meissner Dwarakanath Rajagopal Tony Linthicum * i386-opc.h (template): Add opcode_modifier2 field. (Drex): New macro for SSE5 instructions. (Drexv): Ditto. (Drexc): Ditto. (Sse5Common1): Ditto. (Sse5Common2): Ditto. * i386-gen.c (process_i386_opcodes): Add support for a second opcode_modifier field, automatically detecting whether the field exists or not. * i386-opc.tbl (fmaddps,fmaddpd,fmaddss,fmaddsd): Define SSE5 instructions here. (fmsubps,fmsubpd,fmsubss,fmsubsd): Ditto. (fnmaddps,fnmaddpd,fnmaddss,fnmaddsd): Ditto. (fnmsubps,fnmsubpd,fnmsubss,fnmsubsd): Ditto. (pmacssww,pmacsww,pmacsswd,pmacswd): Ditto. (pmacssdd,pmacsdd,pmacssdql,pmacssdqh): Ditto. (pmacsdql,pmacsdqh,pmadcsswd,pmadcswd): Ditto. (phaddbw,phaddbd,phaddbq,phaddwd): Ditto. (phaddwq,phadddq,phaddubw,phaddubd): Ditto. (phaddubq,phadduwd,phadduwq,phaddudq): Ditto. (phsubbw,phsubwd,phsubdq): Ditto. (pcmov,pperm,permps,permpd): Ditto. (protb,protw,protd,protq): Ditto. (pshlb,pshlw,pshld,pshlq): Ditto. (pshab,pshaw,pshad,pshaq): Ditto. (comps,comeqps,comltps,comungeps,comleps,comungtps): Ditto. (comunordps,comneps,comneqps,comnltps,comugeps): Ditto. (comnleps,comugtps,comordps,comueqps,comultps): Ditto. (comngeps,comuleps,comngtps,comfalseps,comuneps): Ditto. (comuneqps,comunltps,comgeps,comunleps,comgtps,comtrueps): Ditto. (compd,comeqpd,comltpd,comungepd,comlepd,comungtpd,comunordpd): Ditto. (comnepd,comneqpd,comnltpd,comugepd,comnlepd,comugtpd): Ditto. (comordpd,comueqpd,comultpd,comngepd,comulepd,comngtpd): Ditto. (comfalsepd,comunepd,comuneqpd,comunltpd,comgepd): Ditto. (comunlepd,comgtpd,comtruepd): Ditto. (comss,comeqss,comltss,comungess,comless,comungtss,comunordss): Ditto. (comness,comneqss,comnltss,comugess,comnless,comugtss): Ditto. (comordss,comueqss,comultss,comngess,comuless,comngtss): Ditto. (comfalsess,comuness,comuneqss,comunltss,comgess): Ditto. (comunless,comgtss,comtruess): Ditto. (comsd,comeqsd,comltsd,comungesd,comlesd,comungtsd,comunordsd): Ditto. (comnesd,comneqsd,comnltsd,comugesd,comnlesd,comugtsd): Ditto. (comordsd,comueqsd,comultsd,comngesd,comulesd,comngtsd): Ditto. (comfalsesd,comunesd,comuneqsd,comunltsd,comgesd): Ditto. (comunlesd,comgtsd,comtruesd): Ditto. (pcomub,pcomltub,pcomleub,pcomgtub,pcomgeub,pcomequb): Ditto. (pcomnequb,pcomneub): Ditto. (pcomuw,pcomltuw,pcomleuw,pcomgtuw,pcomgeuw,pcomequw): Ditto. (pcomnequw,pcomneuw): Ditto. (pcomud,pcomltud,pcomleud,pcomgtud,pcomgeud,pcomequd): Ditto. (pcomnequd,pcomneud): Ditto. (pcomuq,pcomltuq,pcomleuq,pcomgtuq,pcomgeuq,pcomequq): Ditto. (pcomnequq,pcomneuq): Ditto. (pcomb,pcomltb,pcomleb,pcomgtb,pcomgeb,pcomeqb): Ditto. (pcomneqb,pcomneb): Ditto. (pcomw,pcomltw,pcomlew,pcomgtw,pcomgew,pcomeqw): Ditto. (pcomneqw,pcomnew): Ditto. (pcomd,pcomltd,pcomled,pcomgtd,pcomged,pcomeqd): Ditto. (pcomneqd,pcomned): Ditto. (pcomq,pcomltq,pcomleq,pcomgtq,pcomgeq): Ditto. (pcomeqq,pcomneqq,pcomneq): Ditto. (pcomtrueb, pcomtruew, pcomtrued, pcomtrueq): Ditto. (pcomtrueub, pcomtrueuw, pcomtrueud, pcomtrueuq): Ditto. (pcomfalseb, pcomfalsew, pcomfalsed, pcomfalseq): Ditto. (pcomfalseub, pcomfalseuw, pcomfalseud, pcomfalseuq): Ditto. (frczps,frczpd,frczss,frczsd): Ditto. (cvtph2ps,cvtps2ph): Ditto. * i386-tbl.h: Regenerate from i386-opc.tbl. * i386-dis.c (libiberty.h): Include to get ARRAY_SIZE. (dis386_move_test): New disassembly support for move from test register instruction that overlaps with SSE5 instructions. (print_insn): Add support for special casing the i386/i486 move from test register instruction that overlaps with the SSE5 0x0f24 4 operand instructions. (OP_DREX_ICMP): New macros for SSE5 DREX handling. (OP_DREX_FCMP): Ditto. (OP_E_extended): Rename from OP_E, add additional argument to skip the DREX byte. (OP_E): Call OP_E_extended. (DREX_REG_MEMORY): New macros for drex handling. (DREX_REG_UNKNOWN): Ditto. (DREX4_OC1): Ditto. (DREX4_NO_OC0): Ditto. (DREX4_MASK): Ditto. (three_byte_table): Add SSE5 instructions. (print_drex_arg): New function to print a DREX register or memory reference. (OP_DREX4): New function for handling DREX 4 argument ops. (OP_DREX3): New function for handling DREX 3 argument ops. (twobyte_has_modrm): 0f{25,7a,7b} all use the modrm byte. (THREE_BYTE_SSE5_0F{24,25,7A,7B}): New macros for initializing 3 byte opcode support for SSE5 instructions. (dis386_twobyte): Add SSE5 24/25/7a/7b support. (three_byte_table): Add rows for describing SSE5 instructions. * Makefile.am (i386-dis.lo): Add $(INCDIR)/libiberty.h. * Makefile.in (i386-dis.lo): Add $(INCDIR)/libiberty.h. *** binutils/NEWS.~1~ 2007-08-31 11:40:00.212434000 -0400 --- binutils/NEWS 2007-08-30 19:23:45.252472000 -0400 *************** *** 1,4 **** --- 1,6 ---- -*- text -*- + * Support for SSE5 has been added to the i386 port. + * Added -p switch to readelf to allow string dumps of sections. Changes in 2.18: *** gas/NEWS.~1~ 2007-08-31 11:40:00.702567000 -0400 --- gas/NEWS 2007-08-31 11:39:47.947166000 -0400 *************** *** 1,4 **** --- 1,6 ---- -*- text -*- + * Support for SSE5 has been added to the i386 port. + Changes in 2.18: * The GAS sources are now released under the GPLv3. *** gas/config/tc-i386.c.~1~ 2007-08-31 11:40:00.777890000 -0400 --- gas/config/tc-i386.c 2007-08-31 11:35:12.625640000 -0400 *************** static int check_long_reg (void); *** 88,93 **** --- 88,94 ---- static int check_qword_reg (void); static int check_word_reg (void); static int finalize_imm (void); + static void process_drex (void); static int process_operands (void); static const seg_entry *build_modrm_byte (void); static void output_insn (void); *************** struct _i386_insn *** 160,170 **** unsigned char prefix[MAX_PREFIXES]; /* RM and SIB are the modrm byte and the sib byte where the ! addressing modes of this insn are encoded. */ modrm_byte rm; rex_byte rex; sib_byte sib; }; typedef struct _i386_insn i386_insn; --- 161,173 ---- unsigned char prefix[MAX_PREFIXES]; /* RM and SIB are the modrm byte and the sib byte where the ! addressing modes of this insn are encoded. DREX is the byte ! added by the SSE5 instructions. */ modrm_byte rm; rex_byte rex; sib_byte sib; + drex_byte drex; }; typedef struct _i386_insn i386_insn; *************** static const arch_entry cpu_arch[] = *** 516,521 **** --- 519,526 ---- CpuSVME}, {".sse4a", PROCESSOR_UNKNOWN, CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a}, + {".sse5", PROCESSOR_UNKNOWN, + CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuSSE5}, {".abm", PROCESSOR_UNKNOWN, CpuABM} }; *************** pi (char *line, i386_insn *x) *** 1381,1386 **** --- 1386,1392 ---- (x->rex & REX_R) != 0, (x->rex & REX_X) != 0, (x->rex & REX_B) != 0); + fprintf (stdout, " drex: reg %d rex 0x%x\n", x->drex.reg, x->drex.rex); for (i = 0; i < x->operands; i++) { fprintf (stdout, " #%d: ", i + 1); *************** md_assemble (line) *** 1863,1871 **** /* These AMD 3DNow! and Intel Katmai New Instructions have an opcode suffix which is coded in the same place as an 8-bit immediate field would be. Here we fake an 8-bit immediate ! operand from the opcode suffix stored in tm.extension_opcode. */ ! ! assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS); exp = &im_expressions[i.imm_operands++]; i.op[i.operands].imms = exp; --- 1869,1882 ---- /* These AMD 3DNow! and Intel Katmai New Instructions have an opcode suffix which is coded in the same place as an 8-bit immediate field would be. Here we fake an 8-bit immediate ! operand from the opcode suffix stored in tm.extension_opcode. ! SSE5 also uses this encoding, for some of its 3 argument ! instructions. */ ! ! assert (i.imm_operands == 0 ! && (i.operands <= 2 ! || ((i.tm.cpu_flags & CpuSSE5) != 0 ! && i.operands <= 3))); exp = &im_expressions[i.imm_operands++]; i.op[i.operands].imms = exp; *************** md_assemble (line) *** 1942,1948 **** } } ! if (i.rex != 0) add_prefix (REX_OPCODE | i.rex); /* We are ready to output the insn. */ --- 1953,1966 ---- } } ! /* If the instruction has the DREX attribute (aka SSE5), don't emit a ! REX prefix. */ ! if ((i.tm.opcode_modifier2 & (Drex|Drexc)) != 0) ! { ! i.drex.rex = i.rex; ! i.rex = 0; ! } ! else if (i.rex != 0) add_prefix (REX_OPCODE | i.rex); /* We are ready to output the insn. */ *************** finalize_imm (void) *** 3360,3365 **** --- 3378,3690 ---- return 1; } + static void + process_drex (void) + { + i.drex.modrm_reg = None; + i.drex.modrm_regmem = None; + + /* SSE5 4 operand instructions must have the desitnation the same as one of + the inputs. Figure out the destination register and cache it away in the + drex field, and remember which fields to use for the modrm byte. */ + if ((i.tm.opcode_modifier2 & (Drex|Drexv)) == (Drex|Drexv) && i.operands == 4) + { + i.tm.extension_opcode = None; + + /* Case 1: 4 operand insn, dest = src1, src3 = register. */ + if ((i.types[0] & RegXMM) != 0 + && (i.types[1] & RegXMM) != 0 + && (i.types[2] & RegXMM) != 0 + && (i.types[3] & RegXMM) != 0 + && i.op[0].regs->reg_num == i.op[3].regs->reg_num + && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags) + { + /* Clear the arguments that are stored in drex. */ + i.types[0] = 0; + i.types[3] = 0; + i.reg_operands -= 2; + + /* There are two different ways to encode a 4 operand instruction + with all registers that uses OC1 set to 0 or 1. Favor setting OC1 + to 0 since this mimics the actions of other SSE5 assemblers. Use + modrm encoding 2 for register/register. Include the high order + bit that is normally stored in the REX byte in the register + field. */ + i.tm.extension_opcode = DREX_X1_XMEM_X2_X1; + i.drex.modrm_reg = 2; + i.drex.modrm_regmem = 1; + i.drex.reg = (i.op[3].regs->reg_num + + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); + } + + /* Case 2: 4 operand insn, dest = src1, src3 = memory. */ + else if ((i.types[0] & RegXMM) != 0 + && (i.types[1] & RegXMM) != 0 + && (i.types[2] & (RegXMM | AnyMem)) != 0 + && (i.types[3] & RegXMM) != 0 + && i.op[0].regs->reg_num == i.op[3].regs->reg_num + && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags) + { + /* clear the arguments that are stored in drex */ + i.types[0] = 0; + i.types[3] = 0; + i.reg_operands -= 2; + + /* Specify the modrm encoding for memory addressing. Include the + high order bit that is normally stored in the REX byte in the + register field. */ + i.tm.extension_opcode = DREX_X1_X2_XMEM_X1; + i.drex.modrm_reg = 1; + i.drex.modrm_regmem = 2; + i.drex.reg = (i.op[3].regs->reg_num + + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); + } + + /* Case 3: 4 operand insn, dest = src1, src2 = memory. */ + else if ((i.types[0] & RegXMM) != 0 + && (i.types[1] & AnyMem) != 0 + && (i.types[2] & RegXMM) != 0 + && (i.types[3] & RegXMM) != 0 + && i.op[0].regs->reg_num == i.op[3].regs->reg_num + && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags) + { + /* Clear the arguments that are stored in drex. */ + i.types[0] = 0; + i.types[3] = 0; + i.reg_operands -= 2; + + /* Specify the modrm encoding for memory addressing. Include the + high order bit that is normally stored in the REX byte in the + register field. */ + i.tm.extension_opcode = DREX_X1_XMEM_X2_X1; + i.drex.modrm_reg = 2; + i.drex.modrm_regmem = 1; + i.drex.reg = (i.op[3].regs->reg_num + + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); + } + + /* Case 4: 4 operand insn, dest = src3, src2 = register. */ + else if ((i.types[0] & RegXMM) != 0 + && (i.types[1] & RegXMM) != 0 + && (i.types[2] & RegXMM) != 0 + && (i.types[3] & RegXMM) != 0 + && i.op[2].regs->reg_num == i.op[3].regs->reg_num + && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags) + { + /* clear the arguments that are stored in drex */ + i.types[2] = 0; + i.types[3] = 0; + i.reg_operands -= 2; + + /* There are two different ways to encode a 4 operand instruction + with all registers that uses OC1 set to 0 or 1. Favor setting OC1 + to 0 since this mimics the actions of other SSE5 assemblers. Use + modrm encoding 2 for register/register. Include the high order + bit that is normally stored in the REX byte in the register + field. */ + i.tm.extension_opcode = DREX_XMEM_X1_X2_X2; + i.drex.modrm_reg = 1; + i.drex.modrm_regmem = 0; + + /* Remember the register, including the upper bits */ + i.drex.reg = (i.op[3].regs->reg_num + + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); + } + + /* Case 5: 4 operand insn, dest = src3, src2 = memory. */ + else if ((i.types[0] & RegXMM) != 0 + && (i.types[1] & (RegXMM | AnyMem)) != 0 + && (i.types[2] & RegXMM) != 0 + && (i.types[3] & RegXMM) != 0 + && i.op[2].regs->reg_num == i.op[3].regs->reg_num + && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags) + { + /* Clear the arguments that are stored in drex. */ + i.types[2] = 0; + i.types[3] = 0; + i.reg_operands -= 2; + + /* Specify the modrm encoding and remember the register including the + bits normally stored in the REX byte. */ + i.tm.extension_opcode = DREX_X1_XMEM_X2_X2; + i.drex.modrm_reg = 0; + i.drex.modrm_regmem = 1; + i.drex.reg = (i.op[3].regs->reg_num + + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); + } + + /* Case 6: 4 operand insn, dest = src3, src1 = memory. */ + else if ((i.types[0] & AnyMem) != 0 + && (i.types[1] & RegXMM) != 0 + && (i.types[2] & RegXMM) != 0 + && (i.types[3] & RegXMM) != 0 + && i.op[2].regs->reg_num == i.op[3].regs->reg_num + && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags) + { + /* clear the arguments that are stored in drex */ + i.types[2] = 0; + i.types[3] = 0; + i.reg_operands -= 2; + + /* Specify the modrm encoding and remember the register including the + bits normally stored in the REX byte. */ + i.tm.extension_opcode = DREX_XMEM_X1_X2_X2; + i.drex.modrm_reg = 1; + i.drex.modrm_regmem = 0; + i.drex.reg = (i.op[3].regs->reg_num + + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); + } + + else + as_bad (_("Incorrect operands for the '%s' instruction"), i.tm.name); + } + + /* SSE5 instructions with the DREX byte where the only memory operand is in + the 2nd argument, and the first and last xmm register must match, and is + encoded in the DREX byte. */ + else if ((i.tm.opcode_modifier2 & (Drex|Drexv)) == Drex && i.operands == 4) + { + /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */ + if ((i.types[0] & RegXMM) != 0 + && (i.types[1] & (RegXMM | AnyMem)) != 0 + && (i.types[2] & RegXMM) != 0 + && (i.types[3] & RegXMM) != 0 + && i.op[0].regs->reg_num == i.op[3].regs->reg_num + && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags) + { + /* clear the arguments that are stored in drex */ + i.types[0] = 0; + i.types[3] = 0; + i.reg_operands -= 2; + + /* Specify the modrm encoding and remember the register including the + high bit normally stored in the REX byte. */ + i.drex.modrm_reg = 2; + i.drex.modrm_regmem = 1; + i.drex.reg = (i.op[3].regs->reg_num + + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); + } + + else + as_bad (_("Incorrect operands for the '%s' instruction"), i.tm.name); + } + + /* SSE5 3 operand instructions that the result is a register, being either + operand can be a memory operand, using OC0 to note which one is the + memory. */ + else if ((i.tm.opcode_modifier2 & (Drex|Drexv)) == (Drex|Drexv) && i.operands == 3) + { + i.tm.extension_opcode = None; + + /* Case 1: 3 operand insn, src1 = register. */ + if ((i.types[0] & RegXMM) != 0 + && (i.types[1] & RegXMM) != 0 + && (i.types[2] & RegXMM) != 0) + { + /* Clear the arguments that are stored in drex. */ + i.types[2] = 0; + i.reg_operands--; + + /* Specify the modrm encoding and remember the register including the + high bit normally stored in the REX byte. */ + i.tm.extension_opcode = DREX_XMEM_X1_X2; + i.drex.modrm_reg = 1; + i.drex.modrm_regmem = 0; + i.drex.reg = (i.op[2].regs->reg_num + + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0)); + } + + /* Case 2: 3 operand insn, src1 = memory. */ + else if ((i.types[0] & AnyMem) != 0 + && (i.types[1] & RegXMM) != 0 + && (i.types[2] & RegXMM) != 0) + { + /* Clear the arguments that are stored in drex. */ + i.types[2] = 0; + i.reg_operands--; + + /* Specify the modrm encoding and remember the register including the + high bit normally stored in the REX byte. */ + i.tm.extension_opcode = DREX_XMEM_X1_X2; + i.drex.modrm_reg = 1; + i.drex.modrm_regmem = 0; + i.drex.reg = (i.op[2].regs->reg_num + + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0)); + } + + /* Case 3: 3 operand insn, src2 = memory. */ + else if ((i.types[0] & RegXMM) != 0 + && (i.types[1] & AnyMem) != 0 + && (i.types[2] & RegXMM) != 0) + { + /* Clear the arguments that are stored in drex. */ + i.types[2] = 0; + i.reg_operands--; + + /* Specify the modrm encoding and remember the register including the + high bit normally stored in the REX byte. */ + i.tm.extension_opcode = DREX_X1_XMEM_X2; + i.drex.modrm_reg = 0; + i.drex.modrm_regmem = 1; + i.drex.reg = (i.op[2].regs->reg_num + + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0)); + } + + else + as_bad (_("Incorrect operands for the '%s' instruction"), i.tm.name); + } + + /* SSE5 4 operand instructions that are the comparison instructions where the + first operand is the immediate value of the comparison to be done. */ + else if ((i.tm.opcode_modifier2 & Drexc) != 0 && i.operands == 4) + { + /* Case 1: 4 operand insn, src1 = reg/memory. */ + if ((i.types[0] & Imm) != 0 + && (i.types[1] & (RegXMM | AnyMem)) != 0 + && (i.types[2] & RegXMM) != 0 + && (i.types[3] & RegXMM) != 0) + { + /* clear the arguments that are stored in drex */ + i.types[3] = 0; + i.reg_operands--; + + /* Specify the modrm encoding and remember the register including the + high bit normally stored in the REX byte. */ + i.drex.modrm_reg = 2; + i.drex.modrm_regmem = 1; + i.drex.reg = (i.op[3].regs->reg_num + + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); + } + + /* Case 2: 3 operand insn with ImmExt that places the opcode_extension as + an immediate argument. This is used for all of the varients of + comparison that supplies the appropriate value as part of the + instruction. */ + else if ((i.types[0] & (RegXMM | AnyMem)) != 0 + && (i.types[1] & RegXMM) != 0 + && (i.types[2] & RegXMM) != 0 + && (i.types[3] & Imm) != 0) + { + /* clear the arguments that are stored in drex */ + i.types[2] = 0; + i.reg_operands--; + + /* Specify the modrm encoding and remember the register including the + high bit normally stored in the REX byte. */ + i.drex.modrm_reg = 1; + i.drex.modrm_regmem = 0; + i.drex.reg = (i.op[2].regs->reg_num + + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0)); + } + + else + as_bad (_("Incorrect operands for the '%s' instruction"), i.tm.name); + } + + else if (i.tm.opcode_modifier2 & (Drex|Drexv|Drexc)) + as_bad (_("Internal error for the '%s' instruction"), i.tm.name); + } + static int process_operands (void) { *************** process_operands (void) *** 3368,3373 **** --- 3693,3702 ---- unnecessary segment overrides. */ const seg_entry *default_seg = 0; + /* Handle all of the DREX munging that SSE5 needs. */ + if (i.tm.opcode_modifier2 & (Drex|Drexv|Drexc)) + process_drex (); + /* The imul $imm, %reg instruction is converted into imul $imm, %reg, %reg, and the clr %reg instruction is converted into xor %reg, %reg. */ *************** build_modrm_byte (void) *** 3500,3508 **** { const seg_entry *default_seg = 0; /* i.reg_operands MUST be the number of real register operands; implicit registers do not count. */ ! if (i.reg_operands == 2) { unsigned int source, dest; --- 3829,3855 ---- { const seg_entry *default_seg = 0; + /* SSE5 4 operand instructions are encoded in such a way that one of the + inputs must match the destination register. Process_drex hides the 3rd + argument in the drex field, so that by the time we get here, it looks to + GAS as if this is a 2 operand instruction. */ + if ((i.tm.opcode_modifier2 & (Drex|Drexv|Drexc)) != 0 && i.reg_operands == 2) + { + const reg_entry *reg = i.op[i.drex.modrm_reg].regs; + const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs; + + i.rm.reg = reg->reg_num; + i.rm.regmem = regmem->reg_num; + i.rm.mode = 3; + if ((reg->reg_flags & RegRex) != 0) + i.rex |= REX_R; + if ((regmem->reg_flags & RegRex) != 0) + i.rex |= REX_B; + } + /* i.reg_operands MUST be the number of real register operands; implicit registers do not count. */ ! else if (i.reg_operands == 2) { unsigned int source, dest; *************** build_modrm_byte (void) *** 3574,3583 **** unsigned int fake_zero_displacement = 0; unsigned int op; ! for (op = 0; op < i.operands; op++) ! if ((i.types[op] & AnyMem)) ! break; ! assert (op < i.operands); default_seg = &ds; --- 3921,3937 ---- unsigned int fake_zero_displacement = 0; unsigned int op; ! /* This has been precalculated for SSE5 instructions that have a DREX ! field earlier in process_drex. */ ! if ((i.tm.opcode_modifier2 & (Drex|Drexv|Drexc)) != 0) ! op = i.drex.modrm_regmem; ! else ! { ! for (op = 0; op < i.operands; op++) ! if ((i.types[op] & AnyMem)) ! break; ! assert (op < i.operands); ! } default_seg = &ds; *************** build_modrm_byte (void) *** 3750,3775 **** { unsigned int op; ! for (op = 0; op < i.operands; op++) ! if ((i.types[op] & (Reg | RegMMX | RegXMM ! | SReg2 | SReg3 ! | Control | Debug | Test))) ! break; ! assert (op < i.operands); ! ! /* If there is an extension opcode to put here, the register ! number must be put into the regmem field. */ ! if (i.tm.extension_opcode != None) { ! i.rm.regmem = i.op[op].regs->reg_num; if ((i.op[op].regs->reg_flags & RegRex) != 0) ! i.rex |= REX_B; } else { ! i.rm.reg = i.op[op].regs->reg_num; ! if ((i.op[op].regs->reg_flags & RegRex) != 0) ! i.rex |= REX_R; } /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we --- 4104,4141 ---- { unsigned int op; ! /* This has been precalculated for SSE5 instructions that have a DREX ! field earlier in process_drex. */ ! if ((i.tm.opcode_modifier2 & (Drex|Drexv|Drexc)) != 0) { ! op = i.drex.modrm_reg; ! i.rm.reg = i.op[op].regs->reg_num; if ((i.op[op].regs->reg_flags & RegRex) != 0) ! i.rex |= REX_R; } else { ! for (op = 0; op < i.operands; op++) ! if ((i.types[op] & (Reg | RegMMX | RegXMM ! | SReg2 | SReg3 ! | Control | Debug | Test))) ! break; ! assert (op < i.operands); ! ! /* If there is an extension opcode to put here, the register ! number must be put into the regmem field. */ ! if (i.tm.extension_opcode != None) ! { ! i.rm.regmem = i.op[op].regs->reg_num; ! if ((i.op[op].regs->reg_flags & RegRex) != 0) ! i.rex |= REX_B; ! } ! else ! { ! i.rm.reg = i.op[op].regs->reg_num; ! if ((i.op[op].regs->reg_flags & RegRex) != 0) ! i.rex |= REX_R; ! } } /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we *************** build_modrm_byte (void) *** 3780,3786 **** } /* Fill in i.rm.reg field with extension opcode (if any). */ ! if (i.tm.extension_opcode != None) i.rm.reg = i.tm.extension_opcode; } return default_seg; --- 4146,4153 ---- } /* Fill in i.rm.reg field with extension opcode (if any). */ ! if (i.tm.extension_opcode != None ! && (i.tm.opcode_modifier2 & (Drex|Drexv|Drexc)) == 0) i.rm.reg = i.tm.extension_opcode; } return default_seg; *************** output_insn (void) *** 4022,4032 **** unsigned char *q; unsigned int prefix; ! /* All opcodes on i386 have either 1 or 2 bytes. SSSE3 and ! SSE4 instructions have 3 bytes. We may use one more higher ! byte to specify a prefix the instruction requires. Exclude ! instructions which are in both SSE4 and ABM. */ ! if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4)) != 0 && (i.tm.cpu_flags & CpuABM) == 0) { if (i.tm.base_opcode & 0xff000000) --- 4389,4399 ---- unsigned char *q; unsigned int prefix; ! /* All opcodes on i386 have either 1 or 2 bytes. SSSE3, SSE4, and SSE5 ! instructions have 3 bytes. We may use one more higher byte to specify ! a prefix the instruction requires. Exclude instructions which are in ! both SSE4 and ABM. */ ! if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4 | CpuSSE5)) != 0 && (i.tm.cpu_flags & CpuABM) == 0) { if (i.tm.base_opcode & 0xff000000) *************** output_insn (void) *** 4068,4074 **** } else { ! if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4)) != 0 && (i.tm.cpu_flags & CpuABM) == 0) { p = frag_more (3); --- 4435,4441 ---- } else { ! if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4 | CpuSSE5)) != 0 && (i.tm.cpu_flags & CpuABM) == 0) { p = frag_more (3); *************** output_insn (void) *** 4080,4085 **** --- 4447,4458 ---- /* Put out high byte first: can't use md_number_to_chars! */ *p++ = (i.tm.base_opcode >> 8) & 0xff; *p = i.tm.base_opcode & 0xff; + + /* On SSE5, encode the OC1 bit in the DREX field if this encoding has + multiple formats. */ + if (((i.tm.opcode_modifier2 & (Drex|Drexv)) == (Drex|Drexv)) + && DREX_OC1 (i.tm.extension_opcode)) + *p |= DREX_OC1_MASK; } /* Now the modrm byte and sib byte (if present). */ *************** output_insn (void) *** 4108,4113 **** --- 4481,4498 ---- } } + /* Write the DREX byte if needed. */ + if (i.tm.opcode_modifier2 & (Drex|Drexc)) + { + p = frag_more (1); + *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7)); + + /* Encode the OC0 bit if this encoding has multiple formats. */ + if (((i.tm.opcode_modifier2 & (Drex|Drexv)) == (Drex|Drexv)) + && DREX_OC0 (i.tm.extension_opcode)) + *p |= DREX_OC0_MASK; + } + if (i.disp_operands) output_disp (insn_start_frag, insn_start_off); *** gas/config/tc-i386.h.~1~ 2007-08-31 11:40:00.890290000 -0400 --- gas/config/tc-i386.h 2007-08-31 11:35:24.217961000 -0400 *************** modrm_byte; *** 153,158 **** --- 153,185 ---- /* x86-64 extension prefix. */ typedef int rex_byte; + /* The SSE5 instructions have a two bit instruction modifier (OC) that is + stored in two separate bytes in the instruction. Pick apart OC into the 2 + separate bits for instruction. */ + #define DREX_OC0(x) (((x) & 1) != 0) + #define DREX_OC1(x) (((x) & 2) != 0) + + #define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */ + #define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */ + + /* OC mappings */ + #define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */ + #define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */ + #define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */ + #define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */ + + #define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */ + #define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */ + + /* Information needed to create the DREX byte in SSE5 instructions. */ + typedef struct + { + unsigned int reg; /* register */ + unsigned int rex; /* REX flags */ + unsigned int modrm_reg; /* which arg goes in the modrm.reg field */ + unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */ + } drex_byte; + /* 386 opcode byte to code indirect addressing. */ typedef struct { *** gas/testsuite/gas/i386/i386.exp.~1~ 2007-08-31 11:40:00.944242000 -0400 --- gas/testsuite/gas/i386/i386.exp 2007-08-30 19:19:07.848276000 -0400 *************** if [expr ([istarget "i*86-*-*"] || [ista *** 191,196 **** --- 191,197 ---- run_list_test "x86-64-inval-crc32" "-al" run_dump_test "x86-64-simd" run_dump_test "x86-64-simd-intel" + run_dump_test "x86-64-sse5" run_dump_test "x86-64-mem" run_dump_test "x86-64-mem-intel" run_dump_test "x86-64-reg" *** gas/testsuite/gas/i386/x86-64-sse5.s.~1~ 2007-08-31 11:40:00.966723000 -0400 --- gas/testsuite/gas/i386/x86-64-sse5.s 2007-08-17 15:16:13.661437000 -0400 *************** *** 0 **** --- 1,2970 ---- + # SSE5 instructions. + + .file "x86-64-sse5.s" + .globl foo + .type foo, @function + .text + .p2align 5,,31 + .att_syntax + foo: + + fmaddss %xmm3, %xmm2, %xmm1, %xmm1 + fmaddss 0x4(%rdx), %xmm2, %xmm1, %xmm1 + fmaddss %xmm2, 0x4(%rdx), %xmm1, %xmm1 + fmaddss %xmm1, %xmm3, %xmm2, %xmm1 + fmaddss %xmm1, 0x4(%rdx), %xmm2, %xmm1 + fmaddss %xmm1, %xmm2, 0x4(%rdx), %xmm1 + fmaddsd %xmm3, %xmm2, %xmm1, %xmm1 + fmaddsd 0x4(%rdx), %xmm2, %xmm1, %xmm1 + fmaddsd %xmm2, 0x4(%rdx), %xmm1, %xmm1 + fmaddsd %xmm1, %xmm3, %xmm2, %xmm1 + fmaddsd %xmm1, 0x4(%rdx), %xmm2, %xmm1 + fmaddsd %xmm1, %xmm2, 0x4(%rdx), %xmm1 + fmaddps %xmm3, %xmm2, %xmm1, %xmm1 + fmaddps 0x4(%rdx), %xmm2, %xmm1, %xmm1 + fmaddps %xmm2, 0x4(%rdx), %xmm1, %xmm1 + fmaddps %xmm1, %xmm3, %xmm2, %xmm1 + fmaddps %xmm1, 0x4(%rdx), %xmm2, %xmm1 + fmaddps %xmm1, %xmm2, 0x4(%rdx), %xmm1 + fmaddpd %xmm3, %xmm2, %xmm1, %xmm1 + fmaddpd 0x4(%rdx), %xmm2, %xmm1, %xmm1 + fmaddpd %xmm2, 0x4(%rdx), %xmm1, %xmm1 + fmaddpd %xmm1, %xmm3, %xmm2, %xmm1 + fmaddpd %xmm1, 0x4(%rdx), %xmm2, %xmm1 + fmaddpd %xmm1, %xmm2, 0x4(%rdx), %xmm1 + + fmsubss %xmm3, %xmm2, %xmm1, %xmm1 + fmsubss 0x4(%rdx), %xmm2, %xmm1, %xmm1 + fmsubss %xmm2, 0x4(%rdx), %xmm1, %xmm1 + fmsubss %xmm1, %xmm3, %xmm2, %xmm1 + fmsubss %xmm1, 0x4(%rdx), %xmm2, %xmm1 + fmsubss %xmm1, %xmm2, 0x4(%rdx), %xmm1 + fmsubsd %xmm3, %xmm2, %xmm1, %xmm1 + fmsubsd 0x4(%rdx), %xmm2, %xmm1, %xmm1 + fmsubsd %xmm2, 0x4(%rdx), %xmm1, %xmm1 + fmsubsd %xmm1, %xmm3, %xmm2, %xmm1 + fmsubsd %xmm1, 0x4(%rdx), %xmm2, %xmm1 + fmsubsd %xmm1, %xmm2, 0x4(%rdx), %xmm1 + fmsubps %xmm3, %xmm2, %xmm1, %xmm1 + fmsubps 0x4(%rdx), %xmm2, %xmm1, %xmm1 + fmsubps %xmm2, 0x4(%rdx), %xmm1, %xmm1 + fmsubps %xmm1, %xmm3, %xmm2, %xmm1 + fmsubps %xmm1, 0x4(%rdx), %xmm2, %xmm1 + fmsubps %xmm1, %xmm2, 0x4(%rdx), %xmm1 + fmsubpd %xmm3, %xmm2, %xmm1, %xmm1 + fmsubpd 0x4(%rdx), %xmm2, %xmm1, %xmm1 + fmsubpd %xmm2, 0x4(%rdx), %xmm1, %xmm1 + fmsubpd %xmm1, %xmm3, %xmm2, %xmm1 + fmsubpd %xmm1, 0x4(%rdx), %xmm2, %xmm1 + fmsubpd %xmm1, %xmm2, 0x4(%rdx), %xmm1 + + fnmaddss %xmm3, %xmm2, %xmm1, %xmm1 + fnmaddss 0x4(%rdx), %xmm2, %xmm1, %xmm1 + fnmaddss %xmm2, 0x4(%rdx), %xmm1, %xmm1 + fnmaddss %xmm1, %xmm3, %xmm2, %xmm1 + fnmaddss %xmm1, 0x4(%rdx), %xmm2, %xmm1 + fnmaddss %xmm1, %xmm2, 0x4(%rdx), %xmm1 + fnmaddsd %xmm3, %xmm2, %xmm1, %xmm1 + fnmaddsd 0x4(%rdx), %xmm2, %xmm1, %xmm1 + fnmaddsd %xmm2, 0x4(%rdx), %xmm1, %xmm1 + fnmaddsd %xmm1, %xmm3, %xmm2, %xmm1 + fnmaddsd %xmm1, 0x4(%rdx), %xmm2, %xmm1 + fnmaddsd %xmm1, %xmm2, 0x4(%rdx), %xmm1 + fnmaddps %xmm3, %xmm2, %xmm1, %xmm1 + fnmaddps 0x4(%rdx), %xmm2, %xmm1, %xmm1 + fnmaddps %xmm2, 0x4(%rdx), %xmm1, %xmm1 + fnmaddps %xmm1, %xmm3, %xmm2, %xmm1 + fnmaddps %xmm1, 0x4(%rdx), %xmm2, %xmm1 + fnmaddps %xmm1, %xmm2, 0x4(%rdx), %xmm1 + fnmaddpd %xmm3, %xmm2, %xmm1, %xmm1 + fnmaddpd 0x4(%rdx), %xmm2, %xmm1, %xmm1 + fnmaddpd %xmm2, 0x4(%rdx), %xmm1, %xmm1 + fnmaddpd %xmm1, %xmm3, %xmm2, %xmm1 + fnmaddpd %xmm1, 0x4(%rdx), %xmm2, %xmm1 + fnmaddpd %xmm1, %xmm2, 0x4(%rdx), %xmm1 + + fnmsubss %xmm3, %xmm2, %xmm1, %xmm1 + fnmsubss 0x4(%rdx), %xmm2, %xmm1, %xmm1 + fnmsubss %xmm2, 0x4(%rdx), %xmm1, %xmm1 + fnmsubss %xmm1, %xmm3, %xmm2, %xmm1 + fnmsubss %xmm1, 0x4(%rdx), %xmm2, %xmm1 + fnmsubss %xmm1, %xmm2, 0x4(%rdx), %xmm1 + fnmsubsd %xmm3, %xmm2, %xmm1, %xmm1 + fnmsubsd 0x4(%rdx), %xmm2, %xmm1, %xmm1 + fnmsubsd %xmm2, 0x4(%rdx), %xmm1, %xmm1 + fnmsubsd %xmm1, %xmm3, %xmm2, %xmm1 + fnmsubsd %xmm1, 0x4(%rdx), %xmm2, %xmm1 + fnmsubsd %xmm1, %xmm2, 0x4(%rdx), %xmm1 + fnmsubps %xmm3, %xmm2, %xmm1, %xmm1 + fnmsubps 0x4(%rdx), %xmm2, %xmm1, %xmm1 + fnmsubps %xmm2, 0x4(%rdx), %xmm1, %xmm1 + fnmsubps %xmm1, %xmm3, %xmm2, %xmm1 + fnmsubps %xmm1, 0x4(%rdx), %xmm2, %xmm1 + fnmsubps %xmm1, %xmm2, 0x4(%rdx), %xmm1 + fnmsubpd %xmm3, %xmm2, %xmm1, %xmm1 + fnmsubpd 0x4(%rdx), %xmm2, %xmm1, %xmm1 + fnmsubpd %xmm2, 0x4(%rdx), %xmm1, %xmm1 + fnmsubpd %xmm1, %xmm3, %xmm2, %xmm1 + fnmsubpd %xmm1, 0x4(%rdx), %xmm2, %xmm1 + fnmsubpd %xmm1, %xmm2, 0x4(%rdx), %xmm1 + + fmaddss %xmm13, %xmm12, %xmm11, %xmm11 + fmaddss 0x100000(%r15), %xmm12, %xmm11, %xmm11 + fmaddss %xmm12, 0x100000(%r15), %xmm11, %xmm11 + fmaddss %xmm11, %xmm13, %xmm12, %xmm11 + fmaddss %xmm11, 0x100000(%r15), %xmm12, %xmm11 + fmaddss %xmm11, %xmm12, 0x100000(%r15), %xmm11 + fmaddsd %xmm13, %xmm12, %xmm11, %xmm11 + fmaddsd 0x100000(%r15), %xmm12, %xmm11, %xmm11 + fmaddsd %xmm12, 0x100000(%r15), %xmm11, %xmm11 + fmaddsd %xmm11, %xmm13, %xmm12, %xmm11 + fmaddsd %xmm11, 0x100000(%r15), %xmm12, %xmm11 + fmaddsd %xmm11, %xmm12, 0x100000(%r15), %xmm11 + fmaddps %xmm13, %xmm12, %xmm11, %xmm11 + fmaddps 0x100000(%r15), %xmm12, %xmm11, %xmm11 + fmaddps %xmm12, 0x100000(%r15), %xmm11, %xmm11 + fmaddps %xmm11, %xmm13, %xmm12, %xmm11 + fmaddps %xmm11, 0x100000(%r15), %xmm12, %xmm11 + fmaddps %xmm11, %xmm12, 0x100000(%r15), %xmm11 + fmaddpd %xmm13, %xmm12, %xmm11, %xmm11 + fmaddpd 0x100000(%r15), %xmm12, %xmm11, %xmm11 + fmaddpd %xmm12, 0x100000(%r15), %xmm11, %xmm11 + fmaddpd %xmm11, %xmm13, %xmm12, %xmm11 + fmaddpd %xmm11, 0x100000(%r15), %xmm12, %xmm11 + fmaddpd %xmm11, %xmm12, 0x100000(%r15), %xmm11 + + fmsubss %xmm13, %xmm12, %xmm11, %xmm11 + fmsubss 0x100000(%r15), %xmm12, %xmm11, %xmm11 + fmsubss %xmm12, 0x100000(%r15), %xmm11, %xmm11 + fmsubss %xmm11, %xmm13, %xmm12, %xmm11 + fmsubss %xmm11, 0x100000(%r15), %xmm12, %xmm11 + fmsubss %xmm11, %xmm12, 0x100000(%r15), %xmm11 + fmsubsd %xmm13, %xmm12, %xmm11, %xmm11 + fmsubsd 0x100000(%r15), %xmm12, %xmm11, %xmm11 + fmsubsd %xmm12, 0x100000(%r15), %xmm11, %xmm11 + fmsubsd %xmm11, %xmm13, %xmm12, %xmm11 + fmsubsd %xmm11, 0x100000(%r15), %xmm12, %xmm11 + fmsubsd %xmm11, %xmm12, 0x100000(%r15), %xmm11 + fmsubps %xmm13, %xmm12, %xmm11, %xmm11 + fmsubps 0x100000(%r15), %xmm12, %xmm11, %xmm11 + fmsubps %xmm12, 0x100000(%r15), %xmm11, %xmm11 + fmsubps %xmm11, %xmm13, %xmm12, %xmm11 + fmsubps %xmm11, 0x100000(%r15), %xmm12, %xmm11 + fmsubps %xmm11, %xmm12, 0x100000(%r15), %xmm11 + fmsubpd %xmm13, %xmm12, %xmm11, %xmm11 + fmsubpd 0x100000(%r15), %xmm12, %xmm11, %xmm11 + fmsubpd %xmm12, 0x100000(%r15), %xmm11, %xmm11 + fmsubpd %xmm11, %xmm13, %xmm12, %xmm11 + fmsubpd %xmm11, 0x100000(%r15), %xmm12, %xmm11 + fmsubpd %xmm11, %xmm12, 0x100000(%r15), %xmm11 + + fnmaddss %xmm13, %xmm12, %xmm11, %xmm11 + fnmaddss 0x100000(%r15), %xmm12, %xmm11, %xmm11 + fnmaddss %xmm12, 0x100000(%r15), %xmm11, %xmm11 + fnmaddss %xmm11, %xmm13, %xmm12, %xmm11 + fnmaddss %xmm11, 0x100000(%r15), %xmm12, %xmm11 + fnmaddss %xmm11, %xmm12, 0x100000(%r15), %xmm11 + fnmaddsd %xmm13, %xmm12, %xmm11, %xmm11 + fnmaddsd 0x100000(%r15), %xmm12, %xmm11, %xmm11 + fnmaddsd %xmm12, 0x100000(%r15), %xmm11, %xmm11 + fnmaddsd %xmm11, %xmm13, %xmm12, %xmm11 + fnmaddsd %xmm11, 0x100000(%r15), %xmm12, %xmm11 + fnmaddsd %xmm11, %xmm12, 0x100000(%r15), %xmm11 + fnmaddps %xmm13, %xmm12, %xmm11, %xmm11 + fnmaddps 0x100000(%r15), %xmm12, %xmm11, %xmm11 + fnmaddps %xmm12, 0x100000(%r15), %xmm11, %xmm11 + fnmaddps %xmm11, %xmm13, %xmm12, %xmm11 + fnmaddps %xmm11, 0x100000(%r15), %xmm12, %xmm11 + fnmaddps %xmm11, %xmm12, 0x100000(%r15), %xmm11 + fnmaddpd %xmm13, %xmm12, %xmm11, %xmm11 + fnmaddpd 0x100000(%r15), %xmm12, %xmm11, %xmm11 + fnmaddpd %xmm12, 0x100000(%r15), %xmm11, %xmm11 + fnmaddpd %xmm11, %xmm13, %xmm12, %xmm11 + fnmaddpd %xmm11, 0x100000(%r15), %xmm12, %xmm11 + fnmaddpd %xmm11, %xmm12, 0x100000(%r15), %xmm11 + + fnmsubss %xmm13, %xmm12, %xmm11, %xmm11 + fnmsubss 0x100000(%r15), %xmm12, %xmm11, %xmm11 + fnmsubss %xmm12, 0x100000(%r15), %xmm11, %xmm11 + fnmsubss %xmm11, %xmm13, %xmm12, %xmm11 + fnmsubss %xmm11, 0x100000(%r15), %xmm12, %xmm11 + fnmsubss %xmm11, %xmm12, 0x100000(%r15), %xmm11 + fnmsubsd %xmm13, %xmm12, %xmm11, %xmm11 + fnmsubsd 0x100000(%r15), %xmm12, %xmm11, %xmm11 + fnmsubsd %xmm12, 0x100000(%r15), %xmm11, %xmm11 + fnmsubsd %xmm11, %xmm13, %xmm12, %xmm11 + fnmsubsd %xmm11, 0x100000(%r15), %xmm12, %xmm11 + fnmsubsd %xmm11, %xmm12, 0x100000(%r15), %xmm11 + fnmsubps %xmm13, %xmm12, %xmm11, %xmm11 + fnmsubps 0x100000(%r15), %xmm12, %xmm11, %xmm11 + fnmsubps %xmm12, 0x100000(%r15), %xmm11, %xmm11 + fnmsubps %xmm11, %xmm13, %xmm12, %xmm11 + fnmsubps %xmm11, 0x100000(%r15), %xmm12, %xmm11 + fnmsubps %xmm11, %xmm12, 0x100000(%r15), %xmm11 + fnmsubpd %xmm13, %xmm12, %xmm11, %xmm11 + fnmsubpd 0x100000(%r15), %xmm12, %xmm11, %xmm11 + fnmsubpd %xmm12, 0x100000(%r15), %xmm11, %xmm11 + fnmsubpd %xmm11, %xmm13, %xmm12, %xmm11 + fnmsubpd %xmm11, 0x100000(%r15), %xmm12, %xmm11 + fnmsubpd %xmm11, %xmm12, 0x100000(%r15), %xmm11 + + fmaddss %xmm3, %xmm12, %xmm1, %xmm1 + fmaddss 0x4(%rdx), %xmm12, %xmm1, %xmm1 + fmaddss %xmm12, 0x4(%rdx), %xmm1, %xmm1 + fmaddss %xmm1, %xmm3, %xmm12, %xmm1 + fmaddss %xmm1, 0x4(%rdx), %xmm12, %xmm1 + fmaddss %xmm1, %xmm12, 0x4(%rdx), %xmm1 + fmaddsd %xmm3, %xmm12, %xmm1, %xmm1 + fmaddsd 0x4(%rdx), %xmm12, %xmm1, %xmm1 + fmaddsd %xmm12, 0x4(%rdx), %xmm1, %xmm1 + fmaddsd %xmm1, %xmm3, %xmm12, %xmm1 + fmaddsd %xmm1, 0x4(%rdx), %xmm12, %xmm1 + fmaddsd %xmm1, %xmm12, 0x4(%rdx), %xmm1 + fmaddps %xmm3, %xmm12, %xmm1, %xmm1 + fmaddps 0x4(%rdx), %xmm12, %xmm1, %xmm1 + fmaddps %xmm12, 0x4(%rdx), %xmm1, %xmm1 + fmaddps %xmm1, %xmm3, %xmm12, %xmm1 + fmaddps %xmm1, 0x4(%rdx), %xmm12, %xmm1 + fmaddps %xmm1, %xmm12, 0x4(%rdx), %xmm1 + fmaddpd %xmm3, %xmm12, %xmm1, %xmm1 + fmaddpd 0x4(%rdx), %xmm12, %xmm1, %xmm1 + fmaddpd %xmm12, 0x4(%rdx), %xmm1, %xmm1 + fmaddpd %xmm1, %xmm3, %xmm12, %xmm1 + fmaddpd %xmm1, 0x4(%rdx), %xmm12, %xmm1 + fmaddpd %xmm1, %xmm12, 0x4(%rdx), %xmm1 + + fmsubss %xmm3, %xmm12, %xmm1, %xmm1 + fmsubss 0x4(%rdx), %xmm12, %xmm1, %xmm1 + fmsubss %xmm12, 0x4(%rdx), %xmm1, %xmm1 + fmsubss %xmm1, %xmm3, %xmm12, %xmm1 + fmsubss %xmm1, 0x4(%rdx), %xmm12, %xmm1 + fmsubss %xmm1, %xmm12, 0x4(%rdx), %xmm1 + fmsubsd %xmm3, %xmm12, %xmm1, %xmm1 + fmsubsd 0x4(%rdx), %xmm12, %xmm1, %xmm1 + fmsubsd %xmm12, 0x4(%rdx), %xmm1, %xmm1 + fmsubsd %xmm1, %xmm3, %xmm12, %xmm1 + fmsubsd %xmm1, 0x4(%rdx), %xmm12, %xmm1 + fmsubsd %xmm1, %xmm12, 0x4(%rdx), %xmm1 + fmsubps %xmm3, %xmm12, %xmm1, %xmm1 + fmsubps 0x4(%rdx), %xmm12, %xmm1, %xmm1 + fmsubps %xmm12, 0x4(%rdx), %xmm1, %xmm1 + fmsubps %xmm1, %xmm3, %xmm12, %xmm1 + fmsubps %xmm1, 0x4(%rdx), %xmm12, %xmm1 + fmsubps %xmm1, %xmm12, 0x4(%rdx), %xmm1 + fmsubpd %xmm3, %xmm12, %xmm1, %xmm1 + fmsubpd 0x4(%rdx), %xmm12, %xmm1, %xmm1 + fmsubpd %xmm12, 0x4(%rdx), %xmm1, %xmm1 + fmsubpd %xmm1, %xmm3, %xmm12, %xmm1 + fmsubpd %xmm1, 0x4(%rdx), %xmm12, %xmm1 + fmsubpd %xmm1, %xmm12, 0x4(%rdx), %xmm1 + + fnmaddss %xmm3, %xmm12, %xmm1, %xmm1 + fnmaddss 0x4(%rdx), %xmm12, %xmm1, %xmm1 + fnmaddss %xmm12, 0x4(%rdx), %xmm1, %xmm1 + fnmaddss %xmm1, %xmm3, %xmm12, %xmm1 + fnmaddss %xmm1, 0x4(%rdx), %xmm12, %xmm1 + fnmaddss %xmm1, %xmm12, 0x4(%rdx), %xmm1 + fnmaddsd %xmm3, %xmm12, %xmm1, %xmm1 + fnmaddsd 0x4(%rdx), %xmm12, %xmm1, %xmm1 + fnmaddsd %xmm12, 0x4(%rdx), %xmm1, %xmm1 + fnmaddsd %xmm1, %xmm3, %xmm12, %xmm1 + fnmaddsd %xmm1, 0x4(%rdx), %xmm12, %xmm1 + fnmaddsd %xmm1, %xmm12, 0x4(%rdx), %xmm1 + fnmaddps %xmm3, %xmm12, %xmm1, %xmm1 + fnmaddps 0x4(%rdx), %xmm12, %xmm1, %xmm1 + fnmaddps %xmm12, 0x4(%rdx), %xmm1, %xmm1 + fnmaddps %xmm1, %xmm3, %xmm12, %xmm1 + fnmaddps %xmm1, 0x4(%rdx), %xmm12, %xmm1 + fnmaddps %xmm1, %xmm12, 0x4(%rdx), %xmm1 + fnmaddpd %xmm3, %xmm12, %xmm1, %xmm1 + fnmaddpd 0x4(%rdx), %xmm12, %xmm1, %xmm1 + fnmaddpd %xmm12, 0x4(%rdx), %xmm1, %xmm1 + fnmaddpd %xmm1, %xmm3, %xmm12, %xmm1 + fnmaddpd %xmm1, 0x4(%rdx), %xmm12, %xmm1 + fnmaddpd %xmm1, %xmm12, 0x4(%rdx), %xmm1 + + fnmsubss %xmm3, %xmm12, %xmm1, %xmm1 + fnmsubss 0x4(%rdx), %xmm12, %xmm1, %xmm1 + fnmsubss %xmm12, 0x4(%rdx), %xmm1, %xmm1 + fnmsubss %xmm1, %xmm3, %xmm12, %xmm1 + fnmsubss %xmm1, 0x4(%rdx), %xmm12, %xmm1 + fnmsubss %xmm1, %xmm12, 0x4(%rdx), %xmm1 + fnmsubsd %xmm3, %xmm12, %xmm1, %xmm1 + fnmsubsd 0x4(%rdx), %xmm12, %xmm1, %xmm1 + fnmsubsd %xmm12, 0x4(%rdx), %xmm1, %xmm1 + fnmsubsd %xmm1, %xmm3, %xmm12, %xmm1 + fnmsubsd %xmm1, 0x4(%rdx), %xmm12, %xmm1 + fnmsubsd %xmm1, %xmm12, 0x4(%rdx), %xmm1 + fnmsubps %xmm3, %xmm12, %xmm1, %xmm1 + fnmsubps 0x4(%rdx), %xmm12, %xmm1, %xmm1 + fnmsubps %xmm12, 0x4(%rdx), %xmm1, %xmm1 + fnmsubps %xmm1, %xmm3, %xmm12, %xmm1 + fnmsubps %xmm1, 0x4(%rdx), %xmm12, %xmm1 + fnmsubps %xmm1, %xmm12, 0x4(%rdx), %xmm1 + fnmsubpd %xmm3, %xmm12, %xmm1, %xmm1 + fnmsubpd 0x4(%rdx), %xmm12, %xmm1, %xmm1 + fnmsubpd %xmm12, 0x4(%rdx), %xmm1, %xmm1 + fnmsubpd %xmm1, %xmm3, %xmm12, %xmm1 + fnmsubpd %xmm1, 0x4(%rdx), %xmm12, %xmm1 + fnmsubpd %xmm1, %xmm12, 0x4(%rdx), %xmm1 + + fmaddss %xmm3, %xmm2, %xmm11, %xmm11 + fmaddss 0x4(%rdx), %xmm2, %xmm11, %xmm11 + fmaddss %xmm2, 0x4(%rdx), %xmm11, %xmm11 + fmaddss %xmm11, %xmm3, %xmm2, %xmm11 + fmaddss %xmm11, 0x4(%rdx), %xmm2, %xmm11 + fmaddss %xmm11, %xmm2, 0x4(%rdx), %xmm11 + fmaddsd %xmm3, %xmm2, %xmm11, %xmm11 + fmaddsd 0x4(%rdx), %xmm2, %xmm11, %xmm11 + fmaddsd %xmm2, 0x4(%rdx), %xmm11, %xmm11 + fmaddsd %xmm11, %xmm3, %xmm2, %xmm11 + fmaddsd %xmm11, 0x4(%rdx), %xmm2, %xmm11 + fmaddsd %xmm11, %xmm2, 0x4(%rdx), %xmm11 + fmaddps %xmm3, %xmm2, %xmm11, %xmm11 + fmaddps 0x4(%rdx), %xmm2, %xmm11, %xmm11 + fmaddps %xmm2, 0x4(%rdx), %xmm11, %xmm11 + fmaddps %xmm11, %xmm3, %xmm2, %xmm11 + fmaddps %xmm11, 0x4(%rdx), %xmm2, %xmm11 + fmaddps %xmm11, %xmm2, 0x4(%rdx), %xmm11 + fmaddpd %xmm3, %xmm2, %xmm11, %xmm11 + fmaddpd 0x4(%rdx), %xmm2, %xmm11, %xmm11 + fmaddpd %xmm2, 0x4(%rdx), %xmm11, %xmm11 + fmaddpd %xmm11, %xmm3, %xmm2, %xmm11 + fmaddpd %xmm11, 0x4(%rdx), %xmm2, %xmm11 + fmaddpd %xmm11, %xmm2, 0x4(%rdx), %xmm11 + + fmsubss %xmm3, %xmm2, %xmm11, %xmm11 + fmsubss 0x4(%rdx), %xmm2, %xmm11, %xmm11 + fmsubss %xmm2, 0x4(%rdx), %xmm11, %xmm11 + fmsubss %xmm11, %xmm3, %xmm2, %xmm11 + fmsubss %xmm11, 0x4(%rdx), %xmm2, %xmm11 + fmsubss %xmm11, %xmm2, 0x4(%rdx), %xmm11 + fmsubsd %xmm3, %xmm2, %xmm11, %xmm11 + fmsubsd 0x4(%rdx), %xmm2, %xmm11, %xmm11 + fmsubsd %xmm2, 0x4(%rdx), %xmm11, %xmm11 + fmsubsd %xmm11, %xmm3, %xmm2, %xmm11 + fmsubsd %xmm11, 0x4(%rdx), %xmm2, %xmm11 + fmsubsd %xmm11, %xmm2, 0x4(%rdx), %xmm11 + fmsubps %xmm3, %xmm2, %xmm11, %xmm11 + fmsubps 0x4(%rdx), %xmm2, %xmm11, %xmm11 + fmsubps %xmm2, 0x4(%rdx), %xmm11, %xmm11 + fmsubps %xmm11, %xmm3, %xmm2, %xmm11 + fmsubps %xmm11, 0x4(%rdx), %xmm2, %xmm11 + fmsubps %xmm11, %xmm2, 0x4(%rdx), %xmm11 + fmsubpd %xmm3, %xmm2, %xmm11, %xmm11 + fmsubpd 0x4(%rdx), %xmm2, %xmm11, %xmm11 + fmsubpd %xmm2, 0x4(%rdx), %xmm11, %xmm11 + fmsubpd %xmm11, %xmm3, %xmm2, %xmm11 + fmsubpd %xmm11, 0x4(%rdx), %xmm2, %xmm11 + fmsubpd %xmm11, %xmm2, 0x4(%rdx), %xmm11 + + fnmaddss %xmm3, %xmm2, %xmm11, %xmm11 + fnmaddss 0x4(%rdx), %xmm2, %xmm11, %xmm11 + fnmaddss %xmm2, 0x4(%rdx), %xmm11, %xmm11 + fnmaddss %xmm11, %xmm3, %xmm2, %xmm11 + fnmaddss %xmm11, 0x4(%rdx), %xmm2, %xmm11 + fnmaddss %xmm11, %xmm2, 0x4(%rdx), %xmm11 + fnmaddsd %xmm3, %xmm2, %xmm11, %xmm11 + fnmaddsd 0x4(%rdx), %xmm2, %xmm11, %xmm11 + fnmaddsd %xmm2, 0x4(%rdx), %xmm11, %xmm11 + fnmaddsd %xmm11, %xmm3, %xmm2, %xmm11 + fnmaddsd %xmm11, 0x4(%rdx), %xmm2, %xmm11 + fnmaddsd %xmm11, %xmm2, 0x4(%rdx), %xmm11 + fnmaddps %xmm3, %xmm2, %xmm11, %xmm11 + fnmaddps 0x4(%rdx), %xmm2, %xmm11, %xmm11 + fnmaddps %xmm2, 0x4(%rdx), %xmm11, %xmm11 + fnmaddps %xmm11, %xmm3, %xmm2, %xmm11 + fnmaddps %xmm11, 0x4(%rdx), %xmm2, %xmm11 + fnmaddps %xmm11, %xmm2, 0x4(%rdx), %xmm11 + fnmaddpd %xmm3, %xmm2, %xmm11, %xmm11 + fnmaddpd 0x4(%rdx), %xmm2, %xmm11, %xmm11 + fnmaddpd %xmm2, 0x4(%rdx), %xmm11, %xmm11 + fnmaddpd %xmm11, %xmm3, %xmm2, %xmm11 + fnmaddpd %xmm11, 0x4(%rdx), %xmm2, %xmm11 + fnmaddpd %xmm11, %xmm2, 0x4(%rdx), %xmm11 + + fnmsubss %xmm3, %xmm2, %xmm11, %xmm11 + fnmsubss 0x4(%rdx), %xmm2, %xmm11, %xmm11 + fnmsubss %xmm2, 0x4(%rdx), %xmm11, %xmm11 + fnmsubss %xmm11, %xmm3, %xmm2, %xmm11 + fnmsubss %xmm11, 0x4(%rdx), %xmm2, %xmm11 + fnmsubss %xmm11, %xmm2, 0x4(%rdx), %xmm11 + fnmsubsd %xmm3, %xmm2, %xmm11, %xmm11 + fnmsubsd 0x4(%rdx), %xmm2, %xmm11, %xmm11 + fnmsubsd %xmm2, 0x4(%rdx), %xmm11, %xmm11 + fnmsubsd %xmm11, %xmm3, %xmm2, %xmm11 + fnmsubsd %xmm11, 0x4(%rdx), %xmm2, %xmm11 + fnmsubsd %xmm11, %xmm2, 0x4(%rdx), %xmm11 + fnmsubps %xmm3, %xmm2, %xmm11, %xmm11 + fnmsubps 0x4(%rdx), %xmm2, %xmm11, %xmm11 + fnmsubps %xmm2, 0x4(%rdx), %xmm11, %xmm11 + fnmsubps %xmm11, %xmm3, %xmm2, %xmm11 + fnmsubps %xmm11, 0x4(%rdx), %xmm2, %xmm11 + fnmsubps %xmm11, %xmm2, 0x4(%rdx), %xmm11 + fnmsubpd %xmm3, %xmm2, %xmm11, %xmm11 + fnmsubpd 0x4(%rdx), %xmm2, %xmm11, %xmm11 + fnmsubpd %xmm2, 0x4(%rdx), %xmm11, %xmm11 + fnmsubpd %xmm11, %xmm3, %xmm2, %xmm11 + fnmsubpd %xmm11, 0x4(%rdx), %xmm2, %xmm11 + fnmsubpd %xmm11, %xmm2, 0x4(%rdx), %xmm11 + + fmaddss %xmm13, %xmm2, %xmm1, %xmm1 + fmaddss 0x4(%rdx), %xmm2, %xmm1, %xmm1 + fmaddss %xmm2, 0x4(%rdx), %xmm1, %xmm1 + fmaddss %xmm1, %xmm13, %xmm2, %xmm1 + fmaddss %xmm1, 0x4(%rdx), %xmm2, %xmm1 + fmaddss %xmm1, %xmm2, 0x4(%rdx), %xmm1 + fmaddsd %xmm13, %xmm2, %xmm1, %xmm1 + fmaddsd 0x4(%rdx), %xmm2, %xmm1, %xmm1 + fmaddsd %xmm2, 0x4(%rdx), %xmm1, %xmm1 + fmaddsd %xmm1, %xmm13, %xmm2, %xmm1 + fmaddsd %xmm1, 0x4(%rdx), %xmm2, %xmm1 + fmaddsd %xmm1, %xmm2, 0x4(%rdx), %xmm1 + fmaddps %xmm13, %xmm2, %xmm1, %xmm1 + fmaddps 0x4(%rdx), %xmm2, %xmm1, %xmm1 + fmaddps %xmm2, 0x4(%rdx), %xmm1, %xmm1 + fmaddps %xmm1, %xmm13, %xmm2, %xmm1 + fmaddps %xmm1, 0x4(%rdx), %xmm2, %xmm1 + fmaddps %xmm1, %xmm2, 0x4(%rdx), %xmm1 + fmaddpd %xmm13, %xmm2, %xmm1, %xmm1 + fmaddpd 0x4(%rdx), %xmm2, %xmm1, %xmm1 + fmaddpd %xmm2, 0x4(%rdx), %xmm1, %xmm1 + fmaddpd %xmm1, %xmm13, %xmm2, %xmm1 + fmaddpd %xmm1, 0x4(%rdx), %xmm2, %xmm1 + fmaddpd %xmm1, %xmm2, 0x4(%rdx), %xmm1 + + fmsubss %xmm13, %xmm2, %xmm1, %xmm1 + fmsubss 0x4(%rdx), %xmm2, %xmm1, %xmm1 + fmsubss %xmm2, 0x4(%rdx), %xmm1, %xmm1 + fmsubss %xmm1, %xmm13, %xmm2, %xmm1 + fmsubss %xmm1, 0x4(%rdx), %xmm2, %xmm1 + fmsubss %xmm1, %xmm2, 0x4(%rdx), %xmm1 + fmsubsd %xmm13, %xmm2, %xmm1, %xmm1 + fmsubsd 0x4(%rdx), %xmm2, %xmm1, %xmm1 + fmsubsd %xmm2, 0x4(%rdx), %xmm1, %xmm1 + fmsubsd %xmm1, %xmm13, %xmm2, %xmm1 + fmsubsd %xmm1, 0x4(%rdx), %xmm2, %xmm1 + fmsubsd %xmm1, %xmm2, 0x4(%rdx), %xmm1 + fmsubps %xmm13, %xmm2, %xmm1, %xmm1 + fmsubps 0x4(%rdx), %xmm2, %xmm1, %xmm1 + fmsubps %xmm2, 0x4(%rdx), %xmm1, %xmm1 + fmsubps %xmm1, %xmm13, %xmm2, %xmm1 + fmsubps %xmm1, 0x4(%rdx), %xmm2, %xmm1 + fmsubps %xmm1, %xmm2, 0x4(%rdx), %xmm1 + fmsubpd %xmm13, %xmm2, %xmm1, %xmm1 + fmsubpd 0x4(%rdx), %xmm2, %xmm1, %xmm1 + fmsubpd %xmm2, 0x4(%rdx), %xmm1, %xmm1 + fmsubpd %xmm1, %xmm13, %xmm2, %xmm1 + fmsubpd %xmm1, 0x4(%rdx), %xmm2, %xmm1 + fmsubpd %xmm1, %xmm2, 0x4(%rdx), %xmm1 + + fnmaddss %xmm13, %xmm2, %xmm1, %xmm1 + fnmaddss 0x4(%rdx), %xmm2, %xmm1, %xmm1 + fnmaddss %xmm2, 0x4(%rdx), %xmm1, %xmm1 + fnmaddss %xmm1, %xmm13, %xmm2, %xmm1 + fnmaddss %xmm1, 0x4(%rdx), %xmm2, %xmm1 + fnmaddss %xmm1, %xmm2, 0x4(%rdx), %xmm1 + fnmaddsd %xmm13, %xmm2, %xmm1, %xmm1 + fnmaddsd 0x4(%rdx), %xmm2, %xmm1, %xmm1 + fnmaddsd %xmm2, 0x4(%rdx), %xmm1, %xmm1 + fnmaddsd %xmm1, %xmm13, %xmm2, %xmm1 + fnmaddsd %xmm1, 0x4(%rdx), %xmm2, %xmm1 + fnmaddsd %xmm1, %xmm2, 0x4(%rdx), %xmm1 + fnmaddps %xmm13, %xmm2, %xmm1, %xmm1 + fnmaddps 0x4(%rdx), %xmm2, %xmm1, %xmm1 + fnmaddps %xmm2, 0x4(%rdx), %xmm1, %xmm1 + fnmaddps %xmm1, %xmm13, %xmm2, %xmm1 + fnmaddps %xmm1, 0x4(%rdx), %xmm2, %xmm1 + fnmaddps %xmm1, %xmm2, 0x4(%rdx), %xmm1 + fnmaddpd %xmm13, %xmm2, %xmm1, %xmm1 + fnmaddpd 0x4(%rdx), %xmm2, %xmm1, %xmm1 + fnmaddpd %xmm2, 0x4(%rdx), %xmm1, %xmm1 + fnmaddpd %xmm1, %xmm13, %xmm2, %xmm1 + fnmaddpd %xmm1, 0x4(%rdx), %xmm2, %xmm1 + fnmaddpd %xmm1, %xmm2, 0x4(%rdx), %xmm1 + + fnmsubss %xmm13, %xmm2, %xmm1, %xmm1 + fnmsubss 0x4(%rdx), %xmm2, %xmm1, %xmm1 + fnmsubss %xmm2, 0x4(%rdx), %xmm1, %xmm1 + fnmsubss %xmm1, %xmm13, %xmm2, %xmm1 + fnmsubss %xmm1, 0x4(%rdx), %xmm2, %xmm1 + fnmsubss %xmm1, %xmm2, 0x4(%rdx), %xmm1 + fnmsubsd %xmm13, %xmm2, %xmm1, %xmm1 + fnmsubsd 0x4(%rdx), %xmm2, %xmm1, %xmm1 + fnmsubsd %xmm2, 0x4(%rdx), %xmm1, %xmm1 + fnmsubsd %xmm1, %xmm13, %xmm2, %xmm1 + fnmsubsd %xmm1, 0x4(%rdx), %xmm2, %xmm1 + fnmsubsd %xmm1, %xmm2, 0x4(%rdx), %xmm1 + fnmsubps %xmm13, %xmm2, %xmm1, %xmm1 + fnmsubps 0x4(%rdx), %xmm2, %xmm1, %xmm1 + fnmsubps %xmm2, 0x4(%rdx), %xmm1, %xmm1 + fnmsubps %xmm1, %xmm13, %xmm2, %xmm1 + fnmsubps %xmm1, 0x4(%rdx), %xmm2, %xmm1 + fnmsubps %xmm1, %xmm2, 0x4(%rdx), %xmm1 + fnmsubpd %xmm13, %xmm2, %xmm1, %xmm1 + fnmsubpd 0x4(%rdx), %xmm2, %xmm1, %xmm1 + fnmsubpd %xmm2, 0x4(%rdx), %xmm1, %xmm1 + fnmsubpd %xmm1, %xmm13, %xmm2, %xmm1 + fnmsubpd %xmm1, 0x4(%rdx), %xmm2, %xmm1 + fnmsubpd %xmm1, %xmm2, 0x4(%rdx), %xmm1 + + fmaddss %xmm3, %xmm2, %xmm1, %xmm1 + fmaddss 0x100000(%r15), %xmm2, %xmm1, %xmm1 + fmaddss %xmm2, 0x100000(%r15), %xmm1, %xmm1 + fmaddss %xmm1, %xmm3, %xmm2, %xmm1 + fmaddss %xmm1, 0x100000(%r15), %xmm2, %xmm1 + fmaddss %xmm1, %xmm2, 0x100000(%r15), %xmm1 + fmaddsd %xmm3, %xmm2, %xmm1, %xmm1 + fmaddsd 0x100000(%r15), %xmm2, %xmm1, %xmm1 + fmaddsd %xmm2, 0x100000(%r15), %xmm1, %xmm1 + fmaddsd %xmm1, %xmm3, %xmm2, %xmm1 + fmaddsd %xmm1, 0x100000(%r15), %xmm2, %xmm1 + fmaddsd %xmm1, %xmm2, 0x100000(%r15), %xmm1 + fmaddps %xmm3, %xmm2, %xmm1, %xmm1 + fmaddps 0x100000(%r15), %xmm2, %xmm1, %xmm1 + fmaddps %xmm2, 0x100000(%r15), %xmm1, %xmm1 + fmaddps %xmm1, %xmm3, %xmm2, %xmm1 + fmaddps %xmm1, 0x100000(%r15), %xmm2, %xmm1 + fmaddps %xmm1, %xmm2, 0x100000(%r15), %xmm1 + fmaddpd %xmm3, %xmm2, %xmm1, %xmm1 + fmaddpd 0x100000(%r15), %xmm2, %xmm1, %xmm1 + fmaddpd %xmm2, 0x100000(%r15), %xmm1, %xmm1 + fmaddpd %xmm1, %xmm3, %xmm2, %xmm1 + fmaddpd %xmm1, 0x100000(%r15), %xmm2, %xmm1 + fmaddpd %xmm1, %xmm2, 0x100000(%r15), %xmm1 + + fmsubss %xmm3, %xmm2, %xmm1, %xmm1 + fmsubss 0x100000(%r15), %xmm2, %xmm1, %xmm1 + fmsubss %xmm2, 0x100000(%r15), %xmm1, %xmm1 + fmsubss %xmm1, %xmm3, %xmm2, %xmm1 + fmsubss %xmm1, 0x100000(%r15), %xmm2, %xmm1 + fmsubss %xmm1, %xmm2, 0x100000(%r15), %xmm1 + fmsubsd %xmm3, %xmm2, %xmm1, %xmm1 + fmsubsd 0x100000(%r15), %xmm2, %xmm1, %xmm1 + fmsubsd %xmm2, 0x100000(%r15), %xmm1, %xmm1 + fmsubsd %xmm1, %xmm3, %xmm2, %xmm1 + fmsubsd %xmm1, 0x100000(%r15), %xmm2, %xmm1 + fmsubsd %xmm1, %xmm2, 0x100000(%r15), %xmm1 + fmsubps %xmm3, %xmm2, %xmm1, %xmm1 + fmsubps 0x100000(%r15), %xmm2, %xmm1, %xmm1 + fmsubps %xmm2, 0x100000(%r15), %xmm1, %xmm1 + fmsubps %xmm1, %xmm3, %xmm2, %xmm1 + fmsubps %xmm1, 0x100000(%r15), %xmm2, %xmm1 + fmsubps %xmm1, %xmm2, 0x100000(%r15), %xmm1 + fmsubpd %xmm3, %xmm2, %xmm1, %xmm1 + fmsubpd 0x100000(%r15), %xmm2, %xmm1, %xmm1 + fmsubpd %xmm2, 0x100000(%r15), %xmm1, %xmm1 + fmsubpd %xmm1, %xmm3, %xmm2, %xmm1 + fmsubpd %xmm1, 0x100000(%r15), %xmm2, %xmm1 + fmsubpd %xmm1, %xmm2, 0x100000(%r15), %xmm1 + + fnmaddss %xmm3, %xmm2, %xmm1, %xmm1 + fnmaddss 0x100000(%r15), %xmm2, %xmm1, %xmm1 + fnmaddss %xmm2, 0x100000(%r15), %xmm1, %xmm1 + fnmaddss %xmm1, %xmm3, %xmm2, %xmm1 + fnmaddss %xmm1, 0x100000(%r15), %xmm2, %xmm1 + fnmaddss %xmm1, %xmm2, 0x100000(%r15), %xmm1 + fnmaddsd %xmm3, %xmm2, %xmm1, %xmm1 + fnmaddsd 0x100000(%r15), %xmm2, %xmm1, %xmm1 + fnmaddsd %xmm2, 0x100000(%r15), %xmm1, %xmm1 + fnmaddsd %xmm1, %xmm3, %xmm2, %xmm1 + fnmaddsd %xmm1, 0x100000(%r15), %xmm2, %xmm1 + fnmaddsd %xmm1, %xmm2, 0x100000(%r15), %xmm1 + fnmaddps %xmm3, %xmm2, %xmm1, %xmm1 + fnmaddps 0x100000(%r15), %xmm2, %xmm1, %xmm1 + fnmaddps %xmm2, 0x100000(%r15), %xmm1, %xmm1 + fnmaddps %xmm1, %xmm3, %xmm2, %xmm1 + fnmaddps %xmm1, 0x100000(%r15), %xmm2, %xmm1 + fnmaddps %xmm1, %xmm2, 0x100000(%r15), %xmm1 + fnmaddpd %xmm3, %xmm2, %xmm1, %xmm1 + fnmaddpd 0x100000(%r15), %xmm2, %xmm1, %xmm1 + fnmaddpd %xmm2, 0x100000(%r15), %xmm1, %xmm1 + fnmaddpd %xmm1, %xmm3, %xmm2, %xmm1 + fnmaddpd %xmm1, 0x100000(%r15), %xmm2, %xmm1 + fnmaddpd %xmm1, %xmm2, 0x100000(%r15), %xmm1 + + fnmsubss %xmm3, %xmm2, %xmm1, %xmm1 + fnmsubss 0x100000(%r15), %xmm2, %xmm1, %xmm1 + fnmsubss %xmm2, 0x100000(%r15), %xmm1, %xmm1 + fnmsubss %xmm1, %xmm3, %xmm2, %xmm1 + fnmsubss %xmm1, 0x100000(%r15), %xmm2, %xmm1 + fnmsubss %xmm1, %xmm2, 0x100000(%r15), %xmm1 + fnmsubsd %xmm3, %xmm2, %xmm1, %xmm1 + fnmsubsd 0x100000(%r15), %xmm2, %xmm1, %xmm1 + fnmsubsd %xmm2, 0x100000(%r15), %xmm1, %xmm1 + fnmsubsd %xmm1, %xmm3, %xmm2, %xmm1 + fnmsubsd %xmm1, 0x100000(%r15), %xmm2, %xmm1 + fnmsubsd %xmm1, %xmm2, 0x100000(%r15), %xmm1 + fnmsubps %xmm3, %xmm2, %xmm1, %xmm1 + fnmsubps 0x100000(%r15), %xmm2, %xmm1, %xmm1 + fnmsubps %xmm2, 0x100000(%r15), %xmm1, %xmm1 + fnmsubps %xmm1, %xmm3, %xmm2, %xmm1 + fnmsubps %xmm1, 0x100000(%r15), %xmm2, %xmm1 + fnmsubps %xmm1, %xmm2, 0x100000(%r15), %xmm1 + fnmsubpd %xmm3, %xmm2, %xmm1, %xmm1 + fnmsubpd 0x100000(%r15), %xmm2, %xmm1, %xmm1 + fnmsubpd %xmm2, 0x100000(%r15), %xmm1, %xmm1 + fnmsubpd %xmm1, %xmm3, %xmm2, %xmm1 + fnmsubpd %xmm1, 0x100000(%r15), %xmm2, %xmm1 + fnmsubpd %xmm1, %xmm2, 0x100000(%r15), %xmm1 + + pmacssww %xmm1, %xmm3, %xmm2, %xmm1 + pmacssww %xmm1, 0x4(%rdx), %xmm2, %xmm1 + pmacsww %xmm1, %xmm3, %xmm2, %xmm1 + pmacsww %xmm1, 0x4(%rdx), %xmm2, %xmm1 + pmacswd %xmm1, %xmm3, %xmm2, %xmm1 + pmacswd %xmm1, 0x4(%rdx), %xmm2, %xmm1 + pmacssdd %xmm1, %xmm3, %xmm2, %xmm1 + pmacssdd %xmm1, 0x4(%rdx), %xmm2, %xmm1 + pmacsdd %xmm1, %xmm3, %xmm2, %xmm1 + pmacsdd %xmm1, 0x4(%rdx), %xmm2, %xmm1 + pmacssdql %xmm1, %xmm3, %xmm2, %xmm1 + pmacssdql %xmm1, 0x4(%rdx), %xmm2, %xmm1 + pmacssdqh %xmm1, %xmm3, %xmm2, %xmm1 + pmacssdqh %xmm1, 0x4(%rdx), %xmm2, %xmm1 + pmacsdql %xmm1, %xmm3, %xmm2, %xmm1 + pmacsdql %xmm1, 0x4(%rdx), %xmm2, %xmm1 + pmacsdqh %xmm1, %xmm3, %xmm2, %xmm1 + pmacsdqh %xmm1, 0x4(%rdx), %xmm2, %xmm1 + + pmadcsswd %xmm1, %xmm3, %xmm2, %xmm1 + pmadcsswd %xmm1, 0x4(%rdx), %xmm2, %xmm1 + pmadcswd %xmm1, %xmm3, %xmm2, %xmm1 + pmadcswd %xmm1, 0x4(%rdx), %xmm2, %xmm1 + + pmacssww %xmm11, %xmm13, %xmm12, %xmm11 + pmacssww %xmm11, 0x100000(%r15), %xmm12, %xmm11 + pmacsww %xmm11, %xmm13, %xmm12, %xmm11 + pmacsww %xmm11, 0x100000(%r15), %xmm12, %xmm11 + pmacswd %xmm11, %xmm13, %xmm12, %xmm11 + pmacswd %xmm11, 0x100000(%r15), %xmm12, %xmm11 + pmacssdd %xmm11, %xmm13, %xmm12, %xmm11 + pmacssdd %xmm11, 0x100000(%r15), %xmm12, %xmm11 + pmacsdd %xmm11, %xmm13, %xmm12, %xmm11 + pmacsdd %xmm11, 0x100000(%r15), %xmm12, %xmm11 + pmacssdql %xmm11, %xmm13, %xmm12, %xmm11 + pmacssdql %xmm11, 0x100000(%r15), %xmm12, %xmm11 + pmacssdqh %xmm11, %xmm13, %xmm12, %xmm11 + pmacssdqh %xmm11, 0x100000(%r15), %xmm12, %xmm11 + pmacsdql %xmm11, %xmm13, %xmm12, %xmm11 + pmacsdql %xmm11, 0x100000(%r15), %xmm12, %xmm11 + pmacsdqh %xmm11, %xmm13, %xmm12, %xmm11 + pmacsdqh %xmm11, 0x100000(%r15), %xmm12, %xmm11 + + pmadcsswd %xmm11, %xmm13, %xmm12, %xmm11 + pmadcsswd %xmm11, 0x100000(%r15), %xmm12, %xmm11 + pmadcswd %xmm11, %xmm13, %xmm12, %xmm11 + pmadcswd %xmm11, 0x100000(%r15), %xmm12, %xmm11 + + pmacssww %xmm1, %xmm3, %xmm12, %xmm1 + pmacssww %xmm1, 0x4(%rdx), %xmm12, %xmm1 + pmacsww %xmm1, %xmm3, %xmm12, %xmm1 + pmacsww %xmm1, 0x4(%rdx), %xmm12, %xmm1 + pmacswd %xmm1, %xmm3, %xmm12, %xmm1 + pmacswd %xmm1, 0x4(%rdx), %xmm12, %xmm1 + pmacssdd %xmm1, %xmm3, %xmm12, %xmm1 + pmacssdd %xmm1, 0x4(%rdx), %xmm12, %xmm1 + pmacsdd %xmm1, %xmm3, %xmm12, %xmm1 + pmacsdd %xmm1, 0x4(%rdx), %xmm12, %xmm1 + pmacssdql %xmm1, %xmm3, %xmm12, %xmm1 + pmacssdql %xmm1, 0x4(%rdx), %xmm12, %xmm1 + pmacssdqh %xmm1, %xmm3, %xmm12, %xmm1 + pmacssdqh %xmm1, 0x4(%rdx), %xmm12, %xmm1 + pmacsdql %xmm1, %xmm3, %xmm12, %xmm1 + pmacsdql %xmm1, 0x4(%rdx), %xmm12, %xmm1 + pmacsdqh %xmm1, %xmm3, %xmm12, %xmm1 + pmacsdqh %xmm1, 0x4(%rdx), %xmm12, %xmm1 + + pmadcsswd %xmm1, %xmm3, %xmm12, %xmm1 + pmadcsswd %xmm1, 0x4(%rdx), %xmm12, %xmm1 + pmadcswd %xmm1, %xmm3, %xmm12, %xmm1 + pmadcswd %xmm1, 0x4(%rdx), %xmm12, %xmm1 + + pmacssww %xmm11, %xmm3, %xmm2, %xmm11 + pmacssww %xmm11, 0x4(%rdx), %xmm2, %xmm11 + pmacsww %xmm11, %xmm3, %xmm2, %xmm11 + pmacsww %xmm11, 0x4(%rdx), %xmm2, %xmm11 + pmacswd %xmm11, %xmm3, %xmm2, %xmm11 + pmacswd %xmm11, 0x4(%rdx), %xmm2, %xmm11 + pmacssdd %xmm11, %xmm3, %xmm2, %xmm11 + pmacssdd %xmm11, 0x4(%rdx), %xmm2, %xmm11 + pmacsdd %xmm11, %xmm3, %xmm2, %xmm11 + pmacsdd %xmm11, 0x4(%rdx), %xmm2, %xmm11 + pmacssdql %xmm11, %xmm3, %xmm2, %xmm11 + pmacssdql %xmm11, 0x4(%rdx), %xmm2, %xmm11 + pmacssdqh %xmm11, %xmm3, %xmm2, %xmm11 + pmacssdqh %xmm11, 0x4(%rdx), %xmm2, %xmm11 + pmacsdql %xmm11, %xmm3, %xmm2, %xmm11 + pmacsdql %xmm11, 0x4(%rdx), %xmm2, %xmm11 + pmacsdqh %xmm11, %xmm3, %xmm2, %xmm11 + pmacsdqh %xmm11, 0x4(%rdx), %xmm2, %xmm11 + + pmadcsswd %xmm11, %xmm3, %xmm2, %xmm11 + pmadcsswd %xmm11, 0x4(%rdx), %xmm2, %xmm11 + pmadcswd %xmm11, %xmm3, %xmm2, %xmm11 + pmadcswd %xmm11, 0x4(%rdx), %xmm2, %xmm11 + + pmacssww %xmm1, %xmm13, %xmm2, %xmm1 + pmacssww %xmm1, 0x4(%rdx), %xmm2, %xmm1 + pmacsww %xmm1, %xmm13, %xmm2, %xmm1 + pmacsww %xmm1, 0x4(%rdx), %xmm2, %xmm1 + pmacswd %xmm1, %xmm13, %xmm2, %xmm1 + pmacswd %xmm1, 0x4(%rdx), %xmm2, %xmm1 + pmacssdd %xmm1, %xmm13, %xmm2, %xmm1 + pmacssdd %xmm1, 0x4(%rdx), %xmm2, %xmm1 + pmacsdd %xmm1, %xmm13, %xmm2, %xmm1 + pmacsdd %xmm1, 0x4(%rdx), %xmm2, %xmm1 + pmacssdql %xmm1, %xmm13, %xmm2, %xmm1 + pmacssdql %xmm1, 0x4(%rdx), %xmm2, %xmm1 + pmacssdqh %xmm1, %xmm13, %xmm2, %xmm1 + pmacssdqh %xmm1, 0x4(%rdx), %xmm2, %xmm1 + pmacsdql %xmm1, %xmm13, %xmm2, %xmm1 + pmacsdql %xmm1, 0x4(%rdx), %xmm2, %xmm1 + pmacsdqh %xmm1, %xmm13, %xmm2, %xmm1 + pmacsdqh %xmm1, 0x4(%rdx), %xmm2, %xmm1 + + pmadcsswd %xmm1, %xmm13, %xmm2, %xmm1 + pmadcsswd %xmm1, 0x4(%rdx), %xmm2, %xmm1 + pmadcswd %xmm1, %xmm13, %xmm2, %xmm1 + pmadcswd %xmm1, 0x4(%rdx), %xmm2, %xmm1 + + pmacssww %xmm1, %xmm3, %xmm2, %xmm1 + pmacssww %xmm1, 0x100000(%r15), %xmm2, %xmm1 + pmacsww %xmm1, %xmm3, %xmm2, %xmm1 + pmacsww %xmm1, 0x100000(%r15), %xmm2, %xmm1 + pmacswd %xmm1, %xmm3, %xmm2, %xmm1 + pmacswd %xmm1, 0x100000(%r15), %xmm2, %xmm1 + pmacssdd %xmm1, %xmm3, %xmm2, %xmm1 + pmacssdd %xmm1, 0x100000(%r15), %xmm2, %xmm1 + pmacsdd %xmm1, %xmm3, %xmm2, %xmm1 + pmacsdd %xmm1, 0x100000(%r15), %xmm2, %xmm1 + pmacssdql %xmm1, %xmm3, %xmm2, %xmm1 + pmacssdql %xmm1, 0x100000(%r15), %xmm2, %xmm1 + pmacssdqh %xmm1, %xmm3, %xmm2, %xmm1 + pmacssdqh %xmm1, 0x100000(%r15), %xmm2, %xmm1 + pmacsdql %xmm1, %xmm3, %xmm2, %xmm1 + pmacsdql %xmm1, 0x100000(%r15), %xmm2, %xmm1 + pmacsdqh %xmm1, %xmm3, %xmm2, %xmm1 + pmacsdqh %xmm1, 0x100000(%r15), %xmm2, %xmm1 + + pmadcsswd %xmm1, %xmm3, %xmm2, %xmm1 + pmadcsswd %xmm1, 0x100000(%r15), %xmm2, %xmm1 + pmadcswd %xmm1, %xmm3, %xmm2, %xmm1 + pmadcswd %xmm1, 0x100000(%r15), %xmm2, %xmm1 + + phaddbw %xmm2, %xmm1 + phaddbw 0x4(%rdx), %xmm1 + phaddbd %xmm2, %xmm1 + phaddbd 0x4(%rdx), %xmm1 + phaddbq %xmm2, %xmm1 + phaddbq 0x4(%rdx), %xmm1 + phaddwd %xmm2, %xmm1 + phaddwd 0x4(%rdx), %xmm1 + phaddwq %xmm2, %xmm1 + phaddwq 0x4(%rdx), %xmm1 + phadddq %xmm2, %xmm1 + phadddq 0x4(%rdx), %xmm1 + + phaddubw %xmm2, %xmm1 + phaddubw 0x4(%rdx), %xmm1 + phaddubd %xmm2, %xmm1 + phaddubd 0x4(%rdx), %xmm1 + phaddubq %xmm2, %xmm1 + phaddubq 0x4(%rdx), %xmm1 + phadduwd %xmm2, %xmm1 + phadduwd 0x4(%rdx), %xmm1 + phadduwq %xmm2, %xmm1 + phadduwq 0x4(%rdx), %xmm1 + phaddudq %xmm2, %xmm1 + phaddudq 0x4(%rdx), %xmm1 + + phsubbw %xmm2, %xmm1 + phsubbw 0x4(%rdx), %xmm1 + phsubwd %xmm2, %xmm1 + phsubwd 0x4(%rdx), %xmm1 + phsubdq %xmm2, %xmm1 + phsubdq 0x4(%rdx), %xmm1 + + phaddbw %xmm12, %xmm11 + phaddbw 0x100000(%r15), %xmm11 + phaddbd %xmm12, %xmm11 + phaddbd 0x100000(%r15), %xmm11 + phaddbq %xmm12, %xmm11 + phaddbq 0x100000(%r15), %xmm11 + phaddwd %xmm12, %xmm11 + phaddwd 0x100000(%r15), %xmm11 + phaddwq %xmm12, %xmm11 + phaddwq 0x100000(%r15), %xmm11 + phadddq %xmm12, %xmm11 + phadddq 0x100000(%r15), %xmm11 + + phaddubw %xmm12, %xmm11 + phaddubw 0x100000(%r15), %xmm11 + phaddubd %xmm12, %xmm11 + phaddubd 0x100000(%r15), %xmm11 + phaddubq %xmm12, %xmm11 + phaddubq 0x100000(%r15), %xmm11 + phadduwd %xmm12, %xmm11 + phadduwd 0x100000(%r15), %xmm11 + phadduwq %xmm12, %xmm11 + phadduwq 0x100000(%r15), %xmm11 + phaddudq %xmm12, %xmm11 + phaddudq 0x100000(%r15), %xmm11 + + phsubbw %xmm12, %xmm11 + phsubbw 0x100000(%r15), %xmm11 + phsubwd %xmm12, %xmm11 + phsubwd 0x100000(%r15), %xmm11 + phsubdq %xmm12, %xmm11 + phsubdq 0x100000(%r15), %xmm11 + + phaddbw %xmm12, %xmm1 + phaddbw 0x4(%rdx), %xmm1 + phaddbd %xmm12, %xmm1 + phaddbd 0x4(%rdx), %xmm1 + phaddbq %xmm12, %xmm1 + phaddbq 0x4(%rdx), %xmm1 + phaddwd %xmm12, %xmm1 + phaddwd 0x4(%rdx), %xmm1 + phaddwq %xmm12, %xmm1 + phaddwq 0x4(%rdx), %xmm1 + phadddq %xmm12, %xmm1 + phadddq 0x4(%rdx), %xmm1 + + phaddubw %xmm12, %xmm1 + phaddubw 0x4(%rdx), %xmm1 + phaddubd %xmm12, %xmm1 + phaddubd 0x4(%rdx), %xmm1 + phaddubq %xmm12, %xmm1 + phaddubq 0x4(%rdx), %xmm1 + phadduwd %xmm12, %xmm1 + phadduwd 0x4(%rdx), %xmm1 + phadduwq %xmm12, %xmm1 + phadduwq 0x4(%rdx), %xmm1 + phaddudq %xmm12, %xmm1 + phaddudq 0x4(%rdx), %xmm1 + + phsubbw %xmm12, %xmm1 + phsubbw 0x4(%rdx), %xmm1 + phsubwd %xmm12, %xmm1 + phsubwd 0x4(%rdx), %xmm1 + phsubdq %xmm12, %xmm1 + phsubdq 0x4(%rdx), %xmm1 + + phaddbw %xmm2, %xmm11 + phaddbw 0x4(%rdx), %xmm11 + phaddbd %xmm2, %xmm11 + phaddbd 0x4(%rdx), %xmm11 + phaddbq %xmm2, %xmm11 + phaddbq 0x4(%rdx), %xmm11 + phaddwd %xmm2, %xmm11 + phaddwd 0x4(%rdx), %xmm11 + phaddwq %xmm2, %xmm11 + phaddwq 0x4(%rdx), %xmm11 + phadddq %xmm2, %xmm11 + phadddq 0x4(%rdx), %xmm11 + + phaddubw %xmm2, %xmm11 + phaddubw 0x4(%rdx), %xmm11 + phaddubd %xmm2, %xmm11 + phaddubd 0x4(%rdx), %xmm11 + phaddubq %xmm2, %xmm11 + phaddubq 0x4(%rdx), %xmm11 + phadduwd %xmm2, %xmm11 + phadduwd 0x4(%rdx), %xmm11 + phadduwq %xmm2, %xmm11 + phadduwq 0x4(%rdx), %xmm11 + phaddudq %xmm2, %xmm11 + phaddudq 0x4(%rdx), %xmm11 + + phsubbw %xmm2, %xmm11 + phsubbw 0x4(%rdx), %xmm11 + phsubwd %xmm2, %xmm11 + phsubwd 0x4(%rdx), %xmm11 + phsubdq %xmm2, %xmm11 + phsubdq 0x4(%rdx), %xmm11 + + phaddbw %xmm2, %xmm1 + phaddbw 0x4(%rdx), %xmm1 + phaddbd %xmm2, %xmm1 + phaddbd 0x4(%rdx), %xmm1 + phaddbq %xmm2, %xmm1 + phaddbq 0x4(%rdx), %xmm1 + phaddwd %xmm2, %xmm1 + phaddwd 0x4(%rdx), %xmm1 + phaddwq %xmm2, %xmm1 + phaddwq 0x4(%rdx), %xmm1 + phadddq %xmm2, %xmm1 + phadddq 0x4(%rdx), %xmm1 + + phaddubw %xmm2, %xmm1 + phaddubw 0x4(%rdx), %xmm1 + phaddubd %xmm2, %xmm1 + phaddubd 0x4(%rdx), %xmm1 + phaddubq %xmm2, %xmm1 + phaddubq 0x4(%rdx), %xmm1 + phadduwd %xmm2, %xmm1 + phadduwd 0x4(%rdx), %xmm1 + phadduwq %xmm2, %xmm1 + phadduwq 0x4(%rdx), %xmm1 + phaddudq %xmm2, %xmm1 + phaddudq 0x4(%rdx), %xmm1 + + phsubbw %xmm2, %xmm1 + phsubbw 0x4(%rdx), %xmm1 + phsubwd %xmm2, %xmm1 + phsubwd 0x4(%rdx), %xmm1 + phsubdq %xmm2, %xmm1 + phsubdq 0x4(%rdx), %xmm1 + + phaddbw %xmm2, %xmm1 + phaddbw 0x100000(%r15), %xmm1 + phaddbd %xmm2, %xmm1 + phaddbd 0x100000(%r15), %xmm1 + phaddbq %xmm2, %xmm1 + phaddbq 0x100000(%r15), %xmm1 + phaddwd %xmm2, %xmm1 + phaddwd 0x100000(%r15), %xmm1 + phaddwq %xmm2, %xmm1 + phaddwq 0x100000(%r15), %xmm1 + phadddq %xmm2, %xmm1 + phadddq 0x100000(%r15), %xmm1 + + phaddubw %xmm2, %xmm1 + phaddubw 0x100000(%r15), %xmm1 + phaddubd %xmm2, %xmm1 + phaddubd 0x100000(%r15), %xmm1 + phaddubq %xmm2, %xmm1 + phaddubq 0x100000(%r15), %xmm1 + phadduwd %xmm2, %xmm1 + phadduwd 0x100000(%r15), %xmm1 + phadduwq %xmm2, %xmm1 + phadduwq 0x100000(%r15), %xmm1 + phaddudq %xmm2, %xmm1 + phaddudq 0x100000(%r15), %xmm1 + + phsubbw %xmm2, %xmm1 + phsubbw 0x100000(%r15), %xmm1 + phsubwd %xmm2, %xmm1 + phsubwd 0x100000(%r15), %xmm1 + phsubdq %xmm2, %xmm1 + phsubdq 0x100000(%r15), %xmm1 + + pcmov %xmm3, %xmm2, %xmm1, %xmm1 + pcmov 0x4(%rdx), %xmm2, %xmm1, %xmm1 + pcmov %xmm2, 0x4(%rdx), %xmm1, %xmm1 + pcmov %xmm1, %xmm3, %xmm2, %xmm1 + pcmov %xmm1, 0x4(%rdx), %xmm2, %xmm1 + pcmov %xmm1, %xmm2, 0x4(%rdx), %xmm1 + + pperm %xmm3, %xmm2, %xmm1, %xmm1 + pperm 0x4(%rdx), %xmm2, %xmm1, %xmm1 + pperm %xmm2, 0x4(%rdx), %xmm1, %xmm1 + pperm %xmm1, %xmm3, %xmm2, %xmm1 + pperm %xmm1, 0x4(%rdx), %xmm2, %xmm1 + pperm %xmm1, %xmm2, 0x4(%rdx), %xmm1 + + permps %xmm3, %xmm2, %xmm1, %xmm1 + permps 0x4(%rdx), %xmm2, %xmm1, %xmm1 + permps %xmm2, 0x4(%rdx), %xmm1, %xmm1 + permps %xmm1, %xmm3, %xmm2, %xmm1 + permps %xmm1, 0x4(%rdx), %xmm2, %xmm1 + permps %xmm1, %xmm2, 0x4(%rdx), %xmm1 + + permpd %xmm3, %xmm2, %xmm1, %xmm1 + permpd 0x4(%rdx), %xmm2, %xmm1, %xmm1 + permpd %xmm2, 0x4(%rdx), %xmm1, %xmm1 + permpd %xmm1, %xmm3, %xmm2, %xmm1 + permpd %xmm1, 0x4(%rdx), %xmm2, %xmm1 + permpd %xmm1, %xmm2, 0x4(%rdx), %xmm1 + + pcmov %xmm13, %xmm12, %xmm11, %xmm11 + pcmov 0x100000(%r15), %xmm12, %xmm11, %xmm11 + pcmov %xmm12, 0x100000(%r15), %xmm11, %xmm11 + pcmov %xmm11, %xmm13, %xmm12, %xmm11 + pcmov %xmm11, 0x100000(%r15), %xmm12, %xmm11 + pcmov %xmm11, %xmm12, 0x100000(%r15), %xmm11 + + pperm %xmm13, %xmm12, %xmm11, %xmm11 + pperm 0x100000(%r15), %xmm12, %xmm11, %xmm11 + pperm %xmm12, 0x100000(%r15), %xmm11, %xmm11 + pperm %xmm11, %xmm13, %xmm12, %xmm11 + pperm %xmm11, 0x100000(%r15), %xmm12, %xmm11 + pperm %xmm11, %xmm12, 0x100000(%r15), %xmm11 + + permps %xmm13, %xmm12, %xmm11, %xmm11 + permps 0x100000(%r15), %xmm12, %xmm11, %xmm11 + permps %xmm12, 0x100000(%r15), %xmm11, %xmm11 + permps %xmm11, %xmm13, %xmm12, %xmm11 + permps %xmm11, 0x100000(%r15), %xmm12, %xmm11 + permps %xmm11, %xmm12, 0x100000(%r15), %xmm11 + + permpd %xmm13, %xmm12, %xmm11, %xmm11 + permpd 0x100000(%r15), %xmm12, %xmm11, %xmm11 + permpd %xmm12, 0x100000(%r15), %xmm11, %xmm11 + permpd %xmm11, %xmm13, %xmm12, %xmm11 + permpd %xmm11, 0x100000(%r15), %xmm12, %xmm11 + permpd %xmm11, %xmm12, 0x100000(%r15), %xmm11 + + pcmov %xmm3, %xmm12, %xmm1, %xmm1 + pcmov 0x4(%rdx), %xmm12, %xmm1, %xmm1 + pcmov %xmm12, 0x4(%rdx), %xmm1, %xmm1 + pcmov %xmm1, %xmm3, %xmm12, %xmm1 + pcmov %xmm1, 0x4(%rdx), %xmm12, %xmm1 + pcmov %xmm1, %xmm12, 0x4(%rdx), %xmm1 + + pperm %xmm3, %xmm12, %xmm1, %xmm1 + pperm 0x4(%rdx), %xmm12, %xmm1, %xmm1 + pperm %xmm12, 0x4(%rdx), %xmm1, %xmm1 + pperm %xmm1, %xmm3, %xmm12, %xmm1 + pperm %xmm1, 0x4(%rdx), %xmm12, %xmm1 + pperm %xmm1, %xmm12, 0x4(%rdx), %xmm1 + + permps %xmm3, %xmm12, %xmm1, %xmm1 + permps 0x4(%rdx), %xmm12, %xmm1, %xmm1 + permps %xmm12, 0x4(%rdx), %xmm1, %xmm1 + permps %xmm1, %xmm3, %xmm12, %xmm1 + permps %xmm1, 0x4(%rdx), %xmm12, %xmm1 + permps %xmm1, %xmm12, 0x4(%rdx), %xmm1 + + permpd %xmm3, %xmm12, %xmm1, %xmm1 + permpd 0x4(%rdx), %xmm12, %xmm1, %xmm1 + permpd %xmm12, 0x4(%rdx), %xmm1, %xmm1 + permpd %xmm1, %xmm3, %xmm12, %xmm1 + permpd %xmm1, 0x4(%rdx), %xmm12, %xmm1 + permpd %xmm1, %xmm12, 0x4(%rdx), %xmm1 + + pcmov %xmm3, %xmm2, %xmm11, %xmm11 + pcmov 0x4(%rdx), %xmm2, %xmm11, %xmm11 + pcmov %xmm2, 0x4(%rdx), %xmm11, %xmm11 + pcmov %xmm11, %xmm3, %xmm2, %xmm11 + pcmov %xmm11, 0x4(%rdx), %xmm2, %xmm11 + pcmov %xmm11, %xmm2, 0x4(%rdx), %xmm11 + + pperm %xmm3, %xmm2, %xmm11, %xmm11 + pperm 0x4(%rdx), %xmm2, %xmm11, %xmm11 + pperm %xmm2, 0x4(%rdx), %xmm11, %xmm11 + pperm %xmm11, %xmm3, %xmm2, %xmm11 + pperm %xmm11, 0x4(%rdx), %xmm2, %xmm11 + pperm %xmm11, %xmm2, 0x4(%rdx), %xmm11 + + permps %xmm3, %xmm2, %xmm11, %xmm11 + permps 0x4(%rdx), %xmm2, %xmm11, %xmm11 + permps %xmm2, 0x4(%rdx), %xmm11, %xmm11 + permps %xmm11, %xmm3, %xmm2, %xmm11 + permps %xmm11, 0x4(%rdx), %xmm2, %xmm11 + permps %xmm11, %xmm2, 0x4(%rdx), %xmm11 + + permpd %xmm3, %xmm2, %xmm11, %xmm11 + permpd 0x4(%rdx), %xmm2, %xmm11, %xmm11 + permpd %xmm2, 0x4(%rdx), %xmm11, %xmm11 + permpd %xmm11, %xmm3, %xmm2, %xmm11 + permpd %xmm11, 0x4(%rdx), %xmm2, %xmm11 + permpd %xmm11, %xmm2, 0x4(%rdx), %xmm11 + + pcmov %xmm13, %xmm2, %xmm1, %xmm1 + pcmov 0x4(%rdx), %xmm2, %xmm1, %xmm1 + pcmov %xmm2, 0x4(%rdx), %xmm1, %xmm1 + pcmov %xmm1, %xmm13, %xmm2, %xmm1 + pcmov %xmm1, 0x4(%rdx), %xmm2, %xmm1 + pcmov %xmm1, %xmm2, 0x4(%rdx), %xmm1 + + pperm %xmm13, %xmm2, %xmm1, %xmm1 + pperm 0x4(%rdx), %xmm2, %xmm1, %xmm1 + pperm %xmm2, 0x4(%rdx), %xmm1, %xmm1 + pperm %xmm1, %xmm13, %xmm2, %xmm1 + pperm %xmm1, 0x4(%rdx), %xmm2, %xmm1 + pperm %xmm1, %xmm2, 0x4(%rdx), %xmm1 + + permps %xmm13, %xmm2, %xmm1, %xmm1 + permps 0x4(%rdx), %xmm2, %xmm1, %xmm1 + permps %xmm2, 0x4(%rdx), %xmm1, %xmm1 + permps %xmm1, %xmm13, %xmm2, %xmm1 + permps %xmm1, 0x4(%rdx), %xmm2, %xmm1 + permps %xmm1, %xmm2, 0x4(%rdx), %xmm1 + + permpd %xmm13, %xmm2, %xmm1, %xmm1 + permpd 0x4(%rdx), %xmm2, %xmm1, %xmm1 + permpd %xmm2, 0x4(%rdx), %xmm1, %xmm1 + permpd %xmm1, %xmm13, %xmm2, %xmm1 + permpd %xmm1, 0x4(%rdx), %xmm2, %xmm1 + permpd %xmm1, %xmm2, 0x4(%rdx), %xmm1 + + pcmov %xmm3, %xmm2, %xmm1, %xmm1 + pcmov 0x100000(%r15), %xmm2, %xmm1, %xmm1 + pcmov %xmm2, 0x100000(%r15), %xmm1, %xmm1 + pcmov %xmm1, %xmm3, %xmm2, %xmm1 + pcmov %xmm1, 0x100000(%r15), %xmm2, %xmm1 + pcmov %xmm1, %xmm2, 0x100000(%r15), %xmm1 + + pperm %xmm3, %xmm2, %xmm1, %xmm1 + pperm 0x100000(%r15), %xmm2, %xmm1, %xmm1 + pperm %xmm2, 0x100000(%r15), %xmm1, %xmm1 + pperm %xmm1, %xmm3, %xmm2, %xmm1 + pperm %xmm1, 0x100000(%r15), %xmm2, %xmm1 + pperm %xmm1, %xmm2, 0x100000(%r15), %xmm1 + + permps %xmm3, %xmm2, %xmm1, %xmm1 + permps 0x100000(%r15), %xmm2, %xmm1, %xmm1 + permps %xmm2, 0x100000(%r15), %xmm1, %xmm1 + permps %xmm1, %xmm3, %xmm2, %xmm1 + permps %xmm1, 0x100000(%r15), %xmm2, %xmm1 + permps %xmm1, %xmm2, 0x100000(%r15), %xmm1 + + permpd %xmm3, %xmm2, %xmm1, %xmm1 + permpd 0x100000(%r15), %xmm2, %xmm1, %xmm1 + permpd %xmm2, 0x100000(%r15), %xmm1, %xmm1 + permpd %xmm1, %xmm3, %xmm2, %xmm1 + permpd %xmm1, 0x100000(%r15), %xmm2, %xmm1 + permpd %xmm1, %xmm2, 0x100000(%r15), %xmm1 + + protb %xmm3, %xmm2, %xmm1 + protb 0x4(%rdx), %xmm2, %xmm1 + protb %xmm2, 0x4(%rdx), %xmm1 + protb $0x4, %xmm2, %xmm1 + protw %xmm3, %xmm2, %xmm1 + protw 0x4(%rdx), %xmm2, %xmm1 + protw %xmm2, 0x4(%rdx), %xmm1 + protw $0x4, %xmm2, %xmm1 + protd %xmm3, %xmm2, %xmm1 + protd 0x4(%rdx), %xmm2, %xmm1 + protd %xmm2, 0x4(%rdx), %xmm1 + protd $0x4, %xmm2, %xmm1 + protq %xmm3, %xmm2, %xmm1 + protq 0x4(%rdx), %xmm2, %xmm1 + protq %xmm2, 0x4(%rdx), %xmm1 + protq $0x4, %xmm2, %xmm1 + + protb %xmm13, %xmm12, %xmm11 + protb 0x100000(%r15), %xmm12, %xmm11 + protb %xmm12, 0x100000(%r15), %xmm11 + protb $0x4, %xmm12, %xmm11 + protw %xmm13, %xmm12, %xmm11 + protw 0x100000(%r15), %xmm12, %xmm11 + protw %xmm12, 0x100000(%r15), %xmm11 + protw $0x4, %xmm12, %xmm11 + protd %xmm13, %xmm12, %xmm11 + protd 0x100000(%r15), %xmm12, %xmm11 + protd %xmm12, 0x100000(%r15), %xmm11 + protd $0x4, %xmm12, %xmm11 + protq %xmm13, %xmm12, %xmm11 + protq 0x100000(%r15), %xmm12, %xmm11 + protq %xmm12, 0x100000(%r15), %xmm11 + protq $0x4, %xmm12, %xmm11 + + protb %xmm3, %xmm12, %xmm1 + protb 0x4(%rdx), %xmm12, %xmm1 + protb %xmm12, 0x4(%rdx), %xmm1 + protb $0x4, %xmm12, %xmm1 + protw %xmm3, %xmm12, %xmm1 + protw 0x4(%rdx), %xmm12, %xmm1 + protw %xmm12, 0x4(%rdx), %xmm1 + protw $0x4, %xmm12, %xmm1 + protd %xmm3, %xmm12, %xmm1 + protd 0x4(%rdx), %xmm12, %xmm1 + protd %xmm12, 0x4(%rdx), %xmm1 + protd $0x4, %xmm12, %xmm1 + protq %xmm3, %xmm12, %xmm1 + protq 0x4(%rdx), %xmm12, %xmm1 + protq %xmm12, 0x4(%rdx), %xmm1 + protq $0x4, %xmm12, %xmm1 + + protb %xmm3, %xmm2, %xmm11 + protb 0x4(%rdx), %xmm2, %xmm11 + protb %xmm2, 0x4(%rdx), %xmm11 + protb $0x4, %xmm2, %xmm11 + protw %xmm3, %xmm2, %xmm11 + protw 0x4(%rdx), %xmm2, %xmm11 + protw %xmm2, 0x4(%rdx), %xmm11 + protw $0x4, %xmm2, %xmm11 + protd %xmm3, %xmm2, %xmm11 + protd 0x4(%rdx), %xmm2, %xmm11 + protd %xmm2, 0x4(%rdx), %xmm11 + protd $0x4, %xmm2, %xmm11 + protq %xmm3, %xmm2, %xmm11 + protq 0x4(%rdx), %xmm2, %xmm11 + protq %xmm2, 0x4(%rdx), %xmm11 + protq $0x4, %xmm2, %xmm11 + + protb %xmm13, %xmm2, %xmm1 + protb 0x4(%rdx), %xmm2, %xmm1 + protb %xmm2, 0x4(%rdx), %xmm1 + protb $0x4, %xmm2, %xmm1 + protw %xmm13, %xmm2, %xmm1 + protw 0x4(%rdx), %xmm2, %xmm1 + protw %xmm2, 0x4(%rdx), %xmm1 + protw $0x4, %xmm2, %xmm1 + protd %xmm13, %xmm2, %xmm1 + protd 0x4(%rdx), %xmm2, %xmm1 + protd %xmm2, 0x4(%rdx), %xmm1 + protd $0x4, %xmm2, %xmm1 + protq %xmm13, %xmm2, %xmm1 + protq 0x4(%rdx), %xmm2, %xmm1 + protq %xmm2, 0x4(%rdx), %xmm1 + protq $0x4, %xmm2, %xmm1 + + protb %xmm3, %xmm2, %xmm1 + protb 0x100000(%r15), %xmm2, %xmm1 + protb %xmm2, 0x100000(%r15), %xmm1 + protb $0x4, %xmm2, %xmm1 + protw %xmm3, %xmm2, %xmm1 + protw 0x100000(%r15), %xmm2, %xmm1 + protw %xmm2, 0x100000(%r15), %xmm1 + protw $0x4, %xmm2, %xmm1 + protd %xmm3, %xmm2, %xmm1 + protd 0x100000(%r15), %xmm2, %xmm1 + protd %xmm2, 0x100000(%r15), %xmm1 + protd $0x4, %xmm2, %xmm1 + protq %xmm3, %xmm2, %xmm1 + protq 0x100000(%r15), %xmm2, %xmm1 + protq %xmm2, 0x100000(%r15), %xmm1 + protq $0x4, %xmm2, %xmm1 + + pshlb %xmm3, %xmm2, %xmm1 + pshlb 0x4(%rdx), %xmm2, %xmm1 + pshlb %xmm2, 0x4(%rdx), %xmm1 + pshlw %xmm3, %xmm2, %xmm1 + pshlw 0x4(%rdx), %xmm2, %xmm1 + pshlw %xmm2, 0x4(%rdx), %xmm1 + pshld %xmm3, %xmm2, %xmm1 + pshld 0x4(%rdx), %xmm2, %xmm1 + pshld %xmm2, 0x4(%rdx), %xmm1 + pshlq %xmm3, %xmm2, %xmm1 + pshlq 0x4(%rdx), %xmm2, %xmm1 + pshlq %xmm2, 0x4(%rdx), %xmm1 + + pshab %xmm3, %xmm2, %xmm1 + pshab 0x4(%rdx), %xmm2, %xmm1 + pshab %xmm2, 0x4(%rdx), %xmm1 + pshaw %xmm3, %xmm2, %xmm1 + pshaw 0x4(%rdx), %xmm2, %xmm1 + pshaw %xmm2, 0x4(%rdx), %xmm1 + pshad %xmm3, %xmm2, %xmm1 + pshad 0x4(%rdx), %xmm2, %xmm1 + pshad %xmm2, 0x4(%rdx), %xmm1 + pshaq %xmm3, %xmm2, %xmm1 + pshaq 0x4(%rdx), %xmm2, %xmm1 + pshaq %xmm2, 0x4(%rdx), %xmm1 + + pshlb %xmm13, %xmm12, %xmm11 + pshlb 0x100000(%r15), %xmm12, %xmm11 + pshlb %xmm12, 0x100000(%r15), %xmm11 + pshlw %xmm13, %xmm12, %xmm11 + pshlw 0x100000(%r15), %xmm12, %xmm11 + pshlw %xmm12, 0x100000(%r15), %xmm11 + pshld %xmm13, %xmm12, %xmm11 + pshld 0x100000(%r15), %xmm12, %xmm11 + pshld %xmm12, 0x100000(%r15), %xmm11 + pshlq %xmm13, %xmm12, %xmm11 + pshlq 0x100000(%r15), %xmm12, %xmm11 + pshlq %xmm12, 0x100000(%r15), %xmm11 + + pshab %xmm13, %xmm12, %xmm11 + pshab 0x100000(%r15), %xmm12, %xmm11 + pshab %xmm12, 0x100000(%r15), %xmm11 + pshaw %xmm13, %xmm12, %xmm11 + pshaw 0x100000(%r15), %xmm12, %xmm11 + pshaw %xmm12, 0x100000(%r15), %xmm11 + pshad %xmm13, %xmm12, %xmm11 + pshad 0x100000(%r15), %xmm12, %xmm11 + pshad %xmm12, 0x100000(%r15), %xmm11 + pshaq %xmm13, %xmm12, %xmm11 + pshaq 0x100000(%r15), %xmm12, %xmm11 + pshaq %xmm12, 0x100000(%r15), %xmm11 + + pshlb %xmm3, %xmm12, %xmm1 + pshlb 0x4(%rdx), %xmm12, %xmm1 + pshlb %xmm12, 0x4(%rdx), %xmm1 + pshlw %xmm3, %xmm12, %xmm1 + pshlw 0x4(%rdx), %xmm12, %xmm1 + pshlw %xmm12, 0x4(%rdx), %xmm1 + pshld %xmm3, %xmm12, %xmm1 + pshld 0x4(%rdx), %xmm12, %xmm1 + pshld %xmm12, 0x4(%rdx), %xmm1 + pshlq %xmm3, %xmm12, %xmm1 + pshlq 0x4(%rdx), %xmm12, %xmm1 + pshlq %xmm12, 0x4(%rdx), %xmm1 + + pshab %xmm3, %xmm12, %xmm1 + pshab 0x4(%rdx), %xmm12, %xmm1 + pshab %xmm12, 0x4(%rdx), %xmm1 + pshaw %xmm3, %xmm12, %xmm1 + pshaw 0x4(%rdx), %xmm12, %xmm1 + pshaw %xmm12, 0x4(%rdx), %xmm1 + pshad %xmm3, %xmm12, %xmm1 + pshad 0x4(%rdx), %xmm12, %xmm1 + pshad %xmm12, 0x4(%rdx), %xmm1 + pshaq %xmm3, %xmm12, %xmm1 + pshaq 0x4(%rdx), %xmm12, %xmm1 + pshaq %xmm12, 0x4(%rdx), %xmm1 + + pshlb %xmm3, %xmm2, %xmm11 + pshlb 0x4(%rdx), %xmm2, %xmm11 + pshlb %xmm2, 0x4(%rdx), %xmm11 + pshlw %xmm3, %xmm2, %xmm11 + pshlw 0x4(%rdx), %xmm2, %xmm11 + pshlw %xmm2, 0x4(%rdx), %xmm11 + pshld %xmm3, %xmm2, %xmm11 + pshld 0x4(%rdx), %xmm2, %xmm11 + pshld %xmm2, 0x4(%rdx), %xmm11 + pshlq %xmm3, %xmm2, %xmm11 + pshlq 0x4(%rdx), %xmm2, %xmm11 + pshlq %xmm2, 0x4(%rdx), %xmm11 + + pshab %xmm3, %xmm2, %xmm11 + pshab 0x4(%rdx), %xmm2, %xmm11 + pshab %xmm2, 0x4(%rdx), %xmm11 + pshaw %xmm3, %xmm2, %xmm11 + pshaw 0x4(%rdx), %xmm2, %xmm11 + pshaw %xmm2, 0x4(%rdx), %xmm11 + pshad %xmm3, %xmm2, %xmm11 + pshad 0x4(%rdx), %xmm2, %xmm11 + pshad %xmm2, 0x4(%rdx), %xmm11 + pshaq %xmm3, %xmm2, %xmm11 + pshaq 0x4(%rdx), %xmm2, %xmm11 + pshaq %xmm2, 0x4(%rdx), %xmm11 + + pshlb %xmm13, %xmm2, %xmm1 + pshlb 0x4(%rdx), %xmm2, %xmm1 + pshlb %xmm2, 0x4(%rdx), %xmm1 + pshlw %xmm13, %xmm2, %xmm1 + pshlw 0x4(%rdx), %xmm2, %xmm1 + pshlw %xmm2, 0x4(%rdx), %xmm1 + pshld %xmm13, %xmm2, %xmm1 + pshld 0x4(%rdx), %xmm2, %xmm1 + pshld %xmm2, 0x4(%rdx), %xmm1 + pshlq %xmm13, %xmm2, %xmm1 + pshlq 0x4(%rdx), %xmm2, %xmm1 + pshlq %xmm2, 0x4(%rdx), %xmm1 + + pshab %xmm13, %xmm2, %xmm1 + pshab 0x4(%rdx), %xmm2, %xmm1 + pshab %xmm2, 0x4(%rdx), %xmm1 + pshaw %xmm13, %xmm2, %xmm1 + pshaw 0x4(%rdx), %xmm2, %xmm1 + pshaw %xmm2, 0x4(%rdx), %xmm1 + pshad %xmm13, %xmm2, %xmm1 + pshad 0x4(%rdx), %xmm2, %xmm1 + pshad %xmm2, 0x4(%rdx), %xmm1 + pshaq %xmm13, %xmm2, %xmm1 + pshaq 0x4(%rdx), %xmm2, %xmm1 + pshaq %xmm2, 0x4(%rdx), %xmm1 + + pshlb %xmm3, %xmm2, %xmm1 + pshlb 0x100000(%r15), %xmm2, %xmm1 + pshlb %xmm2, 0x100000(%r15), %xmm1 + pshlw %xmm3, %xmm2, %xmm1 + pshlw 0x100000(%r15), %xmm2, %xmm1 + pshlw %xmm2, 0x100000(%r15), %xmm1 + pshld %xmm3, %xmm2, %xmm1 + pshld 0x100000(%r15), %xmm2, %xmm1 + pshld %xmm2, 0x100000(%r15), %xmm1 + pshlq %xmm3, %xmm2, %xmm1 + pshlq 0x100000(%r15), %xmm2, %xmm1 + pshlq %xmm2, 0x100000(%r15), %xmm1 + + pshab %xmm3, %xmm2, %xmm1 + pshab 0x100000(%r15), %xmm2, %xmm1 + pshab %xmm2, 0x100000(%r15), %xmm1 + pshaw %xmm3, %xmm2, %xmm1 + pshaw 0x100000(%r15), %xmm2, %xmm1 + pshaw %xmm2, 0x100000(%r15), %xmm1 + pshad %xmm3, %xmm2, %xmm1 + pshad 0x100000(%r15), %xmm2, %xmm1 + pshad %xmm2, 0x100000(%r15), %xmm1 + pshaq %xmm3, %xmm2, %xmm1 + pshaq 0x100000(%r15), %xmm2, %xmm1 + pshaq %xmm2, 0x100000(%r15), %xmm1 + + comss $0x4, %xmm3, %xmm2, %xmm1 + comss $0x4, 0x4(%rdx), %xmm2, %xmm1 + comeqss %xmm3, %xmm2, %xmm1 + comltss %xmm3, %xmm2, %xmm1 + comless %xmm3, %xmm2, %xmm1 + comunordss %xmm3, %xmm2, %xmm1 + comness %xmm3, %xmm2, %xmm1 + comnltss %xmm3, %xmm2, %xmm1 + comnless %xmm3, %xmm2, %xmm1 + comordss %xmm3, %xmm2, %xmm1 + comueqss %xmm3, %xmm2, %xmm1 + comultss %xmm3, %xmm2, %xmm1 + comuless %xmm3, %xmm2, %xmm1 + comfalsess %xmm3, %xmm2, %xmm1 + comuness %xmm3, %xmm2, %xmm1 + comunltss %xmm3, %xmm2, %xmm1 + comunless %xmm3, %xmm2, %xmm1 + comtruess %xmm3, %xmm2, %xmm1 + comeqss 0x4(%rdx), %xmm2, %xmm1 + comltss 0x4(%rdx), %xmm2, %xmm1 + comless 0x4(%rdx), %xmm2, %xmm1 + comunordss 0x4(%rdx), %xmm2, %xmm1 + comness 0x4(%rdx), %xmm2, %xmm1 + comnltss 0x4(%rdx), %xmm2, %xmm1 + comnless 0x4(%rdx), %xmm2, %xmm1 + comordss 0x4(%rdx), %xmm2, %xmm1 + comueqss 0x4(%rdx), %xmm2, %xmm1 + comultss 0x4(%rdx), %xmm2, %xmm1 + comuless 0x4(%rdx), %xmm2, %xmm1 + comfalsess 0x4(%rdx), %xmm2, %xmm1 + comuness 0x4(%rdx), %xmm2, %xmm1 + comunltss 0x4(%rdx), %xmm2, %xmm1 + comunless 0x4(%rdx), %xmm2, %xmm1 + comtruess 0x4(%rdx), %xmm2, %xmm1 + comsd $0x4, %xmm3, %xmm2, %xmm1 + comsd $0x4, 0x4(%rdx), %xmm2, %xmm1 + comeqsd %xmm3, %xmm2, %xmm1 + comltsd %xmm3, %xmm2, %xmm1 + comlesd %xmm3, %xmm2, %xmm1 + comunordsd %xmm3, %xmm2, %xmm1 + comnesd %xmm3, %xmm2, %xmm1 + comnltsd %xmm3, %xmm2, %xmm1 + comnlesd %xmm3, %xmm2, %xmm1 + comordsd %xmm3, %xmm2, %xmm1 + comueqsd %xmm3, %xmm2, %xmm1 + comultsd %xmm3, %xmm2, %xmm1 + comulesd %xmm3, %xmm2, %xmm1 + comfalsesd %xmm3, %xmm2, %xmm1 + comunesd %xmm3, %xmm2, %xmm1 + comunltsd %xmm3, %xmm2, %xmm1 + comunlesd %xmm3, %xmm2, %xmm1 + comtruesd %xmm3, %xmm2, %xmm1 + comeqsd 0x4(%rdx), %xmm2, %xmm1 + comltsd 0x4(%rdx), %xmm2, %xmm1 + comlesd 0x4(%rdx), %xmm2, %xmm1 + comunordsd 0x4(%rdx), %xmm2, %xmm1 + comnesd 0x4(%rdx), %xmm2, %xmm1 + comnltsd 0x4(%rdx), %xmm2, %xmm1 + comnlesd 0x4(%rdx), %xmm2, %xmm1 + comordsd 0x4(%rdx), %xmm2, %xmm1 + comueqsd 0x4(%rdx), %xmm2, %xmm1 + comultsd 0x4(%rdx), %xmm2, %xmm1 + comulesd 0x4(%rdx), %xmm2, %xmm1 + comfalsesd 0x4(%rdx), %xmm2, %xmm1 + comunesd 0x4(%rdx), %xmm2, %xmm1 + comunltsd 0x4(%rdx), %xmm2, %xmm1 + comunlesd 0x4(%rdx), %xmm2, %xmm1 + comtruesd 0x4(%rdx), %xmm2, %xmm1 + comps $0x4, %xmm3, %xmm2, %xmm1 + comps $0x4, 0x4(%rdx), %xmm2, %xmm1 + comeqps %xmm3, %xmm2, %xmm1 + comltps %xmm3, %xmm2, %xmm1 + comleps %xmm3, %xmm2, %xmm1 + comunordps %xmm3, %xmm2, %xmm1 + comneps %xmm3, %xmm2, %xmm1 + comnltps %xmm3, %xmm2, %xmm1 + comnleps %xmm3, %xmm2, %xmm1 + comordps %xmm3, %xmm2, %xmm1 + comueqps %xmm3, %xmm2, %xmm1 + comultps %xmm3, %xmm2, %xmm1 + comuleps %xmm3, %xmm2, %xmm1 + comfalseps %xmm3, %xmm2, %xmm1 + comuneps %xmm3, %xmm2, %xmm1 + comunltps %xmm3, %xmm2, %xmm1 + comunleps %xmm3, %xmm2, %xmm1 + comtrueps %xmm3, %xmm2, %xmm1 + comeqps 0x4(%rdx), %xmm2, %xmm1 + comltps 0x4(%rdx), %xmm2, %xmm1 + comleps 0x4(%rdx), %xmm2, %xmm1 + comunordps 0x4(%rdx), %xmm2, %xmm1 + comneps 0x4(%rdx), %xmm2, %xmm1 + comnltps 0x4(%rdx), %xmm2, %xmm1 + comnleps 0x4(%rdx), %xmm2, %xmm1 + comordps 0x4(%rdx), %xmm2, %xmm1 + comueqps 0x4(%rdx), %xmm2, %xmm1 + comultps 0x4(%rdx), %xmm2, %xmm1 + comuleps 0x4(%rdx), %xmm2, %xmm1 + comfalseps 0x4(%rdx), %xmm2, %xmm1 + comuneps 0x4(%rdx), %xmm2, %xmm1 + comunltps 0x4(%rdx), %xmm2, %xmm1 + comunleps 0x4(%rdx), %xmm2, %xmm1 + comtrueps 0x4(%rdx), %xmm2, %xmm1 + compd $0x4, %xmm3, %xmm2, %xmm1 + compd $0x4, 0x4(%rdx), %xmm2, %xmm1 + comeqpd %xmm3, %xmm2, %xmm1 + comltpd %xmm3, %xmm2, %xmm1 + comlepd %xmm3, %xmm2, %xmm1 + comunordpd %xmm3, %xmm2, %xmm1 + comnepd %xmm3, %xmm2, %xmm1 + comnltpd %xmm3, %xmm2, %xmm1 + comnlepd %xmm3, %xmm2, %xmm1 + comordpd %xmm3, %xmm2, %xmm1 + comueqpd %xmm3, %xmm2, %xmm1 + comultpd %xmm3, %xmm2, %xmm1 + comulepd %xmm3, %xmm2, %xmm1 + comfalsepd %xmm3, %xmm2, %xmm1 + comunepd %xmm3, %xmm2, %xmm1 + comunltpd %xmm3, %xmm2, %xmm1 + comunlepd %xmm3, %xmm2, %xmm1 + comtruepd %xmm3, %xmm2, %xmm1 + comeqpd 0x4(%rdx), %xmm2, %xmm1 + comltpd 0x4(%rdx), %xmm2, %xmm1 + comlepd 0x4(%rdx), %xmm2, %xmm1 + comunordpd 0x4(%rdx), %xmm2, %xmm1 + comnepd 0x4(%rdx), %xmm2, %xmm1 + comnltpd 0x4(%rdx), %xmm2, %xmm1 + comnlepd 0x4(%rdx), %xmm2, %xmm1 + comordpd 0x4(%rdx), %xmm2, %xmm1 + comueqpd 0x4(%rdx), %xmm2, %xmm1 + comultpd 0x4(%rdx), %xmm2, %xmm1 + comulepd 0x4(%rdx), %xmm2, %xmm1 + comfalsepd 0x4(%rdx), %xmm2, %xmm1 + comunepd 0x4(%rdx), %xmm2, %xmm1 + comunltpd 0x4(%rdx), %xmm2, %xmm1 + comunlepd 0x4(%rdx), %xmm2, %xmm1 + comtruepd 0x4(%rdx), %xmm2, %xmm1 + + pcomb $0x4, %xmm3, %xmm2, %xmm1 + pcomb $0x4, 0x4(%rdx), %xmm2, %xmm1 + pcomltb %xmm3, %xmm2, %xmm1 + pcomleb %xmm3, %xmm2, %xmm1 + pcomgtb %xmm3, %xmm2, %xmm1 + pcomgeb %xmm3, %xmm2, %xmm1 + pcomeqb %xmm3, %xmm2, %xmm1 + pcomneqb %xmm3, %xmm2, %xmm1 + pcomltb 0x4(%rdx), %xmm2, %xmm1 + pcomleb 0x4(%rdx), %xmm2, %xmm1 + pcomgtb 0x4(%rdx), %xmm2, %xmm1 + pcomgeb 0x4(%rdx), %xmm2, %xmm1 + pcomeqb 0x4(%rdx), %xmm2, %xmm1 + pcomneqb 0x4(%rdx), %xmm2, %xmm1 + pcomw $0x4, %xmm3, %xmm2, %xmm1 + pcomw $0x4, 0x4(%rdx), %xmm2, %xmm1 + pcomltw %xmm3, %xmm2, %xmm1 + pcomlew %xmm3, %xmm2, %xmm1 + pcomgtw %xmm3, %xmm2, %xmm1 + pcomgew %xmm3, %xmm2, %xmm1 + pcomeqw %xmm3, %xmm2, %xmm1 + pcomneqw %xmm3, %xmm2, %xmm1 + pcomltw 0x4(%rdx), %xmm2, %xmm1 + pcomlew 0x4(%rdx), %xmm2, %xmm1 + pcomgtw 0x4(%rdx), %xmm2, %xmm1 + pcomgew 0x4(%rdx), %xmm2, %xmm1 + pcomeqw 0x4(%rdx), %xmm2, %xmm1 + pcomneqw 0x4(%rdx), %xmm2, %xmm1 + pcomd $0x4, %xmm3, %xmm2, %xmm1 + pcomd $0x4, 0x4(%rdx), %xmm2, %xmm1 + pcomltd %xmm3, %xmm2, %xmm1 + pcomled %xmm3, %xmm2, %xmm1 + pcomgtd %xmm3, %xmm2, %xmm1 + pcomged %xmm3, %xmm2, %xmm1 + pcomeqd %xmm3, %xmm2, %xmm1 + pcomneqd %xmm3, %xmm2, %xmm1 + pcomltd 0x4(%rdx), %xmm2, %xmm1 + pcomled 0x4(%rdx), %xmm2, %xmm1 + pcomgtd 0x4(%rdx), %xmm2, %xmm1 + pcomged 0x4(%rdx), %xmm2, %xmm1 + pcomeqd 0x4(%rdx), %xmm2, %xmm1 + pcomneqd 0x4(%rdx), %xmm2, %xmm1 + pcomq $0x4, %xmm3, %xmm2, %xmm1 + pcomq $0x4, 0x4(%rdx), %xmm2, %xmm1 + pcomltq %xmm3, %xmm2, %xmm1 + pcomleq %xmm3, %xmm2, %xmm1 + pcomgtq %xmm3, %xmm2, %xmm1 + pcomgeq %xmm3, %xmm2, %xmm1 + pcomeqq %xmm3, %xmm2, %xmm1 + pcomneqq %xmm3, %xmm2, %xmm1 + pcomltq 0x4(%rdx), %xmm2, %xmm1 + pcomleq 0x4(%rdx), %xmm2, %xmm1 + pcomgtq 0x4(%rdx), %xmm2, %xmm1 + pcomgeq 0x4(%rdx), %xmm2, %xmm1 + pcomeqq 0x4(%rdx), %xmm2, %xmm1 + pcomneqq 0x4(%rdx), %xmm2, %xmm1 + + pcomub $0x4, %xmm3, %xmm2, %xmm1 + pcomub $0x4, 0x4(%rdx), %xmm2, %xmm1 + pcomltub %xmm3, %xmm2, %xmm1 + pcomleub %xmm3, %xmm2, %xmm1 + pcomgtub %xmm3, %xmm2, %xmm1 + pcomgeub %xmm3, %xmm2, %xmm1 + pcomequb %xmm3, %xmm2, %xmm1 + pcomnequb %xmm3, %xmm2, %xmm1 + pcomltub 0x4(%rdx), %xmm2, %xmm1 + pcomleub 0x4(%rdx), %xmm2, %xmm1 + pcomgtub 0x4(%rdx), %xmm2, %xmm1 + pcomgeub 0x4(%rdx), %xmm2, %xmm1 + pcomequb 0x4(%rdx), %xmm2, %xmm1 + pcomnequb 0x4(%rdx), %xmm2, %xmm1 + pcomuw $0x4, %xmm3, %xmm2, %xmm1 + pcomuw $0x4, 0x4(%rdx), %xmm2, %xmm1 + pcomltuw %xmm3, %xmm2, %xmm1 + pcomleuw %xmm3, %xmm2, %xmm1 + pcomgtuw %xmm3, %xmm2, %xmm1 + pcomgeuw %xmm3, %xmm2, %xmm1 + pcomequw %xmm3, %xmm2, %xmm1 + pcomnequw %xmm3, %xmm2, %xmm1 + pcomltuw 0x4(%rdx), %xmm2, %xmm1 + pcomleuw 0x4(%rdx), %xmm2, %xmm1 + pcomgtuw 0x4(%rdx), %xmm2, %xmm1 + pcomgeuw 0x4(%rdx), %xmm2, %xmm1 + pcomequw 0x4(%rdx), %xmm2, %xmm1 + pcomnequw 0x4(%rdx), %xmm2, %xmm1 + pcomud $0x4, %xmm3, %xmm2, %xmm1 + pcomud $0x4, 0x4(%rdx), %xmm2, %xmm1 + pcomltud %xmm3, %xmm2, %xmm1 + pcomleud %xmm3, %xmm2, %xmm1 + pcomgtud %xmm3, %xmm2, %xmm1 + pcomgeud %xmm3, %xmm2, %xmm1 + pcomequd %xmm3, %xmm2, %xmm1 + pcomnequd %xmm3, %xmm2, %xmm1 + pcomltud 0x4(%rdx), %xmm2, %xmm1 + pcomleud 0x4(%rdx), %xmm2, %xmm1 + pcomgtud 0x4(%rdx), %xmm2, %xmm1 + pcomgeud 0x4(%rdx), %xmm2, %xmm1 + pcomequd 0x4(%rdx), %xmm2, %xmm1 + pcomnequd 0x4(%rdx), %xmm2, %xmm1 + pcomuq $0x4, %xmm3, %xmm2, %xmm1 + pcomuq $0x4, 0x4(%rdx), %xmm2, %xmm1 + pcomltuq %xmm3, %xmm2, %xmm1 + pcomleuq %xmm3, %xmm2, %xmm1 + pcomgtuq %xmm3, %xmm2, %xmm1 + pcomgeuq %xmm3, %xmm2, %xmm1 + pcomequq %xmm3, %xmm2, %xmm1 + pcomnequq %xmm3, %xmm2, %xmm1 + pcomltuq 0x4(%rdx), %xmm2, %xmm1 + pcomleuq 0x4(%rdx), %xmm2, %xmm1 + pcomgtuq 0x4(%rdx), %xmm2, %xmm1 + pcomgeuq 0x4(%rdx), %xmm2, %xmm1 + pcomequq 0x4(%rdx), %xmm2, %xmm1 + pcomnequq 0x4(%rdx), %xmm2, %xmm1 + + comss $0x4, %xmm13, %xmm12, %xmm11 + comss $0x4, 0x100000(%r15), %xmm12, %xmm11 + comeqss %xmm13, %xmm12, %xmm11 + comltss %xmm13, %xmm12, %xmm11 + comless %xmm13, %xmm12, %xmm11 + comunordss %xmm13, %xmm12, %xmm11 + comness %xmm13, %xmm12, %xmm11 + comnltss %xmm13, %xmm12, %xmm11 + comnless %xmm13, %xmm12, %xmm11 + comordss %xmm13, %xmm12, %xmm11 + comueqss %xmm13, %xmm12, %xmm11 + comultss %xmm13, %xmm12, %xmm11 + comuless %xmm13, %xmm12, %xmm11 + comfalsess %xmm13, %xmm12, %xmm11 + comuness %xmm13, %xmm12, %xmm11 + comunltss %xmm13, %xmm12, %xmm11 + comunless %xmm13, %xmm12, %xmm11 + comtruess %xmm13, %xmm12, %xmm11 + comeqss 0x100000(%r15), %xmm12, %xmm11 + comltss 0x100000(%r15), %xmm12, %xmm11 + comless 0x100000(%r15), %xmm12, %xmm11 + comunordss 0x100000(%r15), %xmm12, %xmm11 + comness 0x100000(%r15), %xmm12, %xmm11 + comnltss 0x100000(%r15), %xmm12, %xmm11 + comnless 0x100000(%r15), %xmm12, %xmm11 + comordss 0x100000(%r15), %xmm12, %xmm11 + comueqss 0x100000(%r15), %xmm12, %xmm11 + comultss 0x100000(%r15), %xmm12, %xmm11 + comuless 0x100000(%r15), %xmm12, %xmm11 + comfalsess 0x100000(%r15), %xmm12, %xmm11 + comuness 0x100000(%r15), %xmm12, %xmm11 + comunltss 0x100000(%r15), %xmm12, %xmm11 + comunless 0x100000(%r15), %xmm12, %xmm11 + comtruess 0x100000(%r15), %xmm12, %xmm11 + comsd $0x4, %xmm13, %xmm12, %xmm11 + comsd $0x4, 0x100000(%r15), %xmm12, %xmm11 + comeqsd %xmm13, %xmm12, %xmm11 + comltsd %xmm13, %xmm12, %xmm11 + comlesd %xmm13, %xmm12, %xmm11 + comunordsd %xmm13, %xmm12, %xmm11 + comnesd %xmm13, %xmm12, %xmm11 + comnltsd %xmm13, %xmm12, %xmm11 + comnlesd %xmm13, %xmm12, %xmm11 + comordsd %xmm13, %xmm12, %xmm11 + comueqsd %xmm13, %xmm12, %xmm11 + comultsd %xmm13, %xmm12, %xmm11 + comulesd %xmm13, %xmm12, %xmm11 + comfalsesd %xmm13, %xmm12, %xmm11 + comunesd %xmm13, %xmm12, %xmm11 + comunltsd %xmm13, %xmm12, %xmm11 + comunlesd %xmm13, %xmm12, %xmm11 + comtruesd %xmm13, %xmm12, %xmm11 + comeqsd 0x100000(%r15), %xmm12, %xmm11 + comltsd 0x100000(%r15), %xmm12, %xmm11 + comlesd 0x100000(%r15), %xmm12, %xmm11 + comunordsd 0x100000(%r15), %xmm12, %xmm11 + comnesd 0x100000(%r15), %xmm12, %xmm11 + comnltsd 0x100000(%r15), %xmm12, %xmm11 + comnlesd 0x100000(%r15), %xmm12, %xmm11 + comordsd 0x100000(%r15), %xmm12, %xmm11 + comueqsd 0x100000(%r15), %xmm12, %xmm11 + comultsd 0x100000(%r15), %xmm12, %xmm11 + comulesd 0x100000(%r15), %xmm12, %xmm11 + comfalsesd 0x100000(%r15), %xmm12, %xmm11 + comunesd 0x100000(%r15), %xmm12, %xmm11 + comunltsd 0x100000(%r15), %xmm12, %xmm11 + comunlesd 0x100000(%r15), %xmm12, %xmm11 + comtruesd 0x100000(%r15), %xmm12, %xmm11 + comps $0x4, %xmm13, %xmm12, %xmm11 + comps $0x4, 0x100000(%r15), %xmm12, %xmm11 + comeqps %xmm13, %xmm12, %xmm11 + comltps %xmm13, %xmm12, %xmm11 + comleps %xmm13, %xmm12, %xmm11 + comunordps %xmm13, %xmm12, %xmm11 + comneps %xmm13, %xmm12, %xmm11 + comnltps %xmm13, %xmm12, %xmm11 + comnleps %xmm13, %xmm12, %xmm11 + comordps %xmm13, %xmm12, %xmm11 + comueqps %xmm13, %xmm12, %xmm11 + comultps %xmm13, %xmm12, %xmm11 + comuleps %xmm13, %xmm12, %xmm11 + comfalseps %xmm13, %xmm12, %xmm11 + comuneps %xmm13, %xmm12, %xmm11 + comunltps %xmm13, %xmm12, %xmm11 + comunleps %xmm13, %xmm12, %xmm11 + comtrueps %xmm13, %xmm12, %xmm11 + comeqps 0x100000(%r15), %xmm12, %xmm11 + comltps 0x100000(%r15), %xmm12, %xmm11 + comleps 0x100000(%r15), %xmm12, %xmm11 + comunordps 0x100000(%r15), %xmm12, %xmm11 + comneps 0x100000(%r15), %xmm12, %xmm11 + comnltps 0x100000(%r15), %xmm12, %xmm11 + comnleps 0x100000(%r15), %xmm12, %xmm11 + comordps 0x100000(%r15), %xmm12, %xmm11 + comueqps 0x100000(%r15), %xmm12, %xmm11 + comultps 0x100000(%r15), %xmm12, %xmm11 + comuleps 0x100000(%r15), %xmm12, %xmm11 + comfalseps 0x100000(%r15), %xmm12, %xmm11 + comuneps 0x100000(%r15), %xmm12, %xmm11 + comunltps 0x100000(%r15), %xmm12, %xmm11 + comunleps 0x100000(%r15), %xmm12, %xmm11 + comtrueps 0x100000(%r15), %xmm12, %xmm11 + compd $0x4, %xmm13, %xmm12, %xmm11 + compd $0x4, 0x100000(%r15), %xmm12, %xmm11 + comeqpd %xmm13, %xmm12, %xmm11 + comltpd %xmm13, %xmm12, %xmm11 + comlepd %xmm13, %xmm12, %xmm11 + comunordpd %xmm13, %xmm12, %xmm11 + comnepd %xmm13, %xmm12, %xmm11 + comnltpd %xmm13, %xmm12, %xmm11 + comnlepd %xmm13, %xmm12, %xmm11 + comordpd %xmm13, %xmm12, %xmm11 + comueqpd %xmm13, %xmm12, %xmm11 + comultpd %xmm13, %xmm12, %xmm11 + comulepd %xmm13, %xmm12, %xmm11 + comfalsepd %xmm13, %xmm12, %xmm11 + comunepd %xmm13, %xmm12, %xmm11 + comunltpd %xmm13, %xmm12, %xmm11 + comunlepd %xmm13, %xmm12, %xmm11 + comtruepd %xmm13, %xmm12, %xmm11 + comeqpd 0x100000(%r15), %xmm12, %xmm11 + comltpd 0x100000(%r15), %xmm12, %xmm11 + comlepd 0x100000(%r15), %xmm12, %xmm11 + comunordpd 0x100000(%r15), %xmm12, %xmm11 + comnepd 0x100000(%r15), %xmm12, %xmm11 + comnltpd 0x100000(%r15), %xmm12, %xmm11 + comnlepd 0x100000(%r15), %xmm12, %xmm11 + comordpd 0x100000(%r15), %xmm12, %xmm11 + comueqpd 0x100000(%r15), %xmm12, %xmm11 + comultpd 0x100000(%r15), %xmm12, %xmm11 + comulepd 0x100000(%r15), %xmm12, %xmm11 + comfalsepd 0x100000(%r15), %xmm12, %xmm11 + comunepd 0x100000(%r15), %xmm12, %xmm11 + comunltpd 0x100000(%r15), %xmm12, %xmm11 + comunlepd 0x100000(%r15), %xmm12, %xmm11 + comtruepd 0x100000(%r15), %xmm12, %xmm11 + + pcomb $0x4, %xmm13, %xmm12, %xmm11 + pcomb $0x4, 0x100000(%r15), %xmm12, %xmm11 + pcomltb %xmm13, %xmm12, %xmm11 + pcomleb %xmm13, %xmm12, %xmm11 + pcomgtb %xmm13, %xmm12, %xmm11 + pcomgeb %xmm13, %xmm12, %xmm11 + pcomeqb %xmm13, %xmm12, %xmm11 + pcomneqb %xmm13, %xmm12, %xmm11 + pcomltb 0x100000(%r15), %xmm12, %xmm11 + pcomleb 0x100000(%r15), %xmm12, %xmm11 + pcomgtb 0x100000(%r15), %xmm12, %xmm11 + pcomgeb 0x100000(%r15), %xmm12, %xmm11 + pcomeqb 0x100000(%r15), %xmm12, %xmm11 + pcomneqb 0x100000(%r15), %xmm12, %xmm11 + pcomw $0x4, %xmm13, %xmm12, %xmm11 + pcomw $0x4, 0x100000(%r15), %xmm12, %xmm11 + pcomltw %xmm13, %xmm12, %xmm11 + pcomlew %xmm13, %xmm12, %xmm11 + pcomgtw %xmm13, %xmm12, %xmm11 + pcomgew %xmm13, %xmm12, %xmm11 + pcomeqw %xmm13, %xmm12, %xmm11 + pcomneqw %xmm13, %xmm12, %xmm11 + pcomltw 0x100000(%r15), %xmm12, %xmm11 + pcomlew 0x100000(%r15), %xmm12, %xmm11 + pcomgtw 0x100000(%r15), %xmm12, %xmm11 + pcomgew 0x100000(%r15), %xmm12, %xmm11 + pcomeqw 0x100000(%r15), %xmm12, %xmm11 + pcomneqw 0x100000(%r15), %xmm12, %xmm11 + pcomd $0x4, %xmm13, %xmm12, %xmm11 + pcomd $0x4, 0x100000(%r15), %xmm12, %xmm11 + pcomltd %xmm13, %xmm12, %xmm11 + pcomled %xmm13, %xmm12, %xmm11 + pcomgtd %xmm13, %xmm12, %xmm11 + pcomged %xmm13, %xmm12, %xmm11 + pcomeqd %xmm13, %xmm12, %xmm11 + pcomneqd %xmm13, %xmm12, %xmm11 + pcomltd 0x100000(%r15), %xmm12, %xmm11 + pcomled 0x100000(%r15), %xmm12, %xmm11 + pcomgtd 0x100000(%r15), %xmm12, %xmm11 + pcomged 0x100000(%r15), %xmm12, %xmm11 + pcomeqd 0x100000(%r15), %xmm12, %xmm11 + pcomneqd 0x100000(%r15), %xmm12, %xmm11 + pcomq $0x4, %xmm13, %xmm12, %xmm11 + pcomq $0x4, 0x100000(%r15), %xmm12, %xmm11 + pcomltq %xmm13, %xmm12, %xmm11 + pcomleq %xmm13, %xmm12, %xmm11 + pcomgtq %xmm13, %xmm12, %xmm11 + pcomgeq %xmm13, %xmm12, %xmm11 + pcomeqq %xmm13, %xmm12, %xmm11 + pcomneqq %xmm13, %xmm12, %xmm11 + pcomltq 0x100000(%r15), %xmm12, %xmm11 + pcomleq 0x100000(%r15), %xmm12, %xmm11 + pcomgtq 0x100000(%r15), %xmm12, %xmm11 + pcomgeq 0x100000(%r15), %xmm12, %xmm11 + pcomeqq 0x100000(%r15), %xmm12, %xmm11 + pcomneqq 0x100000(%r15), %xmm12, %xmm11 + + pcomub $0x4, %xmm13, %xmm12, %xmm11 + pcomub $0x4, 0x100000(%r15), %xmm12, %xmm11 + pcomltub %xmm13, %xmm12, %xmm11 + pcomleub %xmm13, %xmm12, %xmm11 + pcomgtub %xmm13, %xmm12, %xmm11 + pcomgeub %xmm13, %xmm12, %xmm11 + pcomequb %xmm13, %xmm12, %xmm11 + pcomnequb %xmm13, %xmm12, %xmm11 + pcomltub 0x100000(%r15), %xmm12, %xmm11 + pcomleub 0x100000(%r15), %xmm12, %xmm11 + pcomgtub 0x100000(%r15), %xmm12, %xmm11 + pcomgeub 0x100000(%r15), %xmm12, %xmm11 + pcomequb 0x100000(%r15), %xmm12, %xmm11 + pcomnequb 0x100000(%r15), %xmm12, %xmm11 + pcomuw $0x4, %xmm13, %xmm12, %xmm11 + pcomuw $0x4, 0x100000(%r15), %xmm12, %xmm11 + pcomltuw %xmm13, %xmm12, %xmm11 + pcomleuw %xmm13, %xmm12, %xmm11 + pcomgtuw %xmm13, %xmm12, %xmm11 + pcomgeuw %xmm13, %xmm12, %xmm11 + pcomequw %xmm13, %xmm12, %xmm11 + pcomnequw %xmm13, %xmm12, %xmm11 + pcomltuw 0x100000(%r15), %xmm12, %xmm11 + pcomleuw 0x100000(%r15), %xmm12, %xmm11 + pcomgtuw 0x100000(%r15), %xmm12, %xmm11 + pcomgeuw 0x100000(%r15), %xmm12, %xmm11 + pcomequw 0x100000(%r15), %xmm12, %xmm11 + pcomnequw 0x100000(%r15), %xmm12, %xmm11 + pcomud $0x4, %xmm13, %xmm12, %xmm11 + pcomud $0x4, 0x100000(%r15), %xmm12, %xmm11 + pcomltud %xmm13, %xmm12, %xmm11 + pcomleud %xmm13, %xmm12, %xmm11 + pcomgtud %xmm13, %xmm12, %xmm11 + pcomgeud %xmm13, %xmm12, %xmm11 + pcomequd %xmm13, %xmm12, %xmm11 + pcomnequd %xmm13, %xmm12, %xmm11 + pcomltud 0x100000(%r15), %xmm12, %xmm11 + pcomleud 0x100000(%r15), %xmm12, %xmm11 + pcomgtud 0x100000(%r15), %xmm12, %xmm11 + pcomgeud 0x100000(%r15), %xmm12, %xmm11 + pcomequd 0x100000(%r15), %xmm12, %xmm11 + pcomnequd 0x100000(%r15), %xmm12, %xmm11 + pcomuq $0x4, %xmm13, %xmm12, %xmm11 + pcomuq $0x4, 0x100000(%r15), %xmm12, %xmm11 + pcomltuq %xmm13, %xmm12, %xmm11 + pcomleuq %xmm13, %xmm12, %xmm11 + pcomgtuq %xmm13, %xmm12, %xmm11 + pcomgeuq %xmm13, %xmm12, %xmm11 + pcomequq %xmm13, %xmm12, %xmm11 + pcomnequq %xmm13, %xmm12, %xmm11 + pcomltuq 0x100000(%r15), %xmm12, %xmm11 + pcomleuq 0x100000(%r15), %xmm12, %xmm11 + pcomgtuq 0x100000(%r15), %xmm12, %xmm11 + pcomgeuq 0x100000(%r15), %xmm12, %xmm11 + pcomequq 0x100000(%r15), %xmm12, %xmm11 + pcomnequq 0x100000(%r15), %xmm12, %xmm11 + + comss $0x4, %xmm3, %xmm12, %xmm1 + comss $0x4, 0x4(%rdx), %xmm12, %xmm1 + comeqss %xmm3, %xmm12, %xmm1 + comltss %xmm3, %xmm12, %xmm1 + comless %xmm3, %xmm12, %xmm1 + comunordss %xmm3, %xmm12, %xmm1 + comness %xmm3, %xmm12, %xmm1 + comnltss %xmm3, %xmm12, %xmm1 + comnless %xmm3, %xmm12, %xmm1 + comordss %xmm3, %xmm12, %xmm1 + comueqss %xmm3, %xmm12, %xmm1 + comultss %xmm3, %xmm12, %xmm1 + comuless %xmm3, %xmm12, %xmm1 + comfalsess %xmm3, %xmm12, %xmm1 + comuness %xmm3, %xmm12, %xmm1 + comunltss %xmm3, %xmm12, %xmm1 + comunless %xmm3, %xmm12, %xmm1 + comtruess %xmm3, %xmm12, %xmm1 + comeqss 0x4(%rdx), %xmm12, %xmm1 + comltss 0x4(%rdx), %xmm12, %xmm1 + comless 0x4(%rdx), %xmm12, %xmm1 + comunordss 0x4(%rdx), %xmm12, %xmm1 + comness 0x4(%rdx), %xmm12, %xmm1 + comnltss 0x4(%rdx), %xmm12, %xmm1 + comnless 0x4(%rdx), %xmm12, %xmm1 + comordss 0x4(%rdx), %xmm12, %xmm1 + comueqss 0x4(%rdx), %xmm12, %xmm1 + comultss 0x4(%rdx), %xmm12, %xmm1 + comuless 0x4(%rdx), %xmm12, %xmm1 + comfalsess 0x4(%rdx), %xmm12, %xmm1 + comuness 0x4(%rdx), %xmm12, %xmm1 + comunltss 0x4(%rdx), %xmm12, %xmm1 + comunless 0x4(%rdx), %xmm12, %xmm1 + comtruess 0x4(%rdx), %xmm12, %xmm1 + comsd $0x4, %xmm3, %xmm12, %xmm1 + comsd $0x4, 0x4(%rdx), %xmm12, %xmm1 + comeqsd %xmm3, %xmm12, %xmm1 + comltsd %xmm3, %xmm12, %xmm1 + comlesd %xmm3, %xmm12, %xmm1 + comunordsd %xmm3, %xmm12, %xmm1 + comnesd %xmm3, %xmm12, %xmm1 + comnltsd %xmm3, %xmm12, %xmm1 + comnlesd %xmm3, %xmm12, %xmm1 + comordsd %xmm3, %xmm12, %xmm1 + comueqsd %xmm3, %xmm12, %xmm1 + comultsd %xmm3, %xmm12, %xmm1 + comulesd %xmm3, %xmm12, %xmm1 + comfalsesd %xmm3, %xmm12, %xmm1 + comunesd %xmm3, %xmm12, %xmm1 + comunltsd %xmm3, %xmm12, %xmm1 + comunlesd %xmm3, %xmm12, %xmm1 + comtruesd %xmm3, %xmm12, %xmm1 + comeqsd 0x4(%rdx), %xmm12, %xmm1 + comltsd 0x4(%rdx), %xmm12, %xmm1 + comlesd 0x4(%rdx), %xmm12, %xmm1 + comunordsd 0x4(%rdx), %xmm12, %xmm1 + comnesd 0x4(%rdx), %xmm12, %xmm1 + comnltsd 0x4(%rdx), %xmm12, %xmm1 + comnlesd 0x4(%rdx), %xmm12, %xmm1 + comordsd 0x4(%rdx), %xmm12, %xmm1 + comueqsd 0x4(%rdx), %xmm12, %xmm1 + comultsd 0x4(%rdx), %xmm12, %xmm1 + comulesd 0x4(%rdx), %xmm12, %xmm1 + comfalsesd 0x4(%rdx), %xmm12, %xmm1 + comunesd 0x4(%rdx), %xmm12, %xmm1 + comunltsd 0x4(%rdx), %xmm12, %xmm1 + comunlesd 0x4(%rdx), %xmm12, %xmm1 + comtruesd 0x4(%rdx), %xmm12, %xmm1 + comps $0x4, %xmm3, %xmm12, %xmm1 + comps $0x4, 0x4(%rdx), %xmm12, %xmm1 + comeqps %xmm3, %xmm12, %xmm1 + comltps %xmm3, %xmm12, %xmm1 + comleps %xmm3, %xmm12, %xmm1 + comunordps %xmm3, %xmm12, %xmm1 + comneps %xmm3, %xmm12, %xmm1 + comnltps %xmm3, %xmm12, %xmm1 + comnleps %xmm3, %xmm12, %xmm1 + comordps %xmm3, %xmm12, %xmm1 + comueqps %xmm3, %xmm12, %xmm1 + comultps %xmm3, %xmm12, %xmm1 + comuleps %xmm3, %xmm12, %xmm1 + comfalseps %xmm3, %xmm12, %xmm1 + comuneps %xmm3, %xmm12, %xmm1 + comunltps %xmm3, %xmm12, %xmm1 + comunleps %xmm3, %xmm12, %xmm1 + comtrueps %xmm3, %xmm12, %xmm1 + comeqps 0x4(%rdx), %xmm12, %xmm1 + comltps 0x4(%rdx), %xmm12, %xmm1 + comleps 0x4(%rdx), %xmm12, %xmm1 + comunordps 0x4(%rdx), %xmm12, %xmm1 + comneps 0x4(%rdx), %xmm12, %xmm1 + comnltps 0x4(%rdx), %xmm12, %xmm1 + comnleps 0x4(%rdx), %xmm12, %xmm1 + comordps 0x4(%rdx), %xmm12, %xmm1 + comueqps 0x4(%rdx), %xmm12, %xmm1 + comultps 0x4(%rdx), %xmm12, %xmm1 + comuleps 0x4(%rdx), %xmm12, %xmm1 + comfalseps 0x4(%rdx), %xmm12, %xmm1 + comuneps 0x4(%rdx), %xmm12, %xmm1 + comunltps 0x4(%rdx), %xmm12, %xmm1 + comunleps 0x4(%rdx), %xmm12, %xmm1 + comtrueps 0x4(%rdx), %xmm12, %xmm1 + compd $0x4, %xmm3, %xmm12, %xmm1 + compd $0x4, 0x4(%rdx), %xmm12, %xmm1 + comeqpd %xmm3, %xmm12, %xmm1 + comltpd %xmm3, %xmm12, %xmm1 + comlepd %xmm3, %xmm12, %xmm1 + comunordpd %xmm3, %xmm12, %xmm1 + comnepd %xmm3, %xmm12, %xmm1 + comnltpd %xmm3, %xmm12, %xmm1 + comnlepd %xmm3, %xmm12, %xmm1 + comordpd %xmm3, %xmm12, %xmm1 + comueqpd %xmm3, %xmm12, %xmm1 + comultpd %xmm3, %xmm12, %xmm1 + comulepd %xmm3, %xmm12, %xmm1 + comfalsepd %xmm3, %xmm12, %xmm1 + comunepd %xmm3, %xmm12, %xmm1 + comunltpd %xmm3, %xmm12, %xmm1 + comunlepd %xmm3, %xmm12, %xmm1 + comtruepd %xmm3, %xmm12, %xmm1 + comeqpd 0x4(%rdx), %xmm12, %xmm1 + comltpd 0x4(%rdx), %xmm12, %xmm1 + comlepd 0x4(%rdx), %xmm12, %xmm1 + comunordpd 0x4(%rdx), %xmm12, %xmm1 + comnepd 0x4(%rdx), %xmm12, %xmm1 + comnltpd 0x4(%rdx), %xmm12, %xmm1 + comnlepd 0x4(%rdx), %xmm12, %xmm1 + comordpd 0x4(%rdx), %xmm12, %xmm1 + comueqpd 0x4(%rdx), %xmm12, %xmm1 + comultpd 0x4(%rdx), %xmm12, %xmm1 + comulepd 0x4(%rdx), %xmm12, %xmm1 + comfalsepd 0x4(%rdx), %xmm12, %xmm1 + comunepd 0x4(%rdx), %xmm12, %xmm1 + comunltpd 0x4(%rdx), %xmm12, %xmm1 + comunlepd 0x4(%rdx), %xmm12, %xmm1 + comtruepd 0x4(%rdx), %xmm12, %xmm1 + + pcomb $0x4, %xmm3, %xmm12, %xmm1 + pcomb $0x4, 0x4(%rdx), %xmm12, %xmm1 + pcomltb %xmm3, %xmm12, %xmm1 + pcomleb %xmm3, %xmm12, %xmm1 + pcomgtb %xmm3, %xmm12, %xmm1 + pcomgeb %xmm3, %xmm12, %xmm1 + pcomeqb %xmm3, %xmm12, %xmm1 + pcomneqb %xmm3, %xmm12, %xmm1 + pcomltb 0x4(%rdx), %xmm12, %xmm1 + pcomleb 0x4(%rdx), %xmm12, %xmm1 + pcomgtb 0x4(%rdx), %xmm12, %xmm1 + pcomgeb 0x4(%rdx), %xmm12, %xmm1 + pcomeqb 0x4(%rdx), %xmm12, %xmm1 + pcomneqb 0x4(%rdx), %xmm12, %xmm1 + pcomw $0x4, %xmm3, %xmm12, %xmm1 + pcomw $0x4, 0x4(%rdx), %xmm12, %xmm1 + pcomltw %xmm3, %xmm12, %xmm1 + pcomlew %xmm3, %xmm12, %xmm1 + pcomgtw %xmm3, %xmm12, %xmm1 + pcomgew %xmm3, %xmm12, %xmm1 + pcomeqw %xmm3, %xmm12, %xmm1 + pcomneqw %xmm3, %xmm12, %xmm1 + pcomltw 0x4(%rdx), %xmm12, %xmm1 + pcomlew 0x4(%rdx), %xmm12, %xmm1 + pcomgtw 0x4(%rdx), %xmm12, %xmm1 + pcomgew 0x4(%rdx), %xmm12, %xmm1 + pcomeqw 0x4(%rdx), %xmm12, %xmm1 + pcomneqw 0x4(%rdx), %xmm12, %xmm1 + pcomd $0x4, %xmm3, %xmm12, %xmm1 + pcomd $0x4, 0x4(%rdx), %xmm12, %xmm1 + pcomltd %xmm3, %xmm12, %xmm1 + pcomled %xmm3, %xmm12, %xmm1 + pcomgtd %xmm3, %xmm12, %xmm1 + pcomged %xmm3, %xmm12, %xmm1 + pcomeqd %xmm3, %xmm12, %xmm1 + pcomneqd %xmm3, %xmm12, %xmm1 + pcomltd 0x4(%rdx), %xmm12, %xmm1 + pcomled 0x4(%rdx), %xmm12, %xmm1 + pcomgtd 0x4(%rdx), %xmm12, %xmm1 + pcomged 0x4(%rdx), %xmm12, %xmm1 + pcomeqd 0x4(%rdx), %xmm12, %xmm1 + pcomneqd 0x4(%rdx), %xmm12, %xmm1 + pcomq $0x4, %xmm3, %xmm12, %xmm1 + pcomq $0x4, 0x4(%rdx), %xmm12, %xmm1 + pcomltq %xmm3, %xmm12, %xmm1 + pcomleq %xmm3, %xmm12, %xmm1 + pcomgtq %xmm3, %xmm12, %xmm1 + pcomgeq %xmm3, %xmm12, %xmm1 + pcomeqq %xmm3, %xmm12, %xmm1 + pcomneqq %xmm3, %xmm12, %xmm1 + pcomltq 0x4(%rdx), %xmm12, %xmm1 + pcomleq 0x4(%rdx), %xmm12, %xmm1 + pcomgtq 0x4(%rdx), %xmm12, %xmm1 + pcomgeq 0x4(%rdx), %xmm12, %xmm1 + pcomeqq 0x4(%rdx), %xmm12, %xmm1 + pcomneqq 0x4(%rdx), %xmm12, %xmm1 + + pcomub $0x4, %xmm3, %xmm12, %xmm1 + pcomub $0x4, 0x4(%rdx), %xmm12, %xmm1 + pcomltub %xmm3, %xmm12, %xmm1 + pcomleub %xmm3, %xmm12, %xmm1 + pcomgtub %xmm3, %xmm12, %xmm1 + pcomgeub %xmm3, %xmm12, %xmm1 + pcomequb %xmm3, %xmm12, %xmm1 + pcomnequb %xmm3, %xmm12, %xmm1 + pcomltub 0x4(%rdx), %xmm12, %xmm1 + pcomleub 0x4(%rdx), %xmm12, %xmm1 + pcomgtub 0x4(%rdx), %xmm12, %xmm1 + pcomgeub 0x4(%rdx), %xmm12, %xmm1 + pcomequb 0x4(%rdx), %xmm12, %xmm1 + pcomnequb 0x4(%rdx), %xmm12, %xmm1 + pcomuw $0x4, %xmm3, %xmm12, %xmm1 + pcomuw $0x4, 0x4(%rdx), %xmm12, %xmm1 + pcomltuw %xmm3, %xmm12, %xmm1 + pcomleuw %xmm3, %xmm12, %xmm1 + pcomgtuw %xmm3, %xmm12, %xmm1 + pcomgeuw %xmm3, %xmm12, %xmm1 + pcomequw %xmm3, %xmm12, %xmm1 + pcomnequw %xmm3, %xmm12, %xmm1 + pcomltuw 0x4(%rdx), %xmm12, %xmm1 + pcomleuw 0x4(%rdx), %xmm12, %xmm1 + pcomgtuw 0x4(%rdx), %xmm12, %xmm1 + pcomgeuw 0x4(%rdx), %xmm12, %xmm1 + pcomequw 0x4(%rdx), %xmm12, %xmm1 + pcomnequw 0x4(%rdx), %xmm12, %xmm1 + pcomud $0x4, %xmm3, %xmm12, %xmm1 + pcomud $0x4, 0x4(%rdx), %xmm12, %xmm1 + pcomltud %xmm3, %xmm12, %xmm1 + pcomleud %xmm3, %xmm12, %xmm1 + pcomgtud %xmm3, %xmm12, %xmm1 + pcomgeud %xmm3, %xmm12, %xmm1 + pcomequd %xmm3, %xmm12, %xmm1 + pcomnequd %xmm3, %xmm12, %xmm1 + pcomltud 0x4(%rdx), %xmm12, %xmm1 + pcomleud 0x4(%rdx), %xmm12, %xmm1 + pcomgtud 0x4(%rdx), %xmm12, %xmm1 + pcomgeud 0x4(%rdx), %xmm12, %xmm1 + pcomequd 0x4(%rdx), %xmm12, %xmm1 + pcomnequd 0x4(%rdx), %xmm12, %xmm1 + pcomuq $0x4, %xmm3, %xmm12, %xmm1 + pcomuq $0x4, 0x4(%rdx), %xmm12, %xmm1 + pcomltuq %xmm3, %xmm12, %xmm1 + pcomleuq %xmm3, %xmm12, %xmm1 + pcomgtuq %xmm3, %xmm12, %xmm1 + pcomgeuq %xmm3, %xmm12, %xmm1 + pcomequq %xmm3, %xmm12, %xmm1 + pcomnequq %xmm3, %xmm12, %xmm1 + pcomltuq 0x4(%rdx), %xmm12, %xmm1 + pcomleuq 0x4(%rdx), %xmm12, %xmm1 + pcomgtuq 0x4(%rdx), %xmm12, %xmm1 + pcomgeuq 0x4(%rdx), %xmm12, %xmm1 + pcomequq 0x4(%rdx), %xmm12, %xmm1 + pcomnequq 0x4(%rdx), %xmm12, %xmm1 + + comss $0x4, %xmm3, %xmm2, %xmm11 + comss $0x4, 0x4(%rdx), %xmm2, %xmm11 + comeqss %xmm3, %xmm2, %xmm11 + comltss %xmm3, %xmm2, %xmm11 + comless %xmm3, %xmm2, %xmm11 + comunordss %xmm3, %xmm2, %xmm11 + comness %xmm3, %xmm2, %xmm11 + comnltss %xmm3, %xmm2, %xmm11 + comnless %xmm3, %xmm2, %xmm11 + comordss %xmm3, %xmm2, %xmm11 + comueqss %xmm3, %xmm2, %xmm11 + comultss %xmm3, %xmm2, %xmm11 + comuless %xmm3, %xmm2, %xmm11 + comfalsess %xmm3, %xmm2, %xmm11 + comuness %xmm3, %xmm2, %xmm11 + comunltss %xmm3, %xmm2, %xmm11 + comunless %xmm3, %xmm2, %xmm11 + comtruess %xmm3, %xmm2, %xmm11 + comeqss 0x4(%rdx), %xmm2, %xmm11 + comltss 0x4(%rdx), %xmm2, %xmm11 + comless 0x4(%rdx), %xmm2, %xmm11 + comunordss 0x4(%rdx), %xmm2, %xmm11 + comness 0x4(%rdx), %xmm2, %xmm11 + comnltss 0x4(%rdx), %xmm2, %xmm11 + comnless 0x4(%rdx), %xmm2, %xmm11 + comordss 0x4(%rdx), %xmm2, %xmm11 + comueqss 0x4(%rdx), %xmm2, %xmm11 + comultss 0x4(%rdx), %xmm2, %xmm11 + comuless 0x4(%rdx), %xmm2, %xmm11 + comfalsess 0x4(%rdx), %xmm2, %xmm11 + comuness 0x4(%rdx), %xmm2, %xmm11 + comunltss 0x4(%rdx), %xmm2, %xmm11 + comunless 0x4(%rdx), %xmm2, %xmm11 + comtruess 0x4(%rdx), %xmm2, %xmm11 + comsd $0x4, %xmm3, %xmm2, %xmm11 + comsd $0x4, 0x4(%rdx), %xmm2, %xmm11 + comeqsd %xmm3, %xmm2, %xmm11 + comltsd %xmm3, %xmm2, %xmm11 + comlesd %xmm3, %xmm2, %xmm11 + comunordsd %xmm3, %xmm2, %xmm11 + comnesd %xmm3, %xmm2, %xmm11 + comnltsd %xmm3, %xmm2, %xmm11 + comnlesd %xmm3, %xmm2, %xmm11 + comordsd %xmm3, %xmm2, %xmm11 + comueqsd %xmm3, %xmm2, %xmm11 + comultsd %xmm3, %xmm2, %xmm11 + comulesd %xmm3, %xmm2, %xmm11 + comfalsesd %xmm3, %xmm2, %xmm11 + comunesd %xmm3, %xmm2, %xmm11 + comunltsd %xmm3, %xmm2, %xmm11 + comunlesd %xmm3, %xmm2, %xmm11 + comtruesd %xmm3, %xmm2, %xmm11 + comeqsd 0x4(%rdx), %xmm2, %xmm11 + comltsd 0x4(%rdx), %xmm2, %xmm11 + comlesd 0x4(%rdx), %xmm2, %xmm11 + comunordsd 0x4(%rdx), %xmm2, %xmm11 + comnesd 0x4(%rdx), %xmm2, %xmm11 + comnltsd 0x4(%rdx), %xmm2, %xmm11 + comnlesd 0x4(%rdx), %xmm2, %xmm11 + comordsd 0x4(%rdx), %xmm2, %xmm11 + comueqsd 0x4(%rdx), %xmm2, %xmm11 + comultsd 0x4(%rdx), %xmm2, %xmm11 + comulesd 0x4(%rdx), %xmm2, %xmm11 + comfalsesd 0x4(%rdx), %xmm2, %xmm11 + comunesd 0x4(%rdx), %xmm2, %xmm11 + comunltsd 0x4(%rdx), %xmm2, %xmm11 + comunlesd 0x4(%rdx), %xmm2, %xmm11 + comtruesd 0x4(%rdx), %xmm2, %xmm11 + comps $0x4, %xmm3, %xmm2, %xmm11 + comps $0x4, 0x4(%rdx), %xmm2, %xmm11 + comeqps %xmm3, %xmm2, %xmm11 + comltps %xmm3, %xmm2, %xmm11 + comleps %xmm3, %xmm2, %xmm11 + comunordps %xmm3, %xmm2, %xmm11 + comneps %xmm3, %xmm2, %xmm11 + comnltps %xmm3, %xmm2, %xmm11 + comnleps %xmm3, %xmm2, %xmm11 + comordps %xmm3, %xmm2, %xmm11 + comueqps %xmm3, %xmm2, %xmm11 + comultps %xmm3, %xmm2, %xmm11 + comuleps %xmm3, %xmm2, %xmm11 + comfalseps %xmm3, %xmm2, %xmm11 + comuneps %xmm3, %xmm2, %xmm11 + comunltps %xmm3, %xmm2, %xmm11 + comunleps %xmm3, %xmm2, %xmm11 + comtrueps %xmm3, %xmm2, %xmm11 + comeqps 0x4(%rdx), %xmm2, %xmm11 + comltps 0x4(%rdx), %xmm2, %xmm11 + comleps 0x4(%rdx), %xmm2, %xmm11 + comunordps 0x4(%rdx), %xmm2, %xmm11 + comneps 0x4(%rdx), %xmm2, %xmm11 + comnltps 0x4(%rdx), %xmm2, %xmm11 + comnleps 0x4(%rdx), %xmm2, %xmm11 + comordps 0x4(%rdx), %xmm2, %xmm11 + comueqps 0x4(%rdx), %xmm2, %xmm11 + comultps 0x4(%rdx), %xmm2, %xmm11 + comuleps 0x4(%rdx), %xmm2, %xmm11 + comfalseps 0x4(%rdx), %xmm2, %xmm11 + comuneps 0x4(%rdx), %xmm2, %xmm11 + comunltps 0x4(%rdx), %xmm2, %xmm11 + comunleps 0x4(%rdx), %xmm2, %xmm11 + comtrueps 0x4(%rdx), %xmm2, %xmm11 + compd $0x4, %xmm3, %xmm2, %xmm11 + compd $0x4, 0x4(%rdx), %xmm2, %xmm11 + comeqpd %xmm3, %xmm2, %xmm11 + comltpd %xmm3, %xmm2, %xmm11 + comlepd %xmm3, %xmm2, %xmm11 + comunordpd %xmm3, %xmm2, %xmm11 + comnepd %xmm3, %xmm2, %xmm11 + comnltpd %xmm3, %xmm2, %xmm11 + comnlepd %xmm3, %xmm2, %xmm11 + comordpd %xmm3, %xmm2, %xmm11 + comueqpd %xmm3, %xmm2, %xmm11 + comultpd %xmm3, %xmm2, %xmm11 + comulepd %xmm3, %xmm2, %xmm11 + comfalsepd %xmm3, %xmm2, %xmm11 + comunepd %xmm3, %xmm2, %xmm11 + comunltpd %xmm3, %xmm2, %xmm11 + comunlepd %xmm3, %xmm2, %xmm11 + comtruepd %xmm3, %xmm2, %xmm11 + comeqpd 0x4(%rdx), %xmm2, %xmm11 + comltpd 0x4(%rdx), %xmm2, %xmm11 + comlepd 0x4(%rdx), %xmm2, %xmm11 + comunordpd 0x4(%rdx), %xmm2, %xmm11 + comnepd 0x4(%rdx), %xmm2, %xmm11 + comnltpd 0x4(%rdx), %xmm2, %xmm11 + comnlepd 0x4(%rdx), %xmm2, %xmm11 + comordpd 0x4(%rdx), %xmm2, %xmm11 + comueqpd 0x4(%rdx), %xmm2, %xmm11 + comultpd 0x4(%rdx), %xmm2, %xmm11 + comulepd 0x4(%rdx), %xmm2, %xmm11 + comfalsepd 0x4(%rdx), %xmm2, %xmm11 + comunepd 0x4(%rdx), %xmm2, %xmm11 + comunltpd 0x4(%rdx), %xmm2, %xmm11 + comunlepd 0x4(%rdx), %xmm2, %xmm11 + comtruepd 0x4(%rdx), %xmm2, %xmm11 + + pcomb $0x4, %xmm3, %xmm2, %xmm11 + pcomb $0x4, 0x4(%rdx), %xmm2, %xmm11 + pcomltb %xmm3, %xmm2, %xmm11 + pcomleb %xmm3, %xmm2, %xmm11 + pcomgtb %xmm3, %xmm2, %xmm11 + pcomgeb %xmm3, %xmm2, %xmm11 + pcomeqb %xmm3, %xmm2, %xmm11 + pcomneqb %xmm3, %xmm2, %xmm11 + pcomltb 0x4(%rdx), %xmm2, %xmm11 + pcomleb 0x4(%rdx), %xmm2, %xmm11 + pcomgtb 0x4(%rdx), %xmm2, %xmm11 + pcomgeb 0x4(%rdx), %xmm2, %xmm11 + pcomeqb 0x4(%rdx), %xmm2, %xmm11 + pcomneqb 0x4(%rdx), %xmm2, %xmm11 + pcomw $0x4, %xmm3, %xmm2, %xmm11 + pcomw $0x4, 0x4(%rdx), %xmm2, %xmm11 + pcomltw %xmm3, %xmm2, %xmm11 + pcomlew %xmm3, %xmm2, %xmm11 + pcomgtw %xmm3, %xmm2, %xmm11 + pcomgew %xmm3, %xmm2, %xmm11 + pcomeqw %xmm3, %xmm2, %xmm11 + pcomneqw %xmm3, %xmm2, %xmm11 + pcomltw 0x4(%rdx), %xmm2, %xmm11 + pcomlew 0x4(%rdx), %xmm2, %xmm11 + pcomgtw 0x4(%rdx), %xmm2, %xmm11 + pcomgew 0x4(%rdx), %xmm2, %xmm11 + pcomeqw 0x4(%rdx), %xmm2, %xmm11 + pcomneqw 0x4(%rdx), %xmm2, %xmm11 + pcomd $0x4, %xmm3, %xmm2, %xmm11 + pcomd $0x4, 0x4(%rdx), %xmm2, %xmm11 + pcomltd %xmm3, %xmm2, %xmm11 + pcomled %xmm3, %xmm2, %xmm11 + pcomgtd %xmm3, %xmm2, %xmm11 + pcomged %xmm3, %xmm2, %xmm11 + pcomeqd %xmm3, %xmm2, %xmm11 + pcomneqd %xmm3, %xmm2, %xmm11 + pcomltd 0x4(%rdx), %xmm2, %xmm11 + pcomled 0x4(%rdx), %xmm2, %xmm11 + pcomgtd 0x4(%rdx), %xmm2, %xmm11 + pcomged 0x4(%rdx), %xmm2, %xmm11 + pcomeqd 0x4(%rdx), %xmm2, %xmm11 + pcomneqd 0x4(%rdx), %xmm2, %xmm11 + pcomq $0x4, %xmm3, %xmm2, %xmm11 + pcomq $0x4, 0x4(%rdx), %xmm2, %xmm11 + pcomltq %xmm3, %xmm2, %xmm11 + pcomleq %xmm3, %xmm2, %xmm11 + pcomgtq %xmm3, %xmm2, %xmm11 + pcomgeq %xmm3, %xmm2, %xmm11 + pcomeqq %xmm3, %xmm2, %xmm11 + pcomneqq %xmm3, %xmm2, %xmm11 + pcomltq 0x4(%rdx), %xmm2, %xmm11 + pcomleq 0x4(%rdx), %xmm2, %xmm11 + pcomgtq 0x4(%rdx), %xmm2, %xmm11 + pcomgeq 0x4(%rdx), %xmm2, %xmm11 + pcomeqq 0x4(%rdx), %xmm2, %xmm11 + pcomneqq 0x4(%rdx), %xmm2, %xmm11 + + pcomub $0x4, %xmm3, %xmm2, %xmm11 + pcomub $0x4, 0x4(%rdx), %xmm2, %xmm11 + pcomltub %xmm3, %xmm2, %xmm11 + pcomleub %xmm3, %xmm2, %xmm11 + pcomgtub %xmm3, %xmm2, %xmm11 + pcomgeub %xmm3, %xmm2, %xmm11 + pcomequb %xmm3, %xmm2, %xmm11 + pcomnequb %xmm3, %xmm2, %xmm11 + pcomltub 0x4(%rdx), %xmm2, %xmm11 + pcomleub 0x4(%rdx), %xmm2, %xmm11 + pcomgtub 0x4(%rdx), %xmm2, %xmm11 + pcomgeub 0x4(%rdx), %xmm2, %xmm11 + pcomequb 0x4(%rdx), %xmm2, %xmm11 + pcomnequb 0x4(%rdx), %xmm2, %xmm11 + pcomuw $0x4, %xmm3, %xmm2, %xmm11 + pcomuw $0x4, 0x4(%rdx), %xmm2, %xmm11 + pcomltuw %xmm3, %xmm2, %xmm11 + pcomleuw %xmm3, %xmm2, %xmm11 + pcomgtuw %xmm3, %xmm2, %xmm11 + pcomgeuw %xmm3, %xmm2, %xmm11 + pcomequw %xmm3, %xmm2, %xmm11 + pcomnequw %xmm3, %xmm2, %xmm11 + pcomltuw 0x4(%rdx), %xmm2, %xmm11 + pcomleuw 0x4(%rdx), %xmm2, %xmm11 + pcomgtuw 0x4(%rdx), %xmm2, %xmm11 + pcomgeuw 0x4(%rdx), %xmm2, %xmm11 + pcomequw 0x4(%rdx), %xmm2, %xmm11 + pcomnequw 0x4(%rdx), %xmm2, %xmm11 + pcomud $0x4, %xmm3, %xmm2, %xmm11 + pcomud $0x4, 0x4(%rdx), %xmm2, %xmm11 + pcomltud %xmm3, %xmm2, %xmm11 + pcomleud %xmm3, %xmm2, %xmm11 + pcomgtud %xmm3, %xmm2, %xmm11 + pcomgeud %xmm3, %xmm2, %xmm11 + pcomequd %xmm3, %xmm2, %xmm11 + pcomnequd %xmm3, %xmm2, %xmm11 + pcomltud 0x4(%rdx), %xmm2, %xmm11 + pcomleud 0x4(%rdx), %xmm2, %xmm11 + pcomgtud 0x4(%rdx), %xmm2, %xmm11 + pcomgeud 0x4(%rdx), %xmm2, %xmm11 + pcomequd 0x4(%rdx), %xmm2, %xmm11 + pcomnequd 0x4(%rdx), %xmm2, %xmm11 + pcomuq $0x4, %xmm3, %xmm2, %xmm11 + pcomuq $0x4, 0x4(%rdx), %xmm2, %xmm11 + pcomltuq %xmm3, %xmm2, %xmm11 + pcomleuq %xmm3, %xmm2, %xmm11 + pcomgtuq %xmm3, %xmm2, %xmm11 + pcomgeuq %xmm3, %xmm2, %xmm11 + pcomequq %xmm3, %xmm2, %xmm11 + pcomnequq %xmm3, %xmm2, %xmm11 + pcomltuq 0x4(%rdx), %xmm2, %xmm11 + pcomleuq 0x4(%rdx), %xmm2, %xmm11 + pcomgtuq 0x4(%rdx), %xmm2, %xmm11 + pcomgeuq 0x4(%rdx), %xmm2, %xmm11 + pcomequq 0x4(%rdx), %xmm2, %xmm11 + pcomnequq 0x4(%rdx), %xmm2, %xmm11 + + comss $0x4, %xmm13, %xmm2, %xmm1 + comss $0x4, 0x4(%rdx), %xmm2, %xmm1 + comeqss %xmm13, %xmm2, %xmm1 + comltss %xmm13, %xmm2, %xmm1 + comless %xmm13, %xmm2, %xmm1 + comunordss %xmm13, %xmm2, %xmm1 + comness %xmm13, %xmm2, %xmm1 + comnltss %xmm13, %xmm2, %xmm1 + comnless %xmm13, %xmm2, %xmm1 + comordss %xmm13, %xmm2, %xmm1 + comueqss %xmm13, %xmm2, %xmm1 + comultss %xmm13, %xmm2, %xmm1 + comuless %xmm13, %xmm2, %xmm1 + comfalsess %xmm13, %xmm2, %xmm1 + comuness %xmm13, %xmm2, %xmm1 + comunltss %xmm13, %xmm2, %xmm1 + comunless %xmm13, %xmm2, %xmm1 + comtruess %xmm13, %xmm2, %xmm1 + comeqss 0x4(%rdx), %xmm2, %xmm1 + comltss 0x4(%rdx), %xmm2, %xmm1 + comless 0x4(%rdx), %xmm2, %xmm1 + comunordss 0x4(%rdx), %xmm2, %xmm1 + comness 0x4(%rdx), %xmm2, %xmm1 + comnltss 0x4(%rdx), %xmm2, %xmm1 + comnless 0x4(%rdx), %xmm2, %xmm1 + comordss 0x4(%rdx), %xmm2, %xmm1 + comueqss 0x4(%rdx), %xmm2, %xmm1 + comultss 0x4(%rdx), %xmm2, %xmm1 + comuless 0x4(%rdx), %xmm2, %xmm1 + comfalsess 0x4(%rdx), %xmm2, %xmm1 + comuness 0x4(%rdx), %xmm2, %xmm1 + comunltss 0x4(%rdx), %xmm2, %xmm1 + comunless 0x4(%rdx), %xmm2, %xmm1 + comtruess 0x4(%rdx), %xmm2, %xmm1 + comsd $0x4, %xmm13, %xmm2, %xmm1 + comsd $0x4, 0x4(%rdx), %xmm2, %xmm1 + comeqsd %xmm13, %xmm2, %xmm1 + comltsd %xmm13, %xmm2, %xmm1 + comlesd %xmm13, %xmm2, %xmm1 + comunordsd %xmm13, %xmm2, %xmm1 + comnesd %xmm13, %xmm2, %xmm1 + comnltsd %xmm13, %xmm2, %xmm1 + comnlesd %xmm13, %xmm2, %xmm1 + comordsd %xmm13, %xmm2, %xmm1 + comueqsd %xmm13, %xmm2, %xmm1 + comultsd %xmm13, %xmm2, %xmm1 + comulesd %xmm13, %xmm2, %xmm1 + comfalsesd %xmm13, %xmm2, %xmm1 + comunesd %xmm13, %xmm2, %xmm1 + comunltsd %xmm13, %xmm2, %xmm1 + comunlesd %xmm13, %xmm2, %xmm1 + comtruesd %xmm13, %xmm2, %xmm1 + comeqsd 0x4(%rdx), %xmm2, %xmm1 + comltsd 0x4(%rdx), %xmm2, %xmm1 + comlesd 0x4(%rdx), %xmm2, %xmm1 + comunordsd 0x4(%rdx), %xmm2, %xmm1 + comnesd 0x4(%rdx), %xmm2, %xmm1 + comnltsd 0x4(%rdx), %xmm2, %xmm1 + comnlesd 0x4(%rdx), %xmm2, %xmm1 + comordsd 0x4(%rdx), %xmm2, %xmm1 + comueqsd 0x4(%rdx), %xmm2, %xmm1 + comultsd 0x4(%rdx), %xmm2, %xmm1 + comulesd 0x4(%rdx), %xmm2, %xmm1 + comfalsesd 0x4(%rdx), %xmm2, %xmm1 + comunesd 0x4(%rdx), %xmm2, %xmm1 + comunltsd 0x4(%rdx), %xmm2, %xmm1 + comunlesd 0x4(%rdx), %xmm2, %xmm1 + comtruesd 0x4(%rdx), %xmm2, %xmm1 + comps $0x4, %xmm13, %xmm2, %xmm1 + comps $0x4, 0x4(%rdx), %xmm2, %xmm1 + comeqps %xmm13, %xmm2, %xmm1 + comltps %xmm13, %xmm2, %xmm1 + comleps %xmm13, %xmm2, %xmm1 + comunordps %xmm13, %xmm2, %xmm1 + comneps %xmm13, %xmm2, %xmm1 + comnltps %xmm13, %xmm2, %xmm1 + comnleps %xmm13, %xmm2, %xmm1 + comordps %xmm13, %xmm2, %xmm1 + comueqps %xmm13, %xmm2, %xmm1 + comultps %xmm13, %xmm2, %xmm1 + comuleps %xmm13, %xmm2, %xmm1 + comfalseps %xmm13, %xmm2, %xmm1 + comuneps %xmm13, %xmm2, %xmm1 + comunltps %xmm13, %xmm2, %xmm1 + comunleps %xmm13, %xmm2, %xmm1 + comtrueps %xmm13, %xmm2, %xmm1 + comeqps 0x4(%rdx), %xmm2, %xmm1 + comltps 0x4(%rdx), %xmm2, %xmm1 + comleps 0x4(%rdx), %xmm2, %xmm1 + comunordps 0x4(%rdx), %xmm2, %xmm1 + comneps 0x4(%rdx), %xmm2, %xmm1 + comnltps 0x4(%rdx), %xmm2, %xmm1 + comnleps 0x4(%rdx), %xmm2, %xmm1 + comordps 0x4(%rdx), %xmm2, %xmm1 + comueqps 0x4(%rdx), %xmm2, %xmm1 + comultps 0x4(%rdx), %xmm2, %xmm1 + comuleps 0x4(%rdx), %xmm2, %xmm1 + comfalseps 0x4(%rdx), %xmm2, %xmm1 + comuneps 0x4(%rdx), %xmm2, %xmm1 + comunltps 0x4(%rdx), %xmm2, %xmm1 + comunleps 0x4(%rdx), %xmm2, %xmm1 + comtrueps 0x4(%rdx), %xmm2, %xmm1 + compd $0x4, %xmm13, %xmm2, %xmm1 + compd $0x4, 0x4(%rdx), %xmm2, %xmm1 + comeqpd %xmm13, %xmm2, %xmm1 + comltpd %xmm13, %xmm2, %xmm1 + comlepd %xmm13, %xmm2, %xmm1 + comunordpd %xmm13, %xmm2, %xmm1 + comnepd %xmm13, %xmm2, %xmm1 + comnltpd %xmm13, %xmm2, %xmm1 + comnlepd %xmm13, %xmm2, %xmm1 + comordpd %xmm13, %xmm2, %xmm1 + comueqpd %xmm13, %xmm2, %xmm1 + comultpd %xmm13, %xmm2, %xmm1 + comulepd %xmm13, %xmm2, %xmm1 + comfalsepd %xmm13, %xmm2, %xmm1 + comunepd %xmm13, %xmm2, %xmm1 + comunltpd %xmm13, %xmm2, %xmm1 + comunlepd %xmm13, %xmm2, %xmm1 + comtruepd %xmm13, %xmm2, %xmm1 + comeqpd 0x4(%rdx), %xmm2, %xmm1 + comltpd 0x4(%rdx), %xmm2, %xmm1 + comlepd 0x4(%rdx), %xmm2, %xmm1 + comunordpd 0x4(%rdx), %xmm2, %xmm1 + comnepd 0x4(%rdx), %xmm2, %xmm1 + comnltpd 0x4(%rdx), %xmm2, %xmm1 + comnlepd 0x4(%rdx), %xmm2, %xmm1 + comordpd 0x4(%rdx), %xmm2, %xmm1 + comueqpd 0x4(%rdx), %xmm2, %xmm1 + comultpd 0x4(%rdx), %xmm2, %xmm1 + comulepd 0x4(%rdx), %xmm2, %xmm1 + comfalsepd 0x4(%rdx), %xmm2, %xmm1 + comunepd 0x4(%rdx), %xmm2, %xmm1 + comunltpd 0x4(%rdx), %xmm2, %xmm1 + comunlepd 0x4(%rdx), %xmm2, %xmm1 + comtruepd 0x4(%rdx), %xmm2, %xmm1 + + pcomb $0x4, %xmm13, %xmm2, %xmm1 + pcomb $0x4, 0x4(%rdx), %xmm2, %xmm1 + pcomltb %xmm13, %xmm2, %xmm1 + pcomleb %xmm13, %xmm2, %xmm1 + pcomgtb %xmm13, %xmm2, %xmm1 + pcomgeb %xmm13, %xmm2, %xmm1 + pcomeqb %xmm13, %xmm2, %xmm1 + pcomneqb %xmm13, %xmm2, %xmm1 + pcomltb 0x4(%rdx), %xmm2, %xmm1 + pcomleb 0x4(%rdx), %xmm2, %xmm1 + pcomgtb 0x4(%rdx), %xmm2, %xmm1 + pcomgeb 0x4(%rdx), %xmm2, %xmm1 + pcomeqb 0x4(%rdx), %xmm2, %xmm1 + pcomneqb 0x4(%rdx), %xmm2, %xmm1 + pcomw $0x4, %xmm13, %xmm2, %xmm1 + pcomw $0x4, 0x4(%rdx), %xmm2, %xmm1 + pcomltw %xmm13, %xmm2, %xmm1 + pcomlew %xmm13, %xmm2, %xmm1 + pcomgtw %xmm13, %xmm2, %xmm1 + pcomgew %xmm13, %xmm2, %xmm1 + pcomeqw %xmm13, %xmm2, %xmm1 + pcomneqw %xmm13, %xmm2, %xmm1 + pcomltw 0x4(%rdx), %xmm2, %xmm1 + pcomlew 0x4(%rdx), %xmm2, %xmm1 + pcomgtw 0x4(%rdx), %xmm2, %xmm1 + pcomgew 0x4(%rdx), %xmm2, %xmm1 + pcomeqw 0x4(%rdx), %xmm2, %xmm1 + pcomneqw 0x4(%rdx), %xmm2, %xmm1 + pcomd $0x4, %xmm13, %xmm2, %xmm1 + pcomd $0x4, 0x4(%rdx), %xmm2, %xmm1 + pcomltd %xmm13, %xmm2, %xmm1 + pcomled %xmm13, %xmm2, %xmm1 + pcomgtd %xmm13, %xmm2, %xmm1 + pcomged %xmm13, %xmm2, %xmm1 + pcomeqd %xmm13, %xmm2, %xmm1 + pcomneqd %xmm13, %xmm2, %xmm1 + pcomltd 0x4(%rdx), %xmm2, %xmm1 + pcomled 0x4(%rdx), %xmm2, %xmm1 + pcomgtd 0x4(%rdx), %xmm2, %xmm1 + pcomged 0x4(%rdx), %xmm2, %xmm1 + pcomeqd 0x4(%rdx), %xmm2, %xmm1 + pcomneqd 0x4(%rdx), %xmm2, %xmm1 + pcomq $0x4, %xmm13, %xmm2, %xmm1 + pcomq $0x4, 0x4(%rdx), %xmm2, %xmm1 + pcomltq %xmm13, %xmm2, %xmm1 + pcomleq %xmm13, %xmm2, %xmm1 + pcomgtq %xmm13, %xmm2, %xmm1 + pcomgeq %xmm13, %xmm2, %xmm1 + pcomeqq %xmm13, %xmm2, %xmm1 + pcomneqq %xmm13, %xmm2, %xmm1 + pcomltq 0x4(%rdx), %xmm2, %xmm1 + pcomleq 0x4(%rdx), %xmm2, %xmm1 + pcomgtq 0x4(%rdx), %xmm2, %xmm1 + pcomgeq 0x4(%rdx), %xmm2, %xmm1 + pcomeqq 0x4(%rdx), %xmm2, %xmm1 + pcomneqq 0x4(%rdx), %xmm2, %xmm1 + + pcomub $0x4, %xmm13, %xmm2, %xmm1 + pcomub $0x4, 0x4(%rdx), %xmm2, %xmm1 + pcomltub %xmm13, %xmm2, %xmm1 + pcomleub %xmm13, %xmm2, %xmm1 + pcomgtub %xmm13, %xmm2, %xmm1 + pcomgeub %xmm13, %xmm2, %xmm1 + pcomequb %xmm13, %xmm2, %xmm1 + pcomnequb %xmm13, %xmm2, %xmm1 + pcomltub 0x4(%rdx), %xmm2, %xmm1 + pcomleub 0x4(%rdx), %xmm2, %xmm1 + pcomgtub 0x4(%rdx), %xmm2, %xmm1 + pcomgeub 0x4(%rdx), %xmm2, %xmm1 + pcomequb 0x4(%rdx), %xmm2, %xmm1 + pcomnequb 0x4(%rdx), %xmm2, %xmm1 + pcomuw $0x4, %xmm13, %xmm2, %xmm1 + pcomuw $0x4, 0x4(%rdx), %xmm2, %xmm1 + pcomltuw %xmm13, %xmm2, %xmm1 + pcomleuw %xmm13, %xmm2, %xmm1 + pcomgtuw %xmm13, %xmm2, %xmm1 + pcomgeuw %xmm13, %xmm2, %xmm1 + pcomequw %xmm13, %xmm2, %xmm1 + pcomnequw %xmm13, %xmm2, %xmm1 + pcomltuw 0x4(%rdx), %xmm2, %xmm1 + pcomleuw 0x4(%rdx), %xmm2, %xmm1 + pcomgtuw 0x4(%rdx), %xmm2, %xmm1 + pcomgeuw 0x4(%rdx), %xmm2, %xmm1 + pcomequw 0x4(%rdx), %xmm2, %xmm1 + pcomnequw 0x4(%rdx), %xmm2, %xmm1 + pcomud $0x4, %xmm13, %xmm2, %xmm1 + pcomud $0x4, 0x4(%rdx), %xmm2, %xmm1 + pcomltud %xmm13, %xmm2, %xmm1 + pcomleud %xmm13, %xmm2, %xmm1 + pcomgtud %xmm13, %xmm2, %xmm1 + pcomgeud %xmm13, %xmm2, %xmm1 + pcomequd %xmm13, %xmm2, %xmm1 + pcomnequd %xmm13, %xmm2, %xmm1 + pcomltud 0x4(%rdx), %xmm2, %xmm1 + pcomleud 0x4(%rdx), %xmm2, %xmm1 + pcomgtud 0x4(%rdx), %xmm2, %xmm1 + pcomgeud 0x4(%rdx), %xmm2, %xmm1 + pcomequd 0x4(%rdx), %xmm2, %xmm1 + pcomnequd 0x4(%rdx), %xmm2, %xmm1 + pcomuq $0x4, %xmm13, %xmm2, %xmm1 + pcomuq $0x4, 0x4(%rdx), %xmm2, %xmm1 + pcomltuq %xmm13, %xmm2, %xmm1 + pcomleuq %xmm13, %xmm2, %xmm1 + pcomgtuq %xmm13, %xmm2, %xmm1 + pcomgeuq %xmm13, %xmm2, %xmm1 + pcomequq %xmm13, %xmm2, %xmm1 + pcomnequq %xmm13, %xmm2, %xmm1 + pcomltuq 0x4(%rdx), %xmm2, %xmm1 + pcomleuq 0x4(%rdx), %xmm2, %xmm1 + pcomgtuq 0x4(%rdx), %xmm2, %xmm1 + pcomgeuq 0x4(%rdx), %xmm2, %xmm1 + pcomequq 0x4(%rdx), %xmm2, %xmm1 + pcomnequq 0x4(%rdx), %xmm2, %xmm1 + + comss $0x4, %xmm3, %xmm2, %xmm1 + comss $0x4, 0x100000(%r15), %xmm2, %xmm1 + comeqss %xmm3, %xmm2, %xmm1 + comltss %xmm3, %xmm2, %xmm1 + comless %xmm3, %xmm2, %xmm1 + comunordss %xmm3, %xmm2, %xmm1 + comness %xmm3, %xmm2, %xmm1 + comnltss %xmm3, %xmm2, %xmm1 + comnless %xmm3, %xmm2, %xmm1 + comordss %xmm3, %xmm2, %xmm1 + comueqss %xmm3, %xmm2, %xmm1 + comultss %xmm3, %xmm2, %xmm1 + comuless %xmm3, %xmm2, %xmm1 + comfalsess %xmm3, %xmm2, %xmm1 + comuness %xmm3, %xmm2, %xmm1 + comunltss %xmm3, %xmm2, %xmm1 + comunless %xmm3, %xmm2, %xmm1 + comtruess %xmm3, %xmm2, %xmm1 + comeqss 0x100000(%r15), %xmm2, %xmm1 + comltss 0x100000(%r15), %xmm2, %xmm1 + comless 0x100000(%r15), %xmm2, %xmm1 + comunordss 0x100000(%r15), %xmm2, %xmm1 + comness 0x100000(%r15), %xmm2, %xmm1 + comnltss 0x100000(%r15), %xmm2, %xmm1 + comnless 0x100000(%r15), %xmm2, %xmm1 + comordss 0x100000(%r15), %xmm2, %xmm1 + comueqss 0x100000(%r15), %xmm2, %xmm1 + comultss 0x100000(%r15), %xmm2, %xmm1 + comuless 0x100000(%r15), %xmm2, %xmm1 + comfalsess 0x100000(%r15), %xmm2, %xmm1 + comuness 0x100000(%r15), %xmm2, %xmm1 + comunltss 0x100000(%r15), %xmm2, %xmm1 + comunless 0x100000(%r15), %xmm2, %xmm1 + comtruess 0x100000(%r15), %xmm2, %xmm1 + comsd $0x4, %xmm3, %xmm2, %xmm1 + comsd $0x4, 0x100000(%r15), %xmm2, %xmm1 + comeqsd %xmm3, %xmm2, %xmm1 + comltsd %xmm3, %xmm2, %xmm1 + comlesd %xmm3, %xmm2, %xmm1 + comunordsd %xmm3, %xmm2, %xmm1 + comnesd %xmm3, %xmm2, %xmm1 + comnltsd %xmm3, %xmm2, %xmm1 + comnlesd %xmm3, %xmm2, %xmm1 + comordsd %xmm3, %xmm2, %xmm1 + comueqsd %xmm3, %xmm2, %xmm1 + comultsd %xmm3, %xmm2, %xmm1 + comulesd %xmm3, %xmm2, %xmm1 + comfalsesd %xmm3, %xmm2, %xmm1 + comunesd %xmm3, %xmm2, %xmm1 + comunltsd %xmm3, %xmm2, %xmm1 + comunlesd %xmm3, %xmm2, %xmm1 + comtruesd %xmm3, %xmm2, %xmm1 + comeqsd 0x100000(%r15), %xmm2, %xmm1 + comltsd 0x100000(%r15), %xmm2, %xmm1 + comlesd 0x100000(%r15), %xmm2, %xmm1 + comunordsd 0x100000(%r15), %xmm2, %xmm1 + comnesd 0x100000(%r15), %xmm2, %xmm1 + comnltsd 0x100000(%r15), %xmm2, %xmm1 + comnlesd 0x100000(%r15), %xmm2, %xmm1 + comordsd 0x100000(%r15), %xmm2, %xmm1 + comueqsd 0x100000(%r15), %xmm2, %xmm1 + comultsd 0x100000(%r15), %xmm2, %xmm1 + comulesd 0x100000(%r15), %xmm2, %xmm1 + comfalsesd 0x100000(%r15), %xmm2, %xmm1 + comunesd 0x100000(%r15), %xmm2, %xmm1 + comunltsd 0x100000(%r15), %xmm2, %xmm1 + comunlesd 0x100000(%r15), %xmm2, %xmm1 + comtruesd 0x100000(%r15), %xmm2, %xmm1 + comps $0x4, %xmm3, %xmm2, %xmm1 + comps $0x4, 0x100000(%r15), %xmm2, %xmm1 + comeqps %xmm3, %xmm2, %xmm1 + comltps %xmm3, %xmm2, %xmm1 + comleps %xmm3, %xmm2, %xmm1 + comunordps %xmm3, %xmm2, %xmm1 + comneps %xmm3, %xmm2, %xmm1 + comnltps %xmm3, %xmm2, %xmm1 + comnleps %xmm3, %xmm2, %xmm1 + comordps %xmm3, %xmm2, %xmm1 + comueqps %xmm3, %xmm2, %xmm1 + comultps %xmm3, %xmm2, %xmm1 + comuleps %xmm3, %xmm2, %xmm1 + comfalseps %xmm3, %xmm2, %xmm1 + comuneps %xmm3, %xmm2, %xmm1 + comunltps %xmm3, %xmm2, %xmm1 + comunleps %xmm3, %xmm2, %xmm1 + comtrueps %xmm3, %xmm2, %xmm1 + comeqps 0x100000(%r15), %xmm2, %xmm1 + comltps 0x100000(%r15), %xmm2, %xmm1 + comleps 0x100000(%r15), %xmm2, %xmm1 + comunordps 0x100000(%r15), %xmm2, %xmm1 + comneps 0x100000(%r15), %xmm2, %xmm1 + comnltps 0x100000(%r15), %xmm2, %xmm1 + comnleps 0x100000(%r15), %xmm2, %xmm1 + comordps 0x100000(%r15), %xmm2, %xmm1 + comueqps 0x100000(%r15), %xmm2, %xmm1 + comultps 0x100000(%r15), %xmm2, %xmm1 + comuleps 0x100000(%r15), %xmm2, %xmm1 + comfalseps 0x100000(%r15), %xmm2, %xmm1 + comuneps 0x100000(%r15), %xmm2, %xmm1 + comunltps 0x100000(%r15), %xmm2, %xmm1 + comunleps 0x100000(%r15), %xmm2, %xmm1 + comtrueps 0x100000(%r15), %xmm2, %xmm1 + compd $0x4, %xmm3, %xmm2, %xmm1 + compd $0x4, 0x100000(%r15), %xmm2, %xmm1 + comeqpd %xmm3, %xmm2, %xmm1 + comltpd %xmm3, %xmm2, %xmm1 + comlepd %xmm3, %xmm2, %xmm1 + comunordpd %xmm3, %xmm2, %xmm1 + comnepd %xmm3, %xmm2, %xmm1 + comnltpd %xmm3, %xmm2, %xmm1 + comnlepd %xmm3, %xmm2, %xmm1 + comordpd %xmm3, %xmm2, %xmm1 + comueqpd %xmm3, %xmm2, %xmm1 + comultpd %xmm3, %xmm2, %xmm1 + comulepd %xmm3, %xmm2, %xmm1 + comfalsepd %xmm3, %xmm2, %xmm1 + comunepd %xmm3, %xmm2, %xmm1 + comunltpd %xmm3, %xmm2, %xmm1 + comunlepd %xmm3, %xmm2, %xmm1 + comtruepd %xmm3, %xmm2, %xmm1 + comeqpd 0x100000(%r15), %xmm2, %xmm1 + comltpd 0x100000(%r15), %xmm2, %xmm1 + comlepd 0x100000(%r15), %xmm2, %xmm1 + comunordpd 0x100000(%r15), %xmm2, %xmm1 + comnepd 0x100000(%r15), %xmm2, %xmm1 + comnltpd 0x100000(%r15), %xmm2, %xmm1 + comnlepd 0x100000(%r15), %xmm2, %xmm1 + comordpd 0x100000(%r15), %xmm2, %xmm1 + comueqpd 0x100000(%r15), %xmm2, %xmm1 + comultpd 0x100000(%r15), %xmm2, %xmm1 + comulepd 0x100000(%r15), %xmm2, %xmm1 + comfalsepd 0x100000(%r15), %xmm2, %xmm1 + comunepd 0x100000(%r15), %xmm2, %xmm1 + comunltpd 0x100000(%r15), %xmm2, %xmm1 + comunlepd 0x100000(%r15), %xmm2, %xmm1 + comtruepd 0x100000(%r15), %xmm2, %xmm1 + + pcomb $0x4, %xmm3, %xmm2, %xmm1 + pcomb $0x4, 0x100000(%r15), %xmm2, %xmm1 + pcomltb %xmm3, %xmm2, %xmm1 + pcomleb %xmm3, %xmm2, %xmm1 + pcomgtb %xmm3, %xmm2, %xmm1 + pcomgeb %xmm3, %xmm2, %xmm1 + pcomeqb %xmm3, %xmm2, %xmm1 + pcomneqb %xmm3, %xmm2, %xmm1 + pcomltb 0x100000(%r15), %xmm2, %xmm1 + pcomleb 0x100000(%r15), %xmm2, %xmm1 + pcomgtb 0x100000(%r15), %xmm2, %xmm1 + pcomgeb 0x100000(%r15), %xmm2, %xmm1 + pcomeqb 0x100000(%r15), %xmm2, %xmm1 + pcomneqb 0x100000(%r15), %xmm2, %xmm1 + pcomw $0x4, %xmm3, %xmm2, %xmm1 + pcomw $0x4, 0x100000(%r15), %xmm2, %xmm1 + pcomltw %xmm3, %xmm2, %xmm1 + pcomlew %xmm3, %xmm2, %xmm1 + pcomgtw %xmm3, %xmm2, %xmm1 + pcomgew %xmm3, %xmm2, %xmm1 + pcomeqw %xmm3, %xmm2, %xmm1 + pcomneqw %xmm3, %xmm2, %xmm1 + pcomltw 0x100000(%r15), %xmm2, %xmm1 + pcomlew 0x100000(%r15), %xmm2, %xmm1 + pcomgtw 0x100000(%r15), %xmm2, %xmm1 + pcomgew 0x100000(%r15), %xmm2, %xmm1 + pcomeqw 0x100000(%r15), %xmm2, %xmm1 + pcomneqw 0x100000(%r15), %xmm2, %xmm1 + pcomd $0x4, %xmm3, %xmm2, %xmm1 + pcomd $0x4, 0x100000(%r15), %xmm2, %xmm1 + pcomltd %xmm3, %xmm2, %xmm1 + pcomled %xmm3, %xmm2, %xmm1 + pcomgtd %xmm3, %xmm2, %xmm1 + pcomged %xmm3, %xmm2, %xmm1 + pcomeqd %xmm3, %xmm2, %xmm1 + pcomneqd %xmm3, %xmm2, %xmm1 + pcomltd 0x100000(%r15), %xmm2, %xmm1 + pcomled 0x100000(%r15), %xmm2, %xmm1 + pcomgtd 0x100000(%r15), %xmm2, %xmm1 + pcomged 0x100000(%r15), %xmm2, %xmm1 + pcomeqd 0x100000(%r15), %xmm2, %xmm1 + pcomneqd 0x100000(%r15), %xmm2, %xmm1 + pcomq $0x4, %xmm3, %xmm2, %xmm1 + pcomq $0x4, 0x100000(%r15), %xmm2, %xmm1 + pcomltq %xmm3, %xmm2, %xmm1 + pcomleq %xmm3, %xmm2, %xmm1 + pcomgtq %xmm3, %xmm2, %xmm1 + pcomgeq %xmm3, %xmm2, %xmm1 + pcomeqq %xmm3, %xmm2, %xmm1 + pcomneqq %xmm3, %xmm2, %xmm1 + pcomltq 0x100000(%r15), %xmm2, %xmm1 + pcomleq 0x100000(%r15), %xmm2, %xmm1 + pcomgtq 0x100000(%r15), %xmm2, %xmm1 + pcomgeq 0x100000(%r15), %xmm2, %xmm1 + pcomeqq 0x100000(%r15), %xmm2, %xmm1 + pcomneqq 0x100000(%r15), %xmm2, %xmm1 + + pcomub $0x4, %xmm3, %xmm2, %xmm1 + pcomub $0x4, 0x100000(%r15), %xmm2, %xmm1 + pcomltub %xmm3, %xmm2, %xmm1 + pcomleub %xmm3, %xmm2, %xmm1 + pcomgtub %xmm3, %xmm2, %xmm1 + pcomgeub %xmm3, %xmm2, %xmm1 + pcomequb %xmm3, %xmm2, %xmm1 + pcomnequb %xmm3, %xmm2, %xmm1 + pcomltub 0x100000(%r15), %xmm2, %xmm1 + pcomleub 0x100000(%r15), %xmm2, %xmm1 + pcomgtub 0x100000(%r15), %xmm2, %xmm1 + pcomgeub 0x100000(%r15), %xmm2, %xmm1 + pcomequb 0x100000(%r15), %xmm2, %xmm1 + pcomnequb 0x100000(%r15), %xmm2, %xmm1 + pcomuw $0x4, %xmm3, %xmm2, %xmm1 + pcomuw $0x4, 0x100000(%r15), %xmm2, %xmm1 + pcomltuw %xmm3, %xmm2, %xmm1 + pcomleuw %xmm3, %xmm2, %xmm1 + pcomgtuw %xmm3, %xmm2, %xmm1 + pcomgeuw %xmm3, %xmm2, %xmm1 + pcomequw %xmm3, %xmm2, %xmm1 + pcomnequw %xmm3, %xmm2, %xmm1 + pcomltuw 0x100000(%r15), %xmm2, %xmm1 + pcomleuw 0x100000(%r15), %xmm2, %xmm1 + pcomgtuw 0x100000(%r15), %xmm2, %xmm1 + pcomgeuw 0x100000(%r15), %xmm2, %xmm1 + pcomequw 0x100000(%r15), %xmm2, %xmm1 + pcomnequw 0x100000(%r15), %xmm2, %xmm1 + pcomud $0x4, %xmm3, %xmm2, %xmm1 + pcomud $0x4, 0x100000(%r15), %xmm2, %xmm1 + pcomltud %xmm3, %xmm2, %xmm1 + pcomleud %xmm3, %xmm2, %xmm1 + pcomgtud %xmm3, %xmm2, %xmm1 + pcomgeud %xmm3, %xmm2, %xmm1 + pcomequd %xmm3, %xmm2, %xmm1 + pcomnequd %xmm3, %xmm2, %xmm1 + pcomltud 0x100000(%r15), %xmm2, %xmm1 + pcomleud 0x100000(%r15), %xmm2, %xmm1 + pcomgtud 0x100000(%r15), %xmm2, %xmm1 + pcomgeud 0x100000(%r15), %xmm2, %xmm1 + pcomequd 0x100000(%r15), %xmm2, %xmm1 + pcomnequd 0x100000(%r15), %xmm2, %xmm1 + pcomuq $0x4, %xmm3, %xmm2, %xmm1 + pcomuq $0x4, 0x100000(%r15), %xmm2, %xmm1 + pcomltuq %xmm3, %xmm2, %xmm1 + pcomleuq %xmm3, %xmm2, %xmm1 + pcomgtuq %xmm3, %xmm2, %xmm1 + pcomgeuq %xmm3, %xmm2, %xmm1 + pcomequq %xmm3, %xmm2, %xmm1 + pcomnequq %xmm3, %xmm2, %xmm1 + pcomltuq 0x100000(%r15), %xmm2, %xmm1 + pcomleuq 0x100000(%r15), %xmm2, %xmm1 + pcomgtuq 0x100000(%r15), %xmm2, %xmm1 + pcomgeuq 0x100000(%r15), %xmm2, %xmm1 + pcomequq 0x100000(%r15), %xmm2, %xmm1 + pcomnequq 0x100000(%r15), %xmm2, %xmm1 + + frczss %xmm2, %xmm1 + frczss 0x4(%rdx), %xmm1 + frczsd %xmm2, %xmm1 + frczsd 0x4(%rdx), %xmm1 + frczps %xmm2, %xmm1 + frczps 0x4(%rdx), %xmm1 + frczpd %xmm2, %xmm1 + frczpd 0x4(%rdx), %xmm1 + + frczss %xmm12, %xmm11 + frczss 0x100000(%r15), %xmm11 + frczsd %xmm12, %xmm11 + frczsd 0x100000(%r15), %xmm11 + frczps %xmm12, %xmm11 + frczps 0x100000(%r15), %xmm11 + frczpd %xmm12, %xmm11 + frczpd 0x100000(%r15), %xmm11 + + frczss %xmm12, %xmm1 + frczss 0x4(%rdx), %xmm1 + frczsd %xmm12, %xmm1 + frczsd 0x4(%rdx), %xmm1 + frczps %xmm12, %xmm1 + frczps 0x4(%rdx), %xmm1 + frczpd %xmm12, %xmm1 + frczpd 0x4(%rdx), %xmm1 + + frczss %xmm2, %xmm11 + frczss 0x4(%rdx), %xmm11 + frczsd %xmm2, %xmm11 + frczsd 0x4(%rdx), %xmm11 + frczps %xmm2, %xmm11 + frczps 0x4(%rdx), %xmm11 + frczpd %xmm2, %xmm11 + frczpd 0x4(%rdx), %xmm11 + + frczss %xmm2, %xmm1 + frczss 0x4(%rdx), %xmm1 + frczsd %xmm2, %xmm1 + frczsd 0x4(%rdx), %xmm1 + frczps %xmm2, %xmm1 + frczps 0x4(%rdx), %xmm1 + frczpd %xmm2, %xmm1 + frczpd 0x4(%rdx), %xmm1 + + frczss %xmm2, %xmm1 + frczss 0x100000(%r15), %xmm1 + frczsd %xmm2, %xmm1 + frczsd 0x100000(%r15), %xmm1 + frczps %xmm2, %xmm1 + frczps 0x100000(%r15), %xmm1 + frczpd %xmm2, %xmm1 + frczpd 0x100000(%r15), %xmm1 + + cvtph2ps %xmm2, %xmm1 + cvtph2ps 0x4(%rdx), %xmm1 + cvtps2ph %xmm2, %xmm1 + cvtps2ph %xmm1, 0x4(%rdx) + + cvtph2ps %xmm12, %xmm11 + cvtph2ps 0x100000(%r15), %xmm11 + cvtps2ph %xmm12, %xmm11 + cvtps2ph %xmm11, 0x100000(%r15) + + cvtph2ps %xmm12, %xmm1 + cvtph2ps 0x4(%rdx), %xmm1 + cvtps2ph %xmm12, %xmm1 + cvtps2ph %xmm1, 0x4(%rdx) + + cvtph2ps %xmm2, %xmm11 + cvtph2ps 0x4(%rdx), %xmm11 + cvtps2ph %xmm2, %xmm11 + cvtps2ph %xmm11, 0x4(%rdx) + + cvtph2ps %xmm2, %xmm1 + cvtph2ps 0x4(%rdx), %xmm1 + cvtps2ph %xmm2, %xmm1 + cvtps2ph %xmm1, 0x4(%rdx) + + cvtph2ps %xmm2, %xmm1 + cvtph2ps 0x100000(%r15), %xmm1 + cvtps2ph %xmm2, %xmm1 + cvtps2ph %xmm1, 0x100000(%r15) + + ret + .size foo, .-foo *** gas/testsuite/gas/i386/x86-64-sse5.d.~1~ 2007-08-31 11:40:01.024045000 -0400 --- gas/testsuite/gas/i386/x86-64-sse5.d 2007-08-17 14:52:04.196195000 -0400 *************** *** 0 **** --- 1,2841 ---- + #objdump: -dw + #name: x86-64 x86-64-sse5 + + .*: +file format .* + + Disassembly of section .text: + + 0000000000000000 : + [ ]+0:[ ]+0f 24 02 d3 10[ ]+fmaddss %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+5:[ ]+0f 24 02 52 10 04[ ]+fmaddss 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+b:[ ]+0f 24 02 52 18 04[ ]+fmaddss %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+11:[ ]+0f 24 06 d3 10[ ]+fmaddss %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+16:[ ]+0f 24 06 52 10 04[ ]+fmaddss %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1c:[ ]+0f 24 06 52 18 04[ ]+fmaddss %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+22:[ ]+0f 24 03 d3 10[ ]+fmaddsd %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+27:[ ]+0f 24 03 52 10 04[ ]+fmaddsd 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+2d:[ ]+0f 24 03 52 18 04[ ]+fmaddsd %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+33:[ ]+0f 24 07 d3 10[ ]+fmaddsd %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+38:[ ]+0f 24 07 52 10 04[ ]+fmaddsd %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3e:[ ]+0f 24 07 52 18 04[ ]+fmaddsd %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+44:[ ]+0f 24 00 d3 10[ ]+fmaddps %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+49:[ ]+0f 24 00 52 10 04[ ]+fmaddps 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+4f:[ ]+0f 24 00 52 18 04[ ]+fmaddps %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+55:[ ]+0f 24 04 d3 10[ ]+fmaddps %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+5a:[ ]+0f 24 04 52 10 04[ ]+fmaddps %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+60:[ ]+0f 24 04 52 18 04[ ]+fmaddps %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+66:[ ]+0f 24 01 d3 10[ ]+fmaddpd %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+6b:[ ]+0f 24 01 52 10 04[ ]+fmaddpd 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+71:[ ]+0f 24 01 52 18 04[ ]+fmaddpd %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+77:[ ]+0f 24 05 d3 10[ ]+fmaddpd %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+7c:[ ]+0f 24 05 52 10 04[ ]+fmaddpd %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+82:[ ]+0f 24 05 52 18 04[ ]+fmaddpd %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+88:[ ]+0f 24 0a d3 10[ ]+fmsubss %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+8d:[ ]+0f 24 0a 52 10 04[ ]+fmsubss 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+93:[ ]+0f 24 0a 52 18 04[ ]+fmsubss %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+99:[ ]+0f 24 0e d3 10[ ]+fmsubss %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+9e:[ ]+0f 24 0e 52 10 04[ ]+fmsubss %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+a4:[ ]+0f 24 0e 52 18 04[ ]+fmsubss %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+aa:[ ]+0f 24 0b d3 10[ ]+fmsubsd %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+af:[ ]+0f 24 0b 52 10 04[ ]+fmsubsd 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+b5:[ ]+0f 24 0b 52 18 04[ ]+fmsubsd %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+bb:[ ]+0f 24 0f d3 10[ ]+fmsubsd %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+c0:[ ]+0f 24 0f 52 10 04[ ]+fmsubsd %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+c6:[ ]+0f 24 0f 52 18 04[ ]+fmsubsd %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+cc:[ ]+0f 24 08 d3 10[ ]+fmsubps %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+d1:[ ]+0f 24 08 52 10 04[ ]+fmsubps 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+d7:[ ]+0f 24 08 52 18 04[ ]+fmsubps %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+dd:[ ]+0f 24 0c d3 10[ ]+fmsubps %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+e2:[ ]+0f 24 0c 52 10 04[ ]+fmsubps %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+e8:[ ]+0f 24 0c 52 18 04[ ]+fmsubps %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+ee:[ ]+0f 24 09 d3 10[ ]+fmsubpd %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+f3:[ ]+0f 24 09 52 10 04[ ]+fmsubpd 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+f9:[ ]+0f 24 09 52 18 04[ ]+fmsubpd %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+ff:[ ]+0f 24 0d d3 10[ ]+fmsubpd %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+104:[ ]+0f 24 0d 52 10 04[ ]+fmsubpd %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+10a:[ ]+0f 24 0d 52 18 04[ ]+fmsubpd %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+110:[ ]+0f 24 12 d3 10[ ]+fnmaddss %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+115:[ ]+0f 24 12 52 10 04[ ]+fnmaddss 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+11b:[ ]+0f 24 12 52 18 04[ ]+fnmaddss %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+121:[ ]+0f 24 16 d3 10[ ]+fnmaddss %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+126:[ ]+0f 24 16 52 10 04[ ]+fnmaddss %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+12c:[ ]+0f 24 16 52 18 04[ ]+fnmaddss %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+132:[ ]+0f 24 13 d3 10[ ]+fnmaddsd %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+137:[ ]+0f 24 13 52 10 04[ ]+fnmaddsd 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+13d:[ ]+0f 24 13 52 18 04[ ]+fnmaddsd %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+143:[ ]+0f 24 17 d3 10[ ]+fnmaddsd %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+148:[ ]+0f 24 17 52 10 04[ ]+fnmaddsd %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+14e:[ ]+0f 24 17 52 18 04[ ]+fnmaddsd %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+154:[ ]+0f 24 10 d3 10[ ]+fnmaddps %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+159:[ ]+0f 24 10 52 10 04[ ]+fnmaddps 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+15f:[ ]+0f 24 10 52 18 04[ ]+fnmaddps %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+165:[ ]+0f 24 14 d3 10[ ]+fnmaddps %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+16a:[ ]+0f 24 14 52 10 04[ ]+fnmaddps %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+170:[ ]+0f 24 14 52 18 04[ ]+fnmaddps %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+176:[ ]+0f 24 11 d3 10[ ]+fnmaddpd %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+17b:[ ]+0f 24 11 52 10 04[ ]+fnmaddpd 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+181:[ ]+0f 24 11 52 18 04[ ]+fnmaddpd %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+187:[ ]+0f 24 15 d3 10[ ]+fnmaddpd %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+18c:[ ]+0f 24 15 52 10 04[ ]+fnmaddpd %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+192:[ ]+0f 24 15 52 18 04[ ]+fnmaddpd %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+198:[ ]+0f 24 1a d3 10[ ]+fnmsubss %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+19d:[ ]+0f 24 1a 52 10 04[ ]+fnmsubss 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+1a3:[ ]+0f 24 1a 52 18 04[ ]+fnmsubss %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+1a9:[ ]+0f 24 1e d3 10[ ]+fnmsubss %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+1ae:[ ]+0f 24 1e 52 10 04[ ]+fnmsubss %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1b4:[ ]+0f 24 1e 52 18 04[ ]+fnmsubss %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+1ba:[ ]+0f 24 1b d3 10[ ]+fnmsubsd %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+1bf:[ ]+0f 24 1b 52 10 04[ ]+fnmsubsd 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+1c5:[ ]+0f 24 1b 52 18 04[ ]+fnmsubsd %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+1cb:[ ]+0f 24 1f d3 10[ ]+fnmsubsd %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+1d0:[ ]+0f 24 1f 52 10 04[ ]+fnmsubsd %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1d6:[ ]+0f 24 1f 52 18 04[ ]+fnmsubsd %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+1dc:[ ]+0f 24 18 d3 10[ ]+fnmsubps %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+1e1:[ ]+0f 24 18 52 10 04[ ]+fnmsubps 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+1e7:[ ]+0f 24 18 52 18 04[ ]+fnmsubps %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+1ed:[ ]+0f 24 1c d3 10[ ]+fnmsubps %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+1f2:[ ]+0f 24 1c 52 10 04[ ]+fnmsubps %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1f8:[ ]+0f 24 1c 52 18 04[ ]+fnmsubps %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+1fe:[ ]+0f 24 19 d3 10[ ]+fnmsubpd %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+203:[ ]+0f 24 19 52 10 04[ ]+fnmsubpd 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+209:[ ]+0f 24 19 52 18 04[ ]+fnmsubpd %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+20f:[ ]+0f 24 1d d3 10[ ]+fnmsubpd %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+214:[ ]+0f 24 1d 52 10 04[ ]+fnmsubpd %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+21a:[ ]+0f 24 1d 52 18 04[ ]+fnmsubpd %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+220:[ ]+0f 24 02 e5 b5[ ]+fmaddss %xmm13,%xmm12,%xmm11,%xmm11 + [ ]+225:[ ]+0f 24 02 a7 b5 00 00 10 00[ ]+fmaddss 0x100000\(%r15\),%xmm12,%xmm11,%xmm11 + [ ]+22e:[ ]+0f 24 02 a7 bd 00 00 10 00[ ]+fmaddss %xmm12,0x100000\(%r15\),%xmm11,%xmm11 + [ ]+237:[ ]+0f 24 06 e5 b5[ ]+fmaddss %xmm11,%xmm13,%xmm12,%xmm11 + [ ]+23c:[ ]+0f 24 06 a7 b5 00 00 10 00[ ]+fmaddss %xmm11,0x100000\(%r15\),%xmm12,%xmm11 + [ ]+245:[ ]+0f 24 06 a7 bd 00 00 10 00[ ]+fmaddss %xmm11,%xmm12,0x100000\(%r15\),%xmm11 + [ ]+24e:[ ]+0f 24 03 e5 b5[ ]+fmaddsd %xmm13,%xmm12,%xmm11,%xmm11 + [ ]+253:[ ]+0f 24 03 a7 b5 00 00 10 00[ ]+fmaddsd 0x100000\(%r15\),%xmm12,%xmm11,%xmm11 + [ ]+25c:[ ]+0f 24 03 a7 bd 00 00 10 00[ ]+fmaddsd %xmm12,0x100000\(%r15\),%xmm11,%xmm11 + [ ]+265:[ ]+0f 24 07 e5 b5[ ]+fmaddsd %xmm11,%xmm13,%xmm12,%xmm11 + [ ]+26a:[ ]+0f 24 07 a7 b5 00 00 10 00[ ]+fmaddsd %xmm11,0x100000\(%r15\),%xmm12,%xmm11 + [ ]+273:[ ]+0f 24 07 a7 bd 00 00 10 00[ ]+fmaddsd %xmm11,%xmm12,0x100000\(%r15\),%xmm11 + [ ]+27c:[ ]+0f 24 00 e5 b5[ ]+fmaddps %xmm13,%xmm12,%xmm11,%xmm11 + [ ]+281:[ ]+0f 24 00 a7 b5 00 00 10 00[ ]+fmaddps 0x100000\(%r15\),%xmm12,%xmm11,%xmm11 + [ ]+28a:[ ]+0f 24 00 a7 bd 00 00 10 00[ ]+fmaddps %xmm12,0x100000\(%r15\),%xmm11,%xmm11 + [ ]+293:[ ]+0f 24 04 e5 b5[ ]+fmaddps %xmm11,%xmm13,%xmm12,%xmm11 + [ ]+298:[ ]+0f 24 04 a7 b5 00 00 10 00[ ]+fmaddps %xmm11,0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2a1:[ ]+0f 24 04 a7 bd 00 00 10 00[ ]+fmaddps %xmm11,%xmm12,0x100000\(%r15\),%xmm11 + [ ]+2aa:[ ]+0f 24 01 e5 b5[ ]+fmaddpd %xmm13,%xmm12,%xmm11,%xmm11 + [ ]+2af:[ ]+0f 24 01 a7 b5 00 00 10 00[ ]+fmaddpd 0x100000\(%r15\),%xmm12,%xmm11,%xmm11 + [ ]+2b8:[ ]+0f 24 01 a7 bd 00 00 10 00[ ]+fmaddpd %xmm12,0x100000\(%r15\),%xmm11,%xmm11 + [ ]+2c1:[ ]+0f 24 05 e5 b5[ ]+fmaddpd %xmm11,%xmm13,%xmm12,%xmm11 + [ ]+2c6:[ ]+0f 24 05 a7 b5 00 00 10 00[ ]+fmaddpd %xmm11,0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2cf:[ ]+0f 24 05 a7 bd 00 00 10 00[ ]+fmaddpd %xmm11,%xmm12,0x100000\(%r15\),%xmm11 + [ ]+2d8:[ ]+0f 24 0a e5 b5[ ]+fmsubss %xmm13,%xmm12,%xmm11,%xmm11 + [ ]+2dd:[ ]+0f 24 0a a7 b5 00 00 10 00[ ]+fmsubss 0x100000\(%r15\),%xmm12,%xmm11,%xmm11 + [ ]+2e6:[ ]+0f 24 0a a7 bd 00 00 10 00[ ]+fmsubss %xmm12,0x100000\(%r15\),%xmm11,%xmm11 + [ ]+2ef:[ ]+0f 24 0e e5 b5[ ]+fmsubss %xmm11,%xmm13,%xmm12,%xmm11 + [ ]+2f4:[ ]+0f 24 0e a7 b5 00 00 10 00[ ]+fmsubss %xmm11,0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2fd:[ ]+0f 24 0e a7 bd 00 00 10 00[ ]+fmsubss %xmm11,%xmm12,0x100000\(%r15\),%xmm11 + [ ]+306:[ ]+0f 24 0b e5 b5[ ]+fmsubsd %xmm13,%xmm12,%xmm11,%xmm11 + [ ]+30b:[ ]+0f 24 0b a7 b5 00 00 10 00[ ]+fmsubsd 0x100000\(%r15\),%xmm12,%xmm11,%xmm11 + [ ]+314:[ ]+0f 24 0b a7 bd 00 00 10 00[ ]+fmsubsd %xmm12,0x100000\(%r15\),%xmm11,%xmm11 + [ ]+31d:[ ]+0f 24 0f e5 b5[ ]+fmsubsd %xmm11,%xmm13,%xmm12,%xmm11 + [ ]+322:[ ]+0f 24 0f a7 b5 00 00 10 00[ ]+fmsubsd %xmm11,0x100000\(%r15\),%xmm12,%xmm11 + [ ]+32b:[ ]+0f 24 0f a7 bd 00 00 10 00[ ]+fmsubsd %xmm11,%xmm12,0x100000\(%r15\),%xmm11 + [ ]+334:[ ]+0f 24 08 e5 b5[ ]+fmsubps %xmm13,%xmm12,%xmm11,%xmm11 + [ ]+339:[ ]+0f 24 08 a7 b5 00 00 10 00[ ]+fmsubps 0x100000\(%r15\),%xmm12,%xmm11,%xmm11 + [ ]+342:[ ]+0f 24 08 a7 bd 00 00 10 00[ ]+fmsubps %xmm12,0x100000\(%r15\),%xmm11,%xmm11 + [ ]+34b:[ ]+0f 24 0c e5 b5[ ]+fmsubps %xmm11,%xmm13,%xmm12,%xmm11 + [ ]+350:[ ]+0f 24 0c a7 b5 00 00 10 00[ ]+fmsubps %xmm11,0x100000\(%r15\),%xmm12,%xmm11 + [ ]+359:[ ]+0f 24 0c a7 bd 00 00 10 00[ ]+fmsubps %xmm11,%xmm12,0x100000\(%r15\),%xmm11 + [ ]+362:[ ]+0f 24 09 e5 b5[ ]+fmsubpd %xmm13,%xmm12,%xmm11,%xmm11 + [ ]+367:[ ]+0f 24 09 a7 b5 00 00 10 00[ ]+fmsubpd 0x100000\(%r15\),%xmm12,%xmm11,%xmm11 + [ ]+370:[ ]+0f 24 09 a7 bd 00 00 10 00[ ]+fmsubpd %xmm12,0x100000\(%r15\),%xmm11,%xmm11 + [ ]+379:[ ]+0f 24 0d e5 b5[ ]+fmsubpd %xmm11,%xmm13,%xmm12,%xmm11 + [ ]+37e:[ ]+0f 24 0d a7 b5 00 00 10 00[ ]+fmsubpd %xmm11,0x100000\(%r15\),%xmm12,%xmm11 + [ ]+387:[ ]+0f 24 0d a7 bd 00 00 10 00[ ]+fmsubpd %xmm11,%xmm12,0x100000\(%r15\),%xmm11 + [ ]+390:[ ]+0f 24 12 e5 b5[ ]+fnmaddss %xmm13,%xmm12,%xmm11,%xmm11 + [ ]+395:[ ]+0f 24 12 a7 b5 00 00 10 00[ ]+fnmaddss 0x100000\(%r15\),%xmm12,%xmm11,%xmm11 + [ ]+39e:[ ]+0f 24 12 a7 bd 00 00 10 00[ ]+fnmaddss %xmm12,0x100000\(%r15\),%xmm11,%xmm11 + [ ]+3a7:[ ]+0f 24 16 e5 b5[ ]+fnmaddss %xmm11,%xmm13,%xmm12,%xmm11 + [ ]+3ac:[ ]+0f 24 16 a7 b5 00 00 10 00[ ]+fnmaddss %xmm11,0x100000\(%r15\),%xmm12,%xmm11 + [ ]+3b5:[ ]+0f 24 16 a7 bd 00 00 10 00[ ]+fnmaddss %xmm11,%xmm12,0x100000\(%r15\),%xmm11 + [ ]+3be:[ ]+0f 24 13 e5 b5[ ]+fnmaddsd %xmm13,%xmm12,%xmm11,%xmm11 + [ ]+3c3:[ ]+0f 24 13 a7 b5 00 00 10 00[ ]+fnmaddsd 0x100000\(%r15\),%xmm12,%xmm11,%xmm11 + [ ]+3cc:[ ]+0f 24 13 a7 bd 00 00 10 00[ ]+fnmaddsd %xmm12,0x100000\(%r15\),%xmm11,%xmm11 + [ ]+3d5:[ ]+0f 24 17 e5 b5[ ]+fnmaddsd %xmm11,%xmm13,%xmm12,%xmm11 + [ ]+3da:[ ]+0f 24 17 a7 b5 00 00 10 00[ ]+fnmaddsd %xmm11,0x100000\(%r15\),%xmm12,%xmm11 + [ ]+3e3:[ ]+0f 24 17 a7 bd 00 00 10 00[ ]+fnmaddsd %xmm11,%xmm12,0x100000\(%r15\),%xmm11 + [ ]+3ec:[ ]+0f 24 10 e5 b5[ ]+fnmaddps %xmm13,%xmm12,%xmm11,%xmm11 + [ ]+3f1:[ ]+0f 24 10 a7 b5 00 00 10 00[ ]+fnmaddps 0x100000\(%r15\),%xmm12,%xmm11,%xmm11 + [ ]+3fa:[ ]+0f 24 10 a7 bd 00 00 10 00[ ]+fnmaddps %xmm12,0x100000\(%r15\),%xmm11,%xmm11 + [ ]+403:[ ]+0f 24 14 e5 b5[ ]+fnmaddps %xmm11,%xmm13,%xmm12,%xmm11 + [ ]+408:[ ]+0f 24 14 a7 b5 00 00 10 00[ ]+fnmaddps %xmm11,0x100000\(%r15\),%xmm12,%xmm11 + [ ]+411:[ ]+0f 24 14 a7 bd 00 00 10 00[ ]+fnmaddps %xmm11,%xmm12,0x100000\(%r15\),%xmm11 + [ ]+41a:[ ]+0f 24 11 e5 b5[ ]+fnmaddpd %xmm13,%xmm12,%xmm11,%xmm11 + [ ]+41f:[ ]+0f 24 11 a7 b5 00 00 10 00[ ]+fnmaddpd 0x100000\(%r15\),%xmm12,%xmm11,%xmm11 + [ ]+428:[ ]+0f 24 11 a7 bd 00 00 10 00[ ]+fnmaddpd %xmm12,0x100000\(%r15\),%xmm11,%xmm11 + [ ]+431:[ ]+0f 24 15 e5 b5[ ]+fnmaddpd %xmm11,%xmm13,%xmm12,%xmm11 + [ ]+436:[ ]+0f 24 15 a7 b5 00 00 10 00[ ]+fnmaddpd %xmm11,0x100000\(%r15\),%xmm12,%xmm11 + [ ]+43f:[ ]+0f 24 15 a7 bd 00 00 10 00[ ]+fnmaddpd %xmm11,%xmm12,0x100000\(%r15\),%xmm11 + [ ]+448:[ ]+0f 24 1a e5 b5[ ]+fnmsubss %xmm13,%xmm12,%xmm11,%xmm11 + [ ]+44d:[ ]+0f 24 1a a7 b5 00 00 10 00[ ]+fnmsubss 0x100000\(%r15\),%xmm12,%xmm11,%xmm11 + [ ]+456:[ ]+0f 24 1a a7 bd 00 00 10 00[ ]+fnmsubss %xmm12,0x100000\(%r15\),%xmm11,%xmm11 + [ ]+45f:[ ]+0f 24 1e e5 b5[ ]+fnmsubss %xmm11,%xmm13,%xmm12,%xmm11 + [ ]+464:[ ]+0f 24 1e a7 b5 00 00 10 00[ ]+fnmsubss %xmm11,0x100000\(%r15\),%xmm12,%xmm11 + [ ]+46d:[ ]+0f 24 1e a7 bd 00 00 10 00[ ]+fnmsubss %xmm11,%xmm12,0x100000\(%r15\),%xmm11 + [ ]+476:[ ]+0f 24 1b e5 b5[ ]+fnmsubsd %xmm13,%xmm12,%xmm11,%xmm11 + [ ]+47b:[ ]+0f 24 1b a7 b5 00 00 10 00[ ]+fnmsubsd 0x100000\(%r15\),%xmm12,%xmm11,%xmm11 + [ ]+484:[ ]+0f 24 1b a7 bd 00 00 10 00[ ]+fnmsubsd %xmm12,0x100000\(%r15\),%xmm11,%xmm11 + [ ]+48d:[ ]+0f 24 1f e5 b5[ ]+fnmsubsd %xmm11,%xmm13,%xmm12,%xmm11 + [ ]+492:[ ]+0f 24 1f a7 b5 00 00 10 00[ ]+fnmsubsd %xmm11,0x100000\(%r15\),%xmm12,%xmm11 + [ ]+49b:[ ]+0f 24 1f a7 bd 00 00 10 00[ ]+fnmsubsd %xmm11,%xmm12,0x100000\(%r15\),%xmm11 + [ ]+4a4:[ ]+0f 24 18 e5 b5[ ]+fnmsubps %xmm13,%xmm12,%xmm11,%xmm11 + [ ]+4a9:[ ]+0f 24 18 a7 b5 00 00 10 00[ ]+fnmsubps 0x100000\(%r15\),%xmm12,%xmm11,%xmm11 + [ ]+4b2:[ ]+0f 24 18 a7 bd 00 00 10 00[ ]+fnmsubps %xmm12,0x100000\(%r15\),%xmm11,%xmm11 + [ ]+4bb:[ ]+0f 24 1c e5 b5[ ]+fnmsubps %xmm11,%xmm13,%xmm12,%xmm11 + [ ]+4c0:[ ]+0f 24 1c a7 b5 00 00 10 00[ ]+fnmsubps %xmm11,0x100000\(%r15\),%xmm12,%xmm11 + [ ]+4c9:[ ]+0f 24 1c a7 bd 00 00 10 00[ ]+fnmsubps %xmm11,%xmm12,0x100000\(%r15\),%xmm11 + [ ]+4d2:[ ]+0f 24 19 e5 b5[ ]+fnmsubpd %xmm13,%xmm12,%xmm11,%xmm11 + [ ]+4d7:[ ]+0f 24 19 a7 b5 00 00 10 00[ ]+fnmsubpd 0x100000\(%r15\),%xmm12,%xmm11,%xmm11 + [ ]+4e0:[ ]+0f 24 19 a7 bd 00 00 10 00[ ]+fnmsubpd %xmm12,0x100000\(%r15\),%xmm11,%xmm11 + [ ]+4e9:[ ]+0f 24 1d e5 b5[ ]+fnmsubpd %xmm11,%xmm13,%xmm12,%xmm11 + [ ]+4ee:[ ]+0f 24 1d a7 b5 00 00 10 00[ ]+fnmsubpd %xmm11,0x100000\(%r15\),%xmm12,%xmm11 + [ ]+4f7:[ ]+0f 24 1d a7 bd 00 00 10 00[ ]+fnmsubpd %xmm11,%xmm12,0x100000\(%r15\),%xmm11 + [ ]+500:[ ]+0f 24 02 e3 14[ ]+fmaddss %xmm3,%xmm12,%xmm1,%xmm1 + [ ]+505:[ ]+0f 24 02 62 14 04[ ]+fmaddss 0x4\(%rdx\),%xmm12,%xmm1,%xmm1 + [ ]+50b:[ ]+0f 24 02 62 1c 04[ ]+fmaddss %xmm12,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+511:[ ]+0f 24 06 e3 14[ ]+fmaddss %xmm1,%xmm3,%xmm12,%xmm1 + [ ]+516:[ ]+0f 24 06 62 14 04[ ]+fmaddss %xmm1,0x4\(%rdx\),%xmm12,%xmm1 + [ ]+51c:[ ]+0f 24 06 62 1c 04[ ]+fmaddss %xmm1,%xmm12,0x4\(%rdx\),%xmm1 + [ ]+522:[ ]+0f 24 03 e3 14[ ]+fmaddsd %xmm3,%xmm12,%xmm1,%xmm1 + [ ]+527:[ ]+0f 24 03 62 14 04[ ]+fmaddsd 0x4\(%rdx\),%xmm12,%xmm1,%xmm1 + [ ]+52d:[ ]+0f 24 03 62 1c 04[ ]+fmaddsd %xmm12,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+533:[ ]+0f 24 07 e3 14[ ]+fmaddsd %xmm1,%xmm3,%xmm12,%xmm1 + [ ]+538:[ ]+0f 24 07 62 14 04[ ]+fmaddsd %xmm1,0x4\(%rdx\),%xmm12,%xmm1 + [ ]+53e:[ ]+0f 24 07 62 1c 04[ ]+fmaddsd %xmm1,%xmm12,0x4\(%rdx\),%xmm1 + [ ]+544:[ ]+0f 24 00 e3 14[ ]+fmaddps %xmm3,%xmm12,%xmm1,%xmm1 + [ ]+549:[ ]+0f 24 00 62 14 04[ ]+fmaddps 0x4\(%rdx\),%xmm12,%xmm1,%xmm1 + [ ]+54f:[ ]+0f 24 00 62 1c 04[ ]+fmaddps %xmm12,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+555:[ ]+0f 24 04 e3 14[ ]+fmaddps %xmm1,%xmm3,%xmm12,%xmm1 + [ ]+55a:[ ]+0f 24 04 62 14 04[ ]+fmaddps %xmm1,0x4\(%rdx\),%xmm12,%xmm1 + [ ]+560:[ ]+0f 24 04 62 1c 04[ ]+fmaddps %xmm1,%xmm12,0x4\(%rdx\),%xmm1 + [ ]+566:[ ]+0f 24 01 e3 14[ ]+fmaddpd %xmm3,%xmm12,%xmm1,%xmm1 + [ ]+56b:[ ]+0f 24 01 62 14 04[ ]+fmaddpd 0x4\(%rdx\),%xmm12,%xmm1,%xmm1 + [ ]+571:[ ]+0f 24 01 62 1c 04[ ]+fmaddpd %xmm12,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+577:[ ]+0f 24 05 e3 14[ ]+fmaddpd %xmm1,%xmm3,%xmm12,%xmm1 + [ ]+57c:[ ]+0f 24 05 62 14 04[ ]+fmaddpd %xmm1,0x4\(%rdx\),%xmm12,%xmm1 + [ ]+582:[ ]+0f 24 05 62 1c 04[ ]+fmaddpd %xmm1,%xmm12,0x4\(%rdx\),%xmm1 + [ ]+588:[ ]+0f 24 0a e3 14[ ]+fmsubss %xmm3,%xmm12,%xmm1,%xmm1 + [ ]+58d:[ ]+0f 24 0a 62 14 04[ ]+fmsubss 0x4\(%rdx\),%xmm12,%xmm1,%xmm1 + [ ]+593:[ ]+0f 24 0a 62 1c 04[ ]+fmsubss %xmm12,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+599:[ ]+0f 24 0e e3 14[ ]+fmsubss %xmm1,%xmm3,%xmm12,%xmm1 + [ ]+59e:[ ]+0f 24 0e 62 14 04[ ]+fmsubss %xmm1,0x4\(%rdx\),%xmm12,%xmm1 + [ ]+5a4:[ ]+0f 24 0e 62 1c 04[ ]+fmsubss %xmm1,%xmm12,0x4\(%rdx\),%xmm1 + [ ]+5aa:[ ]+0f 24 0b e3 14[ ]+fmsubsd %xmm3,%xmm12,%xmm1,%xmm1 + [ ]+5af:[ ]+0f 24 0b 62 14 04[ ]+fmsubsd 0x4\(%rdx\),%xmm12,%xmm1,%xmm1 + [ ]+5b5:[ ]+0f 24 0b 62 1c 04[ ]+fmsubsd %xmm12,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+5bb:[ ]+0f 24 0f e3 14[ ]+fmsubsd %xmm1,%xmm3,%xmm12,%xmm1 + [ ]+5c0:[ ]+0f 24 0f 62 14 04[ ]+fmsubsd %xmm1,0x4\(%rdx\),%xmm12,%xmm1 + [ ]+5c6:[ ]+0f 24 0f 62 1c 04[ ]+fmsubsd %xmm1,%xmm12,0x4\(%rdx\),%xmm1 + [ ]+5cc:[ ]+0f 24 08 e3 14[ ]+fmsubps %xmm3,%xmm12,%xmm1,%xmm1 + [ ]+5d1:[ ]+0f 24 08 62 14 04[ ]+fmsubps 0x4\(%rdx\),%xmm12,%xmm1,%xmm1 + [ ]+5d7:[ ]+0f 24 08 62 1c 04[ ]+fmsubps %xmm12,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+5dd:[ ]+0f 24 0c e3 14[ ]+fmsubps %xmm1,%xmm3,%xmm12,%xmm1 + [ ]+5e2:[ ]+0f 24 0c 62 14 04[ ]+fmsubps %xmm1,0x4\(%rdx\),%xmm12,%xmm1 + [ ]+5e8:[ ]+0f 24 0c 62 1c 04[ ]+fmsubps %xmm1,%xmm12,0x4\(%rdx\),%xmm1 + [ ]+5ee:[ ]+0f 24 09 e3 14[ ]+fmsubpd %xmm3,%xmm12,%xmm1,%xmm1 + [ ]+5f3:[ ]+0f 24 09 62 14 04[ ]+fmsubpd 0x4\(%rdx\),%xmm12,%xmm1,%xmm1 + [ ]+5f9:[ ]+0f 24 09 62 1c 04[ ]+fmsubpd %xmm12,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+5ff:[ ]+0f 24 0d e3 14[ ]+fmsubpd %xmm1,%xmm3,%xmm12,%xmm1 + [ ]+604:[ ]+0f 24 0d 62 14 04[ ]+fmsubpd %xmm1,0x4\(%rdx\),%xmm12,%xmm1 + [ ]+60a:[ ]+0f 24 0d 62 1c 04[ ]+fmsubpd %xmm1,%xmm12,0x4\(%rdx\),%xmm1 + [ ]+610:[ ]+0f 24 12 e3 14[ ]+fnmaddss %xmm3,%xmm12,%xmm1,%xmm1 + [ ]+615:[ ]+0f 24 12 62 14 04[ ]+fnmaddss 0x4\(%rdx\),%xmm12,%xmm1,%xmm1 + [ ]+61b:[ ]+0f 24 12 62 1c 04[ ]+fnmaddss %xmm12,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+621:[ ]+0f 24 16 e3 14[ ]+fnmaddss %xmm1,%xmm3,%xmm12,%xmm1 + [ ]+626:[ ]+0f 24 16 62 14 04[ ]+fnmaddss %xmm1,0x4\(%rdx\),%xmm12,%xmm1 + [ ]+62c:[ ]+0f 24 16 62 1c 04[ ]+fnmaddss %xmm1,%xmm12,0x4\(%rdx\),%xmm1 + [ ]+632:[ ]+0f 24 13 e3 14[ ]+fnmaddsd %xmm3,%xmm12,%xmm1,%xmm1 + [ ]+637:[ ]+0f 24 13 62 14 04[ ]+fnmaddsd 0x4\(%rdx\),%xmm12,%xmm1,%xmm1 + [ ]+63d:[ ]+0f 24 13 62 1c 04[ ]+fnmaddsd %xmm12,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+643:[ ]+0f 24 17 e3 14[ ]+fnmaddsd %xmm1,%xmm3,%xmm12,%xmm1 + [ ]+648:[ ]+0f 24 17 62 14 04[ ]+fnmaddsd %xmm1,0x4\(%rdx\),%xmm12,%xmm1 + [ ]+64e:[ ]+0f 24 17 62 1c 04[ ]+fnmaddsd %xmm1,%xmm12,0x4\(%rdx\),%xmm1 + [ ]+654:[ ]+0f 24 10 e3 14[ ]+fnmaddps %xmm3,%xmm12,%xmm1,%xmm1 + [ ]+659:[ ]+0f 24 10 62 14 04[ ]+fnmaddps 0x4\(%rdx\),%xmm12,%xmm1,%xmm1 + [ ]+65f:[ ]+0f 24 10 62 1c 04[ ]+fnmaddps %xmm12,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+665:[ ]+0f 24 14 e3 14[ ]+fnmaddps %xmm1,%xmm3,%xmm12,%xmm1 + [ ]+66a:[ ]+0f 24 14 62 14 04[ ]+fnmaddps %xmm1,0x4\(%rdx\),%xmm12,%xmm1 + [ ]+670:[ ]+0f 24 14 62 1c 04[ ]+fnmaddps %xmm1,%xmm12,0x4\(%rdx\),%xmm1 + [ ]+676:[ ]+0f 24 11 e3 14[ ]+fnmaddpd %xmm3,%xmm12,%xmm1,%xmm1 + [ ]+67b:[ ]+0f 24 11 62 14 04[ ]+fnmaddpd 0x4\(%rdx\),%xmm12,%xmm1,%xmm1 + [ ]+681:[ ]+0f 24 11 62 1c 04[ ]+fnmaddpd %xmm12,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+687:[ ]+0f 24 15 e3 14[ ]+fnmaddpd %xmm1,%xmm3,%xmm12,%xmm1 + [ ]+68c:[ ]+0f 24 15 62 14 04[ ]+fnmaddpd %xmm1,0x4\(%rdx\),%xmm12,%xmm1 + [ ]+692:[ ]+0f 24 15 62 1c 04[ ]+fnmaddpd %xmm1,%xmm12,0x4\(%rdx\),%xmm1 + [ ]+698:[ ]+0f 24 1a e3 14[ ]+fnmsubss %xmm3,%xmm12,%xmm1,%xmm1 + [ ]+69d:[ ]+0f 24 1a 62 14 04[ ]+fnmsubss 0x4\(%rdx\),%xmm12,%xmm1,%xmm1 + [ ]+6a3:[ ]+0f 24 1a 62 1c 04[ ]+fnmsubss %xmm12,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+6a9:[ ]+0f 24 1e e3 14[ ]+fnmsubss %xmm1,%xmm3,%xmm12,%xmm1 + [ ]+6ae:[ ]+0f 24 1e 62 14 04[ ]+fnmsubss %xmm1,0x4\(%rdx\),%xmm12,%xmm1 + [ ]+6b4:[ ]+0f 24 1e 62 1c 04[ ]+fnmsubss %xmm1,%xmm12,0x4\(%rdx\),%xmm1 + [ ]+6ba:[ ]+0f 24 1b e3 14[ ]+fnmsubsd %xmm3,%xmm12,%xmm1,%xmm1 + [ ]+6bf:[ ]+0f 24 1b 62 14 04[ ]+fnmsubsd 0x4\(%rdx\),%xmm12,%xmm1,%xmm1 + [ ]+6c5:[ ]+0f 24 1b 62 1c 04[ ]+fnmsubsd %xmm12,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+6cb:[ ]+0f 24 1f e3 14[ ]+fnmsubsd %xmm1,%xmm3,%xmm12,%xmm1 + [ ]+6d0:[ ]+0f 24 1f 62 14 04[ ]+fnmsubsd %xmm1,0x4\(%rdx\),%xmm12,%xmm1 + [ ]+6d6:[ ]+0f 24 1f 62 1c 04[ ]+fnmsubsd %xmm1,%xmm12,0x4\(%rdx\),%xmm1 + [ ]+6dc:[ ]+0f 24 18 e3 14[ ]+fnmsubps %xmm3,%xmm12,%xmm1,%xmm1 + [ ]+6e1:[ ]+0f 24 18 62 14 04[ ]+fnmsubps 0x4\(%rdx\),%xmm12,%xmm1,%xmm1 + [ ]+6e7:[ ]+0f 24 18 62 1c 04[ ]+fnmsubps %xmm12,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+6ed:[ ]+0f 24 1c e3 14[ ]+fnmsubps %xmm1,%xmm3,%xmm12,%xmm1 + [ ]+6f2:[ ]+0f 24 1c 62 14 04[ ]+fnmsubps %xmm1,0x4\(%rdx\),%xmm12,%xmm1 + [ ]+6f8:[ ]+0f 24 1c 62 1c 04[ ]+fnmsubps %xmm1,%xmm12,0x4\(%rdx\),%xmm1 + [ ]+6fe:[ ]+0f 24 19 e3 14[ ]+fnmsubpd %xmm3,%xmm12,%xmm1,%xmm1 + [ ]+703:[ ]+0f 24 19 62 14 04[ ]+fnmsubpd 0x4\(%rdx\),%xmm12,%xmm1,%xmm1 + [ ]+709:[ ]+0f 24 19 62 1c 04[ ]+fnmsubpd %xmm12,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+70f:[ ]+0f 24 1d e3 14[ ]+fnmsubpd %xmm1,%xmm3,%xmm12,%xmm1 + [ ]+714:[ ]+0f 24 1d 62 14 04[ ]+fnmsubpd %xmm1,0x4\(%rdx\),%xmm12,%xmm1 + [ ]+71a:[ ]+0f 24 1d 62 1c 04[ ]+fnmsubpd %xmm1,%xmm12,0x4\(%rdx\),%xmm1 + [ ]+720:[ ]+0f 24 02 d3 b0[ ]+fmaddss %xmm3,%xmm2,%xmm11,%xmm11 + [ ]+725:[ ]+0f 24 02 52 b0 04[ ]+fmaddss 0x4\(%rdx\),%xmm2,%xmm11,%xmm11 + [ ]+72b:[ ]+0f 24 02 52 b8 04[ ]+fmaddss %xmm2,0x4\(%rdx\),%xmm11,%xmm11 + [ ]+731:[ ]+0f 24 06 d3 b0[ ]+fmaddss %xmm11,%xmm3,%xmm2,%xmm11 + [ ]+736:[ ]+0f 24 06 52 b0 04[ ]+fmaddss %xmm11,0x4\(%rdx\),%xmm2,%xmm11 + [ ]+73c:[ ]+0f 24 06 52 b8 04[ ]+fmaddss %xmm11,%xmm2,0x4\(%rdx\),%xmm11 + [ ]+742:[ ]+0f 24 03 d3 b0[ ]+fmaddsd %xmm3,%xmm2,%xmm11,%xmm11 + [ ]+747:[ ]+0f 24 03 52 b0 04[ ]+fmaddsd 0x4\(%rdx\),%xmm2,%xmm11,%xmm11 + [ ]+74d:[ ]+0f 24 03 52 b8 04[ ]+fmaddsd %xmm2,0x4\(%rdx\),%xmm11,%xmm11 + [ ]+753:[ ]+0f 24 07 d3 b0[ ]+fmaddsd %xmm11,%xmm3,%xmm2,%xmm11 + [ ]+758:[ ]+0f 24 07 52 b0 04[ ]+fmaddsd %xmm11,0x4\(%rdx\),%xmm2,%xmm11 + [ ]+75e:[ ]+0f 24 07 52 b8 04[ ]+fmaddsd %xmm11,%xmm2,0x4\(%rdx\),%xmm11 + [ ]+764:[ ]+0f 24 00 d3 b0[ ]+fmaddps %xmm3,%xmm2,%xmm11,%xmm11 + [ ]+769:[ ]+0f 24 00 52 b0 04[ ]+fmaddps 0x4\(%rdx\),%xmm2,%xmm11,%xmm11 + [ ]+76f:[ ]+0f 24 00 52 b8 04[ ]+fmaddps %xmm2,0x4\(%rdx\),%xmm11,%xmm11 + [ ]+775:[ ]+0f 24 04 d3 b0[ ]+fmaddps %xmm11,%xmm3,%xmm2,%xmm11 + [ ]+77a:[ ]+0f 24 04 52 b0 04[ ]+fmaddps %xmm11,0x4\(%rdx\),%xmm2,%xmm11 + [ ]+780:[ ]+0f 24 04 52 b8 04[ ]+fmaddps %xmm11,%xmm2,0x4\(%rdx\),%xmm11 + [ ]+786:[ ]+0f 24 01 d3 b0[ ]+fmaddpd %xmm3,%xmm2,%xmm11,%xmm11 + [ ]+78b:[ ]+0f 24 01 52 b0 04[ ]+fmaddpd 0x4\(%rdx\),%xmm2,%xmm11,%xmm11 + [ ]+791:[ ]+0f 24 01 52 b8 04[ ]+fmaddpd %xmm2,0x4\(%rdx\),%xmm11,%xmm11 + [ ]+797:[ ]+0f 24 05 d3 b0[ ]+fmaddpd %xmm11,%xmm3,%xmm2,%xmm11 + [ ]+79c:[ ]+0f 24 05 52 b0 04[ ]+fmaddpd %xmm11,0x4\(%rdx\),%xmm2,%xmm11 + [ ]+7a2:[ ]+0f 24 05 52 b8 04[ ]+fmaddpd %xmm11,%xmm2,0x4\(%rdx\),%xmm11 + [ ]+7a8:[ ]+0f 24 0a d3 b0[ ]+fmsubss %xmm3,%xmm2,%xmm11,%xmm11 + [ ]+7ad:[ ]+0f 24 0a 52 b0 04[ ]+fmsubss 0x4\(%rdx\),%xmm2,%xmm11,%xmm11 + [ ]+7b3:[ ]+0f 24 0a 52 b8 04[ ]+fmsubss %xmm2,0x4\(%rdx\),%xmm11,%xmm11 + [ ]+7b9:[ ]+0f 24 0e d3 b0[ ]+fmsubss %xmm11,%xmm3,%xmm2,%xmm11 + [ ]+7be:[ ]+0f 24 0e 52 b0 04[ ]+fmsubss %xmm11,0x4\(%rdx\),%xmm2,%xmm11 + [ ]+7c4:[ ]+0f 24 0e 52 b8 04[ ]+fmsubss %xmm11,%xmm2,0x4\(%rdx\),%xmm11 + [ ]+7ca:[ ]+0f 24 0b d3 b0[ ]+fmsubsd %xmm3,%xmm2,%xmm11,%xmm11 + [ ]+7cf:[ ]+0f 24 0b 52 b0 04[ ]+fmsubsd 0x4\(%rdx\),%xmm2,%xmm11,%xmm11 + [ ]+7d5:[ ]+0f 24 0b 52 b8 04[ ]+fmsubsd %xmm2,0x4\(%rdx\),%xmm11,%xmm11 + [ ]+7db:[ ]+0f 24 0f d3 b0[ ]+fmsubsd %xmm11,%xmm3,%xmm2,%xmm11 + [ ]+7e0:[ ]+0f 24 0f 52 b0 04[ ]+fmsubsd %xmm11,0x4\(%rdx\),%xmm2,%xmm11 + [ ]+7e6:[ ]+0f 24 0f 52 b8 04[ ]+fmsubsd %xmm11,%xmm2,0x4\(%rdx\),%xmm11 + [ ]+7ec:[ ]+0f 24 08 d3 b0[ ]+fmsubps %xmm3,%xmm2,%xmm11,%xmm11 + [ ]+7f1:[ ]+0f 24 08 52 b0 04[ ]+fmsubps 0x4\(%rdx\),%xmm2,%xmm11,%xmm11 + [ ]+7f7:[ ]+0f 24 08 52 b8 04[ ]+fmsubps %xmm2,0x4\(%rdx\),%xmm11,%xmm11 + [ ]+7fd:[ ]+0f 24 0c d3 b0[ ]+fmsubps %xmm11,%xmm3,%xmm2,%xmm11 + [ ]+802:[ ]+0f 24 0c 52 b0 04[ ]+fmsubps %xmm11,0x4\(%rdx\),%xmm2,%xmm11 + [ ]+808:[ ]+0f 24 0c 52 b8 04[ ]+fmsubps %xmm11,%xmm2,0x4\(%rdx\),%xmm11 + [ ]+80e:[ ]+0f 24 09 d3 b0[ ]+fmsubpd %xmm3,%xmm2,%xmm11,%xmm11 + [ ]+813:[ ]+0f 24 09 52 b0 04[ ]+fmsubpd 0x4\(%rdx\),%xmm2,%xmm11,%xmm11 + [ ]+819:[ ]+0f 24 09 52 b8 04[ ]+fmsubpd %xmm2,0x4\(%rdx\),%xmm11,%xmm11 + [ ]+81f:[ ]+0f 24 0d d3 b0[ ]+fmsubpd %xmm11,%xmm3,%xmm2,%xmm11 + [ ]+824:[ ]+0f 24 0d 52 b0 04[ ]+fmsubpd %xmm11,0x4\(%rdx\),%xmm2,%xmm11 + [ ]+82a:[ ]+0f 24 0d 52 b8 04[ ]+fmsubpd %xmm11,%xmm2,0x4\(%rdx\),%xmm11 + [ ]+830:[ ]+0f 24 12 d3 b0[ ]+fnmaddss %xmm3,%xmm2,%xmm11,%xmm11 + [ ]+835:[ ]+0f 24 12 52 b0 04[ ]+fnmaddss 0x4\(%rdx\),%xmm2,%xmm11,%xmm11 + [ ]+83b:[ ]+0f 24 12 52 b8 04[ ]+fnmaddss %xmm2,0x4\(%rdx\),%xmm11,%xmm11 + [ ]+841:[ ]+0f 24 16 d3 b0[ ]+fnmaddss %xmm11,%xmm3,%xmm2,%xmm11 + [ ]+846:[ ]+0f 24 16 52 b0 04[ ]+fnmaddss %xmm11,0x4\(%rdx\),%xmm2,%xmm11 + [ ]+84c:[ ]+0f 24 16 52 b8 04[ ]+fnmaddss %xmm11,%xmm2,0x4\(%rdx\),%xmm11 + [ ]+852:[ ]+0f 24 13 d3 b0[ ]+fnmaddsd %xmm3,%xmm2,%xmm11,%xmm11 + [ ]+857:[ ]+0f 24 13 52 b0 04[ ]+fnmaddsd 0x4\(%rdx\),%xmm2,%xmm11,%xmm11 + [ ]+85d:[ ]+0f 24 13 52 b8 04[ ]+fnmaddsd %xmm2,0x4\(%rdx\),%xmm11,%xmm11 + [ ]+863:[ ]+0f 24 17 d3 b0[ ]+fnmaddsd %xmm11,%xmm3,%xmm2,%xmm11 + [ ]+868:[ ]+0f 24 17 52 b0 04[ ]+fnmaddsd %xmm11,0x4\(%rdx\),%xmm2,%xmm11 + [ ]+86e:[ ]+0f 24 17 52 b8 04[ ]+fnmaddsd %xmm11,%xmm2,0x4\(%rdx\),%xmm11 + [ ]+874:[ ]+0f 24 10 d3 b0[ ]+fnmaddps %xmm3,%xmm2,%xmm11,%xmm11 + [ ]+879:[ ]+0f 24 10 52 b0 04[ ]+fnmaddps 0x4\(%rdx\),%xmm2,%xmm11,%xmm11 + [ ]+87f:[ ]+0f 24 10 52 b8 04[ ]+fnmaddps %xmm2,0x4\(%rdx\),%xmm11,%xmm11 + [ ]+885:[ ]+0f 24 14 d3 b0[ ]+fnmaddps %xmm11,%xmm3,%xmm2,%xmm11 + [ ]+88a:[ ]+0f 24 14 52 b0 04[ ]+fnmaddps %xmm11,0x4\(%rdx\),%xmm2,%xmm11 + [ ]+890:[ ]+0f 24 14 52 b8 04[ ]+fnmaddps %xmm11,%xmm2,0x4\(%rdx\),%xmm11 + [ ]+896:[ ]+0f 24 11 d3 b0[ ]+fnmaddpd %xmm3,%xmm2,%xmm11,%xmm11 + [ ]+89b:[ ]+0f 24 11 52 b0 04[ ]+fnmaddpd 0x4\(%rdx\),%xmm2,%xmm11,%xmm11 + [ ]+8a1:[ ]+0f 24 11 52 b8 04[ ]+fnmaddpd %xmm2,0x4\(%rdx\),%xmm11,%xmm11 + [ ]+8a7:[ ]+0f 24 15 d3 b0[ ]+fnmaddpd %xmm11,%xmm3,%xmm2,%xmm11 + [ ]+8ac:[ ]+0f 24 15 52 b0 04[ ]+fnmaddpd %xmm11,0x4\(%rdx\),%xmm2,%xmm11 + [ ]+8b2:[ ]+0f 24 15 52 b8 04[ ]+fnmaddpd %xmm11,%xmm2,0x4\(%rdx\),%xmm11 + [ ]+8b8:[ ]+0f 24 1a d3 b0[ ]+fnmsubss %xmm3,%xmm2,%xmm11,%xmm11 + [ ]+8bd:[ ]+0f 24 1a 52 b0 04[ ]+fnmsubss 0x4\(%rdx\),%xmm2,%xmm11,%xmm11 + [ ]+8c3:[ ]+0f 24 1a 52 b8 04[ ]+fnmsubss %xmm2,0x4\(%rdx\),%xmm11,%xmm11 + [ ]+8c9:[ ]+0f 24 1e d3 b0[ ]+fnmsubss %xmm11,%xmm3,%xmm2,%xmm11 + [ ]+8ce:[ ]+0f 24 1e 52 b0 04[ ]+fnmsubss %xmm11,0x4\(%rdx\),%xmm2,%xmm11 + [ ]+8d4:[ ]+0f 24 1e 52 b8 04[ ]+fnmsubss %xmm11,%xmm2,0x4\(%rdx\),%xmm11 + [ ]+8da:[ ]+0f 24 1b d3 b0[ ]+fnmsubsd %xmm3,%xmm2,%xmm11,%xmm11 + [ ]+8df:[ ]+0f 24 1b 52 b0 04[ ]+fnmsubsd 0x4\(%rdx\),%xmm2,%xmm11,%xmm11 + [ ]+8e5:[ ]+0f 24 1b 52 b8 04[ ]+fnmsubsd %xmm2,0x4\(%rdx\),%xmm11,%xmm11 + [ ]+8eb:[ ]+0f 24 1f d3 b0[ ]+fnmsubsd %xmm11,%xmm3,%xmm2,%xmm11 + [ ]+8f0:[ ]+0f 24 1f 52 b0 04[ ]+fnmsubsd %xmm11,0x4\(%rdx\),%xmm2,%xmm11 + [ ]+8f6:[ ]+0f 24 1f 52 b8 04[ ]+fnmsubsd %xmm11,%xmm2,0x4\(%rdx\),%xmm11 + [ ]+8fc:[ ]+0f 24 18 d3 b0[ ]+fnmsubps %xmm3,%xmm2,%xmm11,%xmm11 + [ ]+901:[ ]+0f 24 18 52 b0 04[ ]+fnmsubps 0x4\(%rdx\),%xmm2,%xmm11,%xmm11 + [ ]+907:[ ]+0f 24 18 52 b8 04[ ]+fnmsubps %xmm2,0x4\(%rdx\),%xmm11,%xmm11 + [ ]+90d:[ ]+0f 24 1c d3 b0[ ]+fnmsubps %xmm11,%xmm3,%xmm2,%xmm11 + [ ]+912:[ ]+0f 24 1c 52 b0 04[ ]+fnmsubps %xmm11,0x4\(%rdx\),%xmm2,%xmm11 + [ ]+918:[ ]+0f 24 1c 52 b8 04[ ]+fnmsubps %xmm11,%xmm2,0x4\(%rdx\),%xmm11 + [ ]+91e:[ ]+0f 24 19 d3 b0[ ]+fnmsubpd %xmm3,%xmm2,%xmm11,%xmm11 + [ ]+923:[ ]+0f 24 19 52 b0 04[ ]+fnmsubpd 0x4\(%rdx\),%xmm2,%xmm11,%xmm11 + [ ]+929:[ ]+0f 24 19 52 b8 04[ ]+fnmsubpd %xmm2,0x4\(%rdx\),%xmm11,%xmm11 + [ ]+92f:[ ]+0f 24 1d d3 b0[ ]+fnmsubpd %xmm11,%xmm3,%xmm2,%xmm11 + [ ]+934:[ ]+0f 24 1d 52 b0 04[ ]+fnmsubpd %xmm11,0x4\(%rdx\),%xmm2,%xmm11 + [ ]+93a:[ ]+0f 24 1d 52 b8 04[ ]+fnmsubpd %xmm11,%xmm2,0x4\(%rdx\),%xmm11 + [ ]+940:[ ]+0f 24 02 d5 11[ ]+fmaddss %xmm13,%xmm2,%xmm1,%xmm1 + [ ]+945:[ ]+0f 24 02 52 10 04[ ]+fmaddss 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+94b:[ ]+0f 24 02 52 18 04[ ]+fmaddss %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+951:[ ]+0f 24 06 d5 11[ ]+fmaddss %xmm1,%xmm13,%xmm2,%xmm1 + [ ]+956:[ ]+0f 24 06 52 10 04[ ]+fmaddss %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+95c:[ ]+0f 24 06 52 18 04[ ]+fmaddss %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+962:[ ]+0f 24 03 d5 11[ ]+fmaddsd %xmm13,%xmm2,%xmm1,%xmm1 + [ ]+967:[ ]+0f 24 03 52 10 04[ ]+fmaddsd 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+96d:[ ]+0f 24 03 52 18 04[ ]+fmaddsd %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+973:[ ]+0f 24 07 d5 11[ ]+fmaddsd %xmm1,%xmm13,%xmm2,%xmm1 + [ ]+978:[ ]+0f 24 07 52 10 04[ ]+fmaddsd %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+97e:[ ]+0f 24 07 52 18 04[ ]+fmaddsd %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+984:[ ]+0f 24 00 d5 11[ ]+fmaddps %xmm13,%xmm2,%xmm1,%xmm1 + [ ]+989:[ ]+0f 24 00 52 10 04[ ]+fmaddps 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+98f:[ ]+0f 24 00 52 18 04[ ]+fmaddps %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+995:[ ]+0f 24 04 d5 11[ ]+fmaddps %xmm1,%xmm13,%xmm2,%xmm1 + [ ]+99a:[ ]+0f 24 04 52 10 04[ ]+fmaddps %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+9a0:[ ]+0f 24 04 52 18 04[ ]+fmaddps %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+9a6:[ ]+0f 24 01 d5 11[ ]+fmaddpd %xmm13,%xmm2,%xmm1,%xmm1 + [ ]+9ab:[ ]+0f 24 01 52 10 04[ ]+fmaddpd 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+9b1:[ ]+0f 24 01 52 18 04[ ]+fmaddpd %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+9b7:[ ]+0f 24 05 d5 11[ ]+fmaddpd %xmm1,%xmm13,%xmm2,%xmm1 + [ ]+9bc:[ ]+0f 24 05 52 10 04[ ]+fmaddpd %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+9c2:[ ]+0f 24 05 52 18 04[ ]+fmaddpd %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+9c8:[ ]+0f 24 0a d5 11[ ]+fmsubss %xmm13,%xmm2,%xmm1,%xmm1 + [ ]+9cd:[ ]+0f 24 0a 52 10 04[ ]+fmsubss 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+9d3:[ ]+0f 24 0a 52 18 04[ ]+fmsubss %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+9d9:[ ]+0f 24 0e d5 11[ ]+fmsubss %xmm1,%xmm13,%xmm2,%xmm1 + [ ]+9de:[ ]+0f 24 0e 52 10 04[ ]+fmsubss %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+9e4:[ ]+0f 24 0e 52 18 04[ ]+fmsubss %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+9ea:[ ]+0f 24 0b d5 11[ ]+fmsubsd %xmm13,%xmm2,%xmm1,%xmm1 + [ ]+9ef:[ ]+0f 24 0b 52 10 04[ ]+fmsubsd 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+9f5:[ ]+0f 24 0b 52 18 04[ ]+fmsubsd %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+9fb:[ ]+0f 24 0f d5 11[ ]+fmsubsd %xmm1,%xmm13,%xmm2,%xmm1 + [ ]+a00:[ ]+0f 24 0f 52 10 04[ ]+fmsubsd %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+a06:[ ]+0f 24 0f 52 18 04[ ]+fmsubsd %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+a0c:[ ]+0f 24 08 d5 11[ ]+fmsubps %xmm13,%xmm2,%xmm1,%xmm1 + [ ]+a11:[ ]+0f 24 08 52 10 04[ ]+fmsubps 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+a17:[ ]+0f 24 08 52 18 04[ ]+fmsubps %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+a1d:[ ]+0f 24 0c d5 11[ ]+fmsubps %xmm1,%xmm13,%xmm2,%xmm1 + [ ]+a22:[ ]+0f 24 0c 52 10 04[ ]+fmsubps %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+a28:[ ]+0f 24 0c 52 18 04[ ]+fmsubps %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+a2e:[ ]+0f 24 09 d5 11[ ]+fmsubpd %xmm13,%xmm2,%xmm1,%xmm1 + [ ]+a33:[ ]+0f 24 09 52 10 04[ ]+fmsubpd 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+a39:[ ]+0f 24 09 52 18 04[ ]+fmsubpd %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+a3f:[ ]+0f 24 0d d5 11[ ]+fmsubpd %xmm1,%xmm13,%xmm2,%xmm1 + [ ]+a44:[ ]+0f 24 0d 52 10 04[ ]+fmsubpd %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+a4a:[ ]+0f 24 0d 52 18 04[ ]+fmsubpd %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+a50:[ ]+0f 24 12 d5 11[ ]+fnmaddss %xmm13,%xmm2,%xmm1,%xmm1 + [ ]+a55:[ ]+0f 24 12 52 10 04[ ]+fnmaddss 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+a5b:[ ]+0f 24 12 52 18 04[ ]+fnmaddss %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+a61:[ ]+0f 24 16 d5 11[ ]+fnmaddss %xmm1,%xmm13,%xmm2,%xmm1 + [ ]+a66:[ ]+0f 24 16 52 10 04[ ]+fnmaddss %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+a6c:[ ]+0f 24 16 52 18 04[ ]+fnmaddss %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+a72:[ ]+0f 24 13 d5 11[ ]+fnmaddsd %xmm13,%xmm2,%xmm1,%xmm1 + [ ]+a77:[ ]+0f 24 13 52 10 04[ ]+fnmaddsd 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+a7d:[ ]+0f 24 13 52 18 04[ ]+fnmaddsd %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+a83:[ ]+0f 24 17 d5 11[ ]+fnmaddsd %xmm1,%xmm13,%xmm2,%xmm1 + [ ]+a88:[ ]+0f 24 17 52 10 04[ ]+fnmaddsd %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+a8e:[ ]+0f 24 17 52 18 04[ ]+fnmaddsd %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+a94:[ ]+0f 24 10 d5 11[ ]+fnmaddps %xmm13,%xmm2,%xmm1,%xmm1 + [ ]+a99:[ ]+0f 24 10 52 10 04[ ]+fnmaddps 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+a9f:[ ]+0f 24 10 52 18 04[ ]+fnmaddps %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+aa5:[ ]+0f 24 14 d5 11[ ]+fnmaddps %xmm1,%xmm13,%xmm2,%xmm1 + [ ]+aaa:[ ]+0f 24 14 52 10 04[ ]+fnmaddps %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+ab0:[ ]+0f 24 14 52 18 04[ ]+fnmaddps %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+ab6:[ ]+0f 24 11 d5 11[ ]+fnmaddpd %xmm13,%xmm2,%xmm1,%xmm1 + [ ]+abb:[ ]+0f 24 11 52 10 04[ ]+fnmaddpd 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+ac1:[ ]+0f 24 11 52 18 04[ ]+fnmaddpd %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+ac7:[ ]+0f 24 15 d5 11[ ]+fnmaddpd %xmm1,%xmm13,%xmm2,%xmm1 + [ ]+acc:[ ]+0f 24 15 52 10 04[ ]+fnmaddpd %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+ad2:[ ]+0f 24 15 52 18 04[ ]+fnmaddpd %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+ad8:[ ]+0f 24 1a d5 11[ ]+fnmsubss %xmm13,%xmm2,%xmm1,%xmm1 + [ ]+add:[ ]+0f 24 1a 52 10 04[ ]+fnmsubss 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+ae3:[ ]+0f 24 1a 52 18 04[ ]+fnmsubss %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+ae9:[ ]+0f 24 1e d5 11[ ]+fnmsubss %xmm1,%xmm13,%xmm2,%xmm1 + [ ]+aee:[ ]+0f 24 1e 52 10 04[ ]+fnmsubss %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+af4:[ ]+0f 24 1e 52 18 04[ ]+fnmsubss %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+afa:[ ]+0f 24 1b d5 11[ ]+fnmsubsd %xmm13,%xmm2,%xmm1,%xmm1 + [ ]+aff:[ ]+0f 24 1b 52 10 04[ ]+fnmsubsd 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+b05:[ ]+0f 24 1b 52 18 04[ ]+fnmsubsd %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+b0b:[ ]+0f 24 1f d5 11[ ]+fnmsubsd %xmm1,%xmm13,%xmm2,%xmm1 + [ ]+b10:[ ]+0f 24 1f 52 10 04[ ]+fnmsubsd %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+b16:[ ]+0f 24 1f 52 18 04[ ]+fnmsubsd %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+b1c:[ ]+0f 24 18 d5 11[ ]+fnmsubps %xmm13,%xmm2,%xmm1,%xmm1 + [ ]+b21:[ ]+0f 24 18 52 10 04[ ]+fnmsubps 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+b27:[ ]+0f 24 18 52 18 04[ ]+fnmsubps %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+b2d:[ ]+0f 24 1c d5 11[ ]+fnmsubps %xmm1,%xmm13,%xmm2,%xmm1 + [ ]+b32:[ ]+0f 24 1c 52 10 04[ ]+fnmsubps %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+b38:[ ]+0f 24 1c 52 18 04[ ]+fnmsubps %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+b3e:[ ]+0f 24 19 d5 11[ ]+fnmsubpd %xmm13,%xmm2,%xmm1,%xmm1 + [ ]+b43:[ ]+0f 24 19 52 10 04[ ]+fnmsubpd 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+b49:[ ]+0f 24 19 52 18 04[ ]+fnmsubpd %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+b4f:[ ]+0f 24 1d d5 11[ ]+fnmsubpd %xmm1,%xmm13,%xmm2,%xmm1 + [ ]+b54:[ ]+0f 24 1d 52 10 04[ ]+fnmsubpd %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+b5a:[ ]+0f 24 1d 52 18 04[ ]+fnmsubpd %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+b60:[ ]+0f 24 02 d3 10[ ]+fmaddss %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+b65:[ ]+0f 24 02 97 11 00 00 10 00[ ]+fmaddss 0x100000\(%r15\),%xmm2,%xmm1,%xmm1 + [ ]+b6e:[ ]+0f 24 02 97 19 00 00 10 00[ ]+fmaddss %xmm2,0x100000\(%r15\),%xmm1,%xmm1 + [ ]+b77:[ ]+0f 24 06 d3 10[ ]+fmaddss %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+b7c:[ ]+0f 24 06 97 11 00 00 10 00[ ]+fmaddss %xmm1,0x100000\(%r15\),%xmm2,%xmm1 + [ ]+b85:[ ]+0f 24 06 97 19 00 00 10 00[ ]+fmaddss %xmm1,%xmm2,0x100000\(%r15\),%xmm1 + [ ]+b8e:[ ]+0f 24 03 d3 10[ ]+fmaddsd %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+b93:[ ]+0f 24 03 97 11 00 00 10 00[ ]+fmaddsd 0x100000\(%r15\),%xmm2,%xmm1,%xmm1 + [ ]+b9c:[ ]+0f 24 03 97 19 00 00 10 00[ ]+fmaddsd %xmm2,0x100000\(%r15\),%xmm1,%xmm1 + [ ]+ba5:[ ]+0f 24 07 d3 10[ ]+fmaddsd %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+baa:[ ]+0f 24 07 97 11 00 00 10 00[ ]+fmaddsd %xmm1,0x100000\(%r15\),%xmm2,%xmm1 + [ ]+bb3:[ ]+0f 24 07 97 19 00 00 10 00[ ]+fmaddsd %xmm1,%xmm2,0x100000\(%r15\),%xmm1 + [ ]+bbc:[ ]+0f 24 00 d3 10[ ]+fmaddps %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+bc1:[ ]+0f 24 00 97 11 00 00 10 00[ ]+fmaddps 0x100000\(%r15\),%xmm2,%xmm1,%xmm1 + [ ]+bca:[ ]+0f 24 00 97 19 00 00 10 00[ ]+fmaddps %xmm2,0x100000\(%r15\),%xmm1,%xmm1 + [ ]+bd3:[ ]+0f 24 04 d3 10[ ]+fmaddps %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+bd8:[ ]+0f 24 04 97 11 00 00 10 00[ ]+fmaddps %xmm1,0x100000\(%r15\),%xmm2,%xmm1 + [ ]+be1:[ ]+0f 24 04 97 19 00 00 10 00[ ]+fmaddps %xmm1,%xmm2,0x100000\(%r15\),%xmm1 + [ ]+bea:[ ]+0f 24 01 d3 10[ ]+fmaddpd %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+bef:[ ]+0f 24 01 97 11 00 00 10 00[ ]+fmaddpd 0x100000\(%r15\),%xmm2,%xmm1,%xmm1 + [ ]+bf8:[ ]+0f 24 01 97 19 00 00 10 00[ ]+fmaddpd %xmm2,0x100000\(%r15\),%xmm1,%xmm1 + [ ]+c01:[ ]+0f 24 05 d3 10[ ]+fmaddpd %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+c06:[ ]+0f 24 05 97 11 00 00 10 00[ ]+fmaddpd %xmm1,0x100000\(%r15\),%xmm2,%xmm1 + [ ]+c0f:[ ]+0f 24 05 97 19 00 00 10 00[ ]+fmaddpd %xmm1,%xmm2,0x100000\(%r15\),%xmm1 + [ ]+c18:[ ]+0f 24 0a d3 10[ ]+fmsubss %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+c1d:[ ]+0f 24 0a 97 11 00 00 10 00[ ]+fmsubss 0x100000\(%r15\),%xmm2,%xmm1,%xmm1 + [ ]+c26:[ ]+0f 24 0a 97 19 00 00 10 00[ ]+fmsubss %xmm2,0x100000\(%r15\),%xmm1,%xmm1 + [ ]+c2f:[ ]+0f 24 0e d3 10[ ]+fmsubss %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+c34:[ ]+0f 24 0e 97 11 00 00 10 00[ ]+fmsubss %xmm1,0x100000\(%r15\),%xmm2,%xmm1 + [ ]+c3d:[ ]+0f 24 0e 97 19 00 00 10 00[ ]+fmsubss %xmm1,%xmm2,0x100000\(%r15\),%xmm1 + [ ]+c46:[ ]+0f 24 0b d3 10[ ]+fmsubsd %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+c4b:[ ]+0f 24 0b 97 11 00 00 10 00[ ]+fmsubsd 0x100000\(%r15\),%xmm2,%xmm1,%xmm1 + [ ]+c54:[ ]+0f 24 0b 97 19 00 00 10 00[ ]+fmsubsd %xmm2,0x100000\(%r15\),%xmm1,%xmm1 + [ ]+c5d:[ ]+0f 24 0f d3 10[ ]+fmsubsd %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+c62:[ ]+0f 24 0f 97 11 00 00 10 00[ ]+fmsubsd %xmm1,0x100000\(%r15\),%xmm2,%xmm1 + [ ]+c6b:[ ]+0f 24 0f 97 19 00 00 10 00[ ]+fmsubsd %xmm1,%xmm2,0x100000\(%r15\),%xmm1 + [ ]+c74:[ ]+0f 24 08 d3 10[ ]+fmsubps %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+c79:[ ]+0f 24 08 97 11 00 00 10 00[ ]+fmsubps 0x100000\(%r15\),%xmm2,%xmm1,%xmm1 + [ ]+c82:[ ]+0f 24 08 97 19 00 00 10 00[ ]+fmsubps %xmm2,0x100000\(%r15\),%xmm1,%xmm1 + [ ]+c8b:[ ]+0f 24 0c d3 10[ ]+fmsubps %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+c90:[ ]+0f 24 0c 97 11 00 00 10 00[ ]+fmsubps %xmm1,0x100000\(%r15\),%xmm2,%xmm1 + [ ]+c99:[ ]+0f 24 0c 97 19 00 00 10 00[ ]+fmsubps %xmm1,%xmm2,0x100000\(%r15\),%xmm1 + [ ]+ca2:[ ]+0f 24 09 d3 10[ ]+fmsubpd %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+ca7:[ ]+0f 24 09 97 11 00 00 10 00[ ]+fmsubpd 0x100000\(%r15\),%xmm2,%xmm1,%xmm1 + [ ]+cb0:[ ]+0f 24 09 97 19 00 00 10 00[ ]+fmsubpd %xmm2,0x100000\(%r15\),%xmm1,%xmm1 + [ ]+cb9:[ ]+0f 24 0d d3 10[ ]+fmsubpd %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+cbe:[ ]+0f 24 0d 97 11 00 00 10 00[ ]+fmsubpd %xmm1,0x100000\(%r15\),%xmm2,%xmm1 + [ ]+cc7:[ ]+0f 24 0d 97 19 00 00 10 00[ ]+fmsubpd %xmm1,%xmm2,0x100000\(%r15\),%xmm1 + [ ]+cd0:[ ]+0f 24 12 d3 10[ ]+fnmaddss %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+cd5:[ ]+0f 24 12 97 11 00 00 10 00[ ]+fnmaddss 0x100000\(%r15\),%xmm2,%xmm1,%xmm1 + [ ]+cde:[ ]+0f 24 12 97 19 00 00 10 00[ ]+fnmaddss %xmm2,0x100000\(%r15\),%xmm1,%xmm1 + [ ]+ce7:[ ]+0f 24 16 d3 10[ ]+fnmaddss %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+cec:[ ]+0f 24 16 97 11 00 00 10 00[ ]+fnmaddss %xmm1,0x100000\(%r15\),%xmm2,%xmm1 + [ ]+cf5:[ ]+0f 24 16 97 19 00 00 10 00[ ]+fnmaddss %xmm1,%xmm2,0x100000\(%r15\),%xmm1 + [ ]+cfe:[ ]+0f 24 13 d3 10[ ]+fnmaddsd %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+d03:[ ]+0f 24 13 97 11 00 00 10 00[ ]+fnmaddsd 0x100000\(%r15\),%xmm2,%xmm1,%xmm1 + [ ]+d0c:[ ]+0f 24 13 97 19 00 00 10 00[ ]+fnmaddsd %xmm2,0x100000\(%r15\),%xmm1,%xmm1 + [ ]+d15:[ ]+0f 24 17 d3 10[ ]+fnmaddsd %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+d1a:[ ]+0f 24 17 97 11 00 00 10 00[ ]+fnmaddsd %xmm1,0x100000\(%r15\),%xmm2,%xmm1 + [ ]+d23:[ ]+0f 24 17 97 19 00 00 10 00[ ]+fnmaddsd %xmm1,%xmm2,0x100000\(%r15\),%xmm1 + [ ]+d2c:[ ]+0f 24 10 d3 10[ ]+fnmaddps %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+d31:[ ]+0f 24 10 97 11 00 00 10 00[ ]+fnmaddps 0x100000\(%r15\),%xmm2,%xmm1,%xmm1 + [ ]+d3a:[ ]+0f 24 10 97 19 00 00 10 00[ ]+fnmaddps %xmm2,0x100000\(%r15\),%xmm1,%xmm1 + [ ]+d43:[ ]+0f 24 14 d3 10[ ]+fnmaddps %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+d48:[ ]+0f 24 14 97 11 00 00 10 00[ ]+fnmaddps %xmm1,0x100000\(%r15\),%xmm2,%xmm1 + [ ]+d51:[ ]+0f 24 14 97 19 00 00 10 00[ ]+fnmaddps %xmm1,%xmm2,0x100000\(%r15\),%xmm1 + [ ]+d5a:[ ]+0f 24 11 d3 10[ ]+fnmaddpd %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+d5f:[ ]+0f 24 11 97 11 00 00 10 00[ ]+fnmaddpd 0x100000\(%r15\),%xmm2,%xmm1,%xmm1 + [ ]+d68:[ ]+0f 24 11 97 19 00 00 10 00[ ]+fnmaddpd %xmm2,0x100000\(%r15\),%xmm1,%xmm1 + [ ]+d71:[ ]+0f 24 15 d3 10[ ]+fnmaddpd %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+d76:[ ]+0f 24 15 97 11 00 00 10 00[ ]+fnmaddpd %xmm1,0x100000\(%r15\),%xmm2,%xmm1 + [ ]+d7f:[ ]+0f 24 15 97 19 00 00 10 00[ ]+fnmaddpd %xmm1,%xmm2,0x100000\(%r15\),%xmm1 + [ ]+d88:[ ]+0f 24 1a d3 10[ ]+fnmsubss %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+d8d:[ ]+0f 24 1a 97 11 00 00 10 00[ ]+fnmsubss 0x100000\(%r15\),%xmm2,%xmm1,%xmm1 + [ ]+d96:[ ]+0f 24 1a 97 19 00 00 10 00[ ]+fnmsubss %xmm2,0x100000\(%r15\),%xmm1,%xmm1 + [ ]+d9f:[ ]+0f 24 1e d3 10[ ]+fnmsubss %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+da4:[ ]+0f 24 1e 97 11 00 00 10 00[ ]+fnmsubss %xmm1,0x100000\(%r15\),%xmm2,%xmm1 + [ ]+dad:[ ]+0f 24 1e 97 19 00 00 10 00[ ]+fnmsubss %xmm1,%xmm2,0x100000\(%r15\),%xmm1 + [ ]+db6:[ ]+0f 24 1b d3 10[ ]+fnmsubsd %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+dbb:[ ]+0f 24 1b 97 11 00 00 10 00[ ]+fnmsubsd 0x100000\(%r15\),%xmm2,%xmm1,%xmm1 + [ ]+dc4:[ ]+0f 24 1b 97 19 00 00 10 00[ ]+fnmsubsd %xmm2,0x100000\(%r15\),%xmm1,%xmm1 + [ ]+dcd:[ ]+0f 24 1f d3 10[ ]+fnmsubsd %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+dd2:[ ]+0f 24 1f 97 11 00 00 10 00[ ]+fnmsubsd %xmm1,0x100000\(%r15\),%xmm2,%xmm1 + [ ]+ddb:[ ]+0f 24 1f 97 19 00 00 10 00[ ]+fnmsubsd %xmm1,%xmm2,0x100000\(%r15\),%xmm1 + [ ]+de4:[ ]+0f 24 18 d3 10[ ]+fnmsubps %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+de9:[ ]+0f 24 18 97 11 00 00 10 00[ ]+fnmsubps 0x100000\(%r15\),%xmm2,%xmm1,%xmm1 + [ ]+df2:[ ]+0f 24 18 97 19 00 00 10 00[ ]+fnmsubps %xmm2,0x100000\(%r15\),%xmm1,%xmm1 + [ ]+dfb:[ ]+0f 24 1c d3 10[ ]+fnmsubps %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+e00:[ ]+0f 24 1c 97 11 00 00 10 00[ ]+fnmsubps %xmm1,0x100000\(%r15\),%xmm2,%xmm1 + [ ]+e09:[ ]+0f 24 1c 97 19 00 00 10 00[ ]+fnmsubps %xmm1,%xmm2,0x100000\(%r15\),%xmm1 + [ ]+e12:[ ]+0f 24 19 d3 10[ ]+fnmsubpd %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+e17:[ ]+0f 24 19 97 11 00 00 10 00[ ]+fnmsubpd 0x100000\(%r15\),%xmm2,%xmm1,%xmm1 + [ ]+e20:[ ]+0f 24 19 97 19 00 00 10 00[ ]+fnmsubpd %xmm2,0x100000\(%r15\),%xmm1,%xmm1 + [ ]+e29:[ ]+0f 24 1d d3 10[ ]+fnmsubpd %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+e2e:[ ]+0f 24 1d 97 11 00 00 10 00[ ]+fnmsubpd %xmm1,0x100000\(%r15\),%xmm2,%xmm1 + [ ]+e37:[ ]+0f 24 1d 97 19 00 00 10 00[ ]+fnmsubpd %xmm1,%xmm2,0x100000\(%r15\),%xmm1 + [ ]+e40:[ ]+0f 24 85 d3 10[ ]+pmacssww %xmm1,%xmm2,%xmm3,%xmm1 + [ ]+e45:[ ]+0f 24 85 52 10 04[ ]+pmacssww %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+e4b:[ ]+0f 24 95 d3 10[ ]+pmacsww %xmm1,%xmm2,%xmm3,%xmm1 + [ ]+e50:[ ]+0f 24 95 52 10 04[ ]+pmacsww %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+e56:[ ]+0f 24 96 d3 10[ ]+pmacswd %xmm1,%xmm2,%xmm3,%xmm1 + [ ]+e5b:[ ]+0f 24 96 52 10 04[ ]+pmacswd %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+e61:[ ]+0f 24 8e d3 10[ ]+pmacssdd %xmm1,%xmm2,%xmm3,%xmm1 + [ ]+e66:[ ]+0f 24 8e 52 10 04[ ]+pmacssdd %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+e6c:[ ]+0f 24 9e d3 10[ ]+pmacsdd %xmm1,%xmm2,%xmm3,%xmm1 + [ ]+e71:[ ]+0f 24 9e 52 10 04[ ]+pmacsdd %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+e77:[ ]+0f 24 87 d3 10[ ]+pmacssdql %xmm1,%xmm2,%xmm3,%xmm1 + [ ]+e7c:[ ]+0f 24 87 52 10 04[ ]+pmacssdql %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+e82:[ ]+0f 24 8f d3 10[ ]+pmacssdqh %xmm1,%xmm2,%xmm3,%xmm1 + [ ]+e87:[ ]+0f 24 8f 52 10 04[ ]+pmacssdqh %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+e8d:[ ]+0f 24 97 d3 10[ ]+pmacsdql %xmm1,%xmm2,%xmm3,%xmm1 + [ ]+e92:[ ]+0f 24 97 52 10 04[ ]+pmacsdql %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+e98:[ ]+0f 24 9f d3 10[ ]+pmacsdqh %xmm1,%xmm2,%xmm3,%xmm1 + [ ]+e9d:[ ]+0f 24 9f 52 10 04[ ]+pmacsdqh %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+ea3:[ ]+0f 24 a6 d3 10[ ]+pmadcsswd %xmm1,%xmm2,%xmm3,%xmm1 + [ ]+ea8:[ ]+0f 24 a6 52 10 04[ ]+pmadcsswd %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+eae:[ ]+0f 24 b6 d3 10[ ]+pmadcswd %xmm1,%xmm2,%xmm3,%xmm1 + [ ]+eb3:[ ]+0f 24 b6 52 10 04[ ]+pmadcswd %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+eb9:[ ]+0f 24 85 e5 b5[ ]+pmacssww %xmm11,%xmm12,%xmm13,%xmm11 + [ ]+ebe:[ ]+0f 24 85 a7 b5 00 00 10 00[ ]+pmacssww %xmm11,%xmm12,0x100000\(%r15\),%xmm11 + [ ]+ec7:[ ]+0f 24 95 e5 b5[ ]+pmacsww %xmm11,%xmm12,%xmm13,%xmm11 + [ ]+ecc:[ ]+0f 24 95 a7 b5 00 00 10 00[ ]+pmacsww %xmm11,%xmm12,0x100000\(%r15\),%xmm11 + [ ]+ed5:[ ]+0f 24 96 e5 b5[ ]+pmacswd %xmm11,%xmm12,%xmm13,%xmm11 + [ ]+eda:[ ]+0f 24 96 a7 b5 00 00 10 00[ ]+pmacswd %xmm11,%xmm12,0x100000\(%r15\),%xmm11 + [ ]+ee3:[ ]+0f 24 8e e5 b5[ ]+pmacssdd %xmm11,%xmm12,%xmm13,%xmm11 + [ ]+ee8:[ ]+0f 24 8e a7 b5 00 00 10 00[ ]+pmacssdd %xmm11,%xmm12,0x100000\(%r15\),%xmm11 + [ ]+ef1:[ ]+0f 24 9e e5 b5[ ]+pmacsdd %xmm11,%xmm12,%xmm13,%xmm11 + [ ]+ef6:[ ]+0f 24 9e a7 b5 00 00 10 00[ ]+pmacsdd %xmm11,%xmm12,0x100000\(%r15\),%xmm11 + [ ]+eff:[ ]+0f 24 87 e5 b5[ ]+pmacssdql %xmm11,%xmm12,%xmm13,%xmm11 + [ ]+f04:[ ]+0f 24 87 a7 b5 00 00 10 00[ ]+pmacssdql %xmm11,%xmm12,0x100000\(%r15\),%xmm11 + [ ]+f0d:[ ]+0f 24 8f e5 b5[ ]+pmacssdqh %xmm11,%xmm12,%xmm13,%xmm11 + [ ]+f12:[ ]+0f 24 8f a7 b5 00 00 10 00[ ]+pmacssdqh %xmm11,%xmm12,0x100000\(%r15\),%xmm11 + [ ]+f1b:[ ]+0f 24 97 e5 b5[ ]+pmacsdql %xmm11,%xmm12,%xmm13,%xmm11 + [ ]+f20:[ ]+0f 24 97 a7 b5 00 00 10 00[ ]+pmacsdql %xmm11,%xmm12,0x100000\(%r15\),%xmm11 + [ ]+f29:[ ]+0f 24 9f e5 b5[ ]+pmacsdqh %xmm11,%xmm12,%xmm13,%xmm11 + [ ]+f2e:[ ]+0f 24 9f a7 b5 00 00 10 00[ ]+pmacsdqh %xmm11,%xmm12,0x100000\(%r15\),%xmm11 + [ ]+f37:[ ]+0f 24 a6 e5 b5[ ]+pmadcsswd %xmm11,%xmm12,%xmm13,%xmm11 + [ ]+f3c:[ ]+0f 24 a6 a7 b5 00 00 10 00[ ]+pmadcsswd %xmm11,%xmm12,0x100000\(%r15\),%xmm11 + [ ]+f45:[ ]+0f 24 b6 e5 b5[ ]+pmadcswd %xmm11,%xmm12,%xmm13,%xmm11 + [ ]+f4a:[ ]+0f 24 b6 a7 b5 00 00 10 00[ ]+pmadcswd %xmm11,%xmm12,0x100000\(%r15\),%xmm11 + [ ]+f53:[ ]+0f 24 85 e3 14[ ]+pmacssww %xmm1,%xmm12,%xmm3,%xmm1 + [ ]+f58:[ ]+0f 24 85 62 14 04[ ]+pmacssww %xmm1,%xmm12,0x4\(%rdx\),%xmm1 + [ ]+f5e:[ ]+0f 24 95 e3 14[ ]+pmacsww %xmm1,%xmm12,%xmm3,%xmm1 + [ ]+f63:[ ]+0f 24 95 62 14 04[ ]+pmacsww %xmm1,%xmm12,0x4\(%rdx\),%xmm1 + [ ]+f69:[ ]+0f 24 96 e3 14[ ]+pmacswd %xmm1,%xmm12,%xmm3,%xmm1 + [ ]+f6e:[ ]+0f 24 96 62 14 04[ ]+pmacswd %xmm1,%xmm12,0x4\(%rdx\),%xmm1 + [ ]+f74:[ ]+0f 24 8e e3 14[ ]+pmacssdd %xmm1,%xmm12,%xmm3,%xmm1 + [ ]+f79:[ ]+0f 24 8e 62 14 04[ ]+pmacssdd %xmm1,%xmm12,0x4\(%rdx\),%xmm1 + [ ]+f7f:[ ]+0f 24 9e e3 14[ ]+pmacsdd %xmm1,%xmm12,%xmm3,%xmm1 + [ ]+f84:[ ]+0f 24 9e 62 14 04[ ]+pmacsdd %xmm1,%xmm12,0x4\(%rdx\),%xmm1 + [ ]+f8a:[ ]+0f 24 87 e3 14[ ]+pmacssdql %xmm1,%xmm12,%xmm3,%xmm1 + [ ]+f8f:[ ]+0f 24 87 62 14 04[ ]+pmacssdql %xmm1,%xmm12,0x4\(%rdx\),%xmm1 + [ ]+f95:[ ]+0f 24 8f e3 14[ ]+pmacssdqh %xmm1,%xmm12,%xmm3,%xmm1 + [ ]+f9a:[ ]+0f 24 8f 62 14 04[ ]+pmacssdqh %xmm1,%xmm12,0x4\(%rdx\),%xmm1 + [ ]+fa0:[ ]+0f 24 97 e3 14[ ]+pmacsdql %xmm1,%xmm12,%xmm3,%xmm1 + [ ]+fa5:[ ]+0f 24 97 62 14 04[ ]+pmacsdql %xmm1,%xmm12,0x4\(%rdx\),%xmm1 + [ ]+fab:[ ]+0f 24 9f e3 14[ ]+pmacsdqh %xmm1,%xmm12,%xmm3,%xmm1 + [ ]+fb0:[ ]+0f 24 9f 62 14 04[ ]+pmacsdqh %xmm1,%xmm12,0x4\(%rdx\),%xmm1 + [ ]+fb6:[ ]+0f 24 a6 e3 14[ ]+pmadcsswd %xmm1,%xmm12,%xmm3,%xmm1 + [ ]+fbb:[ ]+0f 24 a6 62 14 04[ ]+pmadcsswd %xmm1,%xmm12,0x4\(%rdx\),%xmm1 + [ ]+fc1:[ ]+0f 24 b6 e3 14[ ]+pmadcswd %xmm1,%xmm12,%xmm3,%xmm1 + [ ]+fc6:[ ]+0f 24 b6 62 14 04[ ]+pmadcswd %xmm1,%xmm12,0x4\(%rdx\),%xmm1 + [ ]+fcc:[ ]+0f 24 85 d3 b0[ ]+pmacssww %xmm11,%xmm2,%xmm3,%xmm11 + [ ]+fd1:[ ]+0f 24 85 52 b0 04[ ]+pmacssww %xmm11,%xmm2,0x4\(%rdx\),%xmm11 + [ ]+fd7:[ ]+0f 24 95 d3 b0[ ]+pmacsww %xmm11,%xmm2,%xmm3,%xmm11 + [ ]+fdc:[ ]+0f 24 95 52 b0 04[ ]+pmacsww %xmm11,%xmm2,0x4\(%rdx\),%xmm11 + [ ]+fe2:[ ]+0f 24 96 d3 b0[ ]+pmacswd %xmm11,%xmm2,%xmm3,%xmm11 + [ ]+fe7:[ ]+0f 24 96 52 b0 04[ ]+pmacswd %xmm11,%xmm2,0x4\(%rdx\),%xmm11 + [ ]+fed:[ ]+0f 24 8e d3 b0[ ]+pmacssdd %xmm11,%xmm2,%xmm3,%xmm11 + [ ]+ff2:[ ]+0f 24 8e 52 b0 04[ ]+pmacssdd %xmm11,%xmm2,0x4\(%rdx\),%xmm11 + [ ]+ff8:[ ]+0f 24 9e d3 b0[ ]+pmacsdd %xmm11,%xmm2,%xmm3,%xmm11 + [ ]+ffd:[ ]+0f 24 9e 52 b0 04[ ]+pmacsdd %xmm11,%xmm2,0x4\(%rdx\),%xmm11 + [ ]+1003:[ ]+0f 24 87 d3 b0[ ]+pmacssdql %xmm11,%xmm2,%xmm3,%xmm11 + [ ]+1008:[ ]+0f 24 87 52 b0 04[ ]+pmacssdql %xmm11,%xmm2,0x4\(%rdx\),%xmm11 + [ ]+100e:[ ]+0f 24 8f d3 b0[ ]+pmacssdqh %xmm11,%xmm2,%xmm3,%xmm11 + [ ]+1013:[ ]+0f 24 8f 52 b0 04[ ]+pmacssdqh %xmm11,%xmm2,0x4\(%rdx\),%xmm11 + [ ]+1019:[ ]+0f 24 97 d3 b0[ ]+pmacsdql %xmm11,%xmm2,%xmm3,%xmm11 + [ ]+101e:[ ]+0f 24 97 52 b0 04[ ]+pmacsdql %xmm11,%xmm2,0x4\(%rdx\),%xmm11 + [ ]+1024:[ ]+0f 24 9f d3 b0[ ]+pmacsdqh %xmm11,%xmm2,%xmm3,%xmm11 + [ ]+1029:[ ]+0f 24 9f 52 b0 04[ ]+pmacsdqh %xmm11,%xmm2,0x4\(%rdx\),%xmm11 + [ ]+102f:[ ]+0f 24 a6 d3 b0[ ]+pmadcsswd %xmm11,%xmm2,%xmm3,%xmm11 + [ ]+1034:[ ]+0f 24 a6 52 b0 04[ ]+pmadcsswd %xmm11,%xmm2,0x4\(%rdx\),%xmm11 + [ ]+103a:[ ]+0f 24 b6 d3 b0[ ]+pmadcswd %xmm11,%xmm2,%xmm3,%xmm11 + [ ]+103f:[ ]+0f 24 b6 52 b0 04[ ]+pmadcswd %xmm11,%xmm2,0x4\(%rdx\),%xmm11 + [ ]+1045:[ ]+0f 24 85 d5 11[ ]+pmacssww %xmm1,%xmm2,%xmm13,%xmm1 + [ ]+104a:[ ]+0f 24 85 52 10 04[ ]+pmacssww %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+1050:[ ]+0f 24 95 d5 11[ ]+pmacsww %xmm1,%xmm2,%xmm13,%xmm1 + [ ]+1055:[ ]+0f 24 95 52 10 04[ ]+pmacsww %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+105b:[ ]+0f 24 96 d5 11[ ]+pmacswd %xmm1,%xmm2,%xmm13,%xmm1 + [ ]+1060:[ ]+0f 24 96 52 10 04[ ]+pmacswd %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+1066:[ ]+0f 24 8e d5 11[ ]+pmacssdd %xmm1,%xmm2,%xmm13,%xmm1 + [ ]+106b:[ ]+0f 24 8e 52 10 04[ ]+pmacssdd %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+1071:[ ]+0f 24 9e d5 11[ ]+pmacsdd %xmm1,%xmm2,%xmm13,%xmm1 + [ ]+1076:[ ]+0f 24 9e 52 10 04[ ]+pmacsdd %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+107c:[ ]+0f 24 87 d5 11[ ]+pmacssdql %xmm1,%xmm2,%xmm13,%xmm1 + [ ]+1081:[ ]+0f 24 87 52 10 04[ ]+pmacssdql %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+1087:[ ]+0f 24 8f d5 11[ ]+pmacssdqh %xmm1,%xmm2,%xmm13,%xmm1 + [ ]+108c:[ ]+0f 24 8f 52 10 04[ ]+pmacssdqh %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+1092:[ ]+0f 24 97 d5 11[ ]+pmacsdql %xmm1,%xmm2,%xmm13,%xmm1 + [ ]+1097:[ ]+0f 24 97 52 10 04[ ]+pmacsdql %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+109d:[ ]+0f 24 9f d5 11[ ]+pmacsdqh %xmm1,%xmm2,%xmm13,%xmm1 + [ ]+10a2:[ ]+0f 24 9f 52 10 04[ ]+pmacsdqh %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+10a8:[ ]+0f 24 a6 d5 11[ ]+pmadcsswd %xmm1,%xmm2,%xmm13,%xmm1 + [ ]+10ad:[ ]+0f 24 a6 52 10 04[ ]+pmadcsswd %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+10b3:[ ]+0f 24 b6 d5 11[ ]+pmadcswd %xmm1,%xmm2,%xmm13,%xmm1 + [ ]+10b8:[ ]+0f 24 b6 52 10 04[ ]+pmadcswd %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+10be:[ ]+0f 24 85 d3 10[ ]+pmacssww %xmm1,%xmm2,%xmm3,%xmm1 + [ ]+10c3:[ ]+0f 24 85 97 11 00 00 10 00[ ]+pmacssww %xmm1,%xmm2,0x100000\(%r15\),%xmm1 + [ ]+10cc:[ ]+0f 24 95 d3 10[ ]+pmacsww %xmm1,%xmm2,%xmm3,%xmm1 + [ ]+10d1:[ ]+0f 24 95 97 11 00 00 10 00[ ]+pmacsww %xmm1,%xmm2,0x100000\(%r15\),%xmm1 + [ ]+10da:[ ]+0f 24 96 d3 10[ ]+pmacswd %xmm1,%xmm2,%xmm3,%xmm1 + [ ]+10df:[ ]+0f 24 96 97 11 00 00 10 00[ ]+pmacswd %xmm1,%xmm2,0x100000\(%r15\),%xmm1 + [ ]+10e8:[ ]+0f 24 8e d3 10[ ]+pmacssdd %xmm1,%xmm2,%xmm3,%xmm1 + [ ]+10ed:[ ]+0f 24 8e 97 11 00 00 10 00[ ]+pmacssdd %xmm1,%xmm2,0x100000\(%r15\),%xmm1 + [ ]+10f6:[ ]+0f 24 9e d3 10[ ]+pmacsdd %xmm1,%xmm2,%xmm3,%xmm1 + [ ]+10fb:[ ]+0f 24 9e 97 11 00 00 10 00[ ]+pmacsdd %xmm1,%xmm2,0x100000\(%r15\),%xmm1 + [ ]+1104:[ ]+0f 24 87 d3 10[ ]+pmacssdql %xmm1,%xmm2,%xmm3,%xmm1 + [ ]+1109:[ ]+0f 24 87 97 11 00 00 10 00[ ]+pmacssdql %xmm1,%xmm2,0x100000\(%r15\),%xmm1 + [ ]+1112:[ ]+0f 24 8f d3 10[ ]+pmacssdqh %xmm1,%xmm2,%xmm3,%xmm1 + [ ]+1117:[ ]+0f 24 8f 97 11 00 00 10 00[ ]+pmacssdqh %xmm1,%xmm2,0x100000\(%r15\),%xmm1 + [ ]+1120:[ ]+0f 24 97 d3 10[ ]+pmacsdql %xmm1,%xmm2,%xmm3,%xmm1 + [ ]+1125:[ ]+0f 24 97 97 11 00 00 10 00[ ]+pmacsdql %xmm1,%xmm2,0x100000\(%r15\),%xmm1 + [ ]+112e:[ ]+0f 24 9f d3 10[ ]+pmacsdqh %xmm1,%xmm2,%xmm3,%xmm1 + [ ]+1133:[ ]+0f 24 9f 97 11 00 00 10 00[ ]+pmacsdqh %xmm1,%xmm2,0x100000\(%r15\),%xmm1 + [ ]+113c:[ ]+0f 24 a6 d3 10[ ]+pmadcsswd %xmm1,%xmm2,%xmm3,%xmm1 + [ ]+1141:[ ]+0f 24 a6 97 11 00 00 10 00[ ]+pmadcsswd %xmm1,%xmm2,0x100000\(%r15\),%xmm1 + [ ]+114a:[ ]+0f 24 b6 d3 10[ ]+pmadcswd %xmm1,%xmm2,%xmm3,%xmm1 + [ ]+114f:[ ]+0f 24 b6 97 11 00 00 10 00[ ]+pmadcswd %xmm1,%xmm2,0x100000\(%r15\),%xmm1 + [ ]+1158:[ ]+0f 7a 41 ca[ ]+phaddbw %xmm2,%xmm1 + [ ]+115c:[ ]+0f 7a 41 4a 04[ ]+phaddbw 0x4\(%rdx\),%xmm1 + [ ]+1161:[ ]+0f 7a 42 ca[ ]+phaddbd %xmm2,%xmm1 + [ ]+1165:[ ]+0f 7a 42 4a 04[ ]+phaddbd 0x4\(%rdx\),%xmm1 + [ ]+116a:[ ]+0f 7a 43 ca[ ]+phaddbq %xmm2,%xmm1 + [ ]+116e:[ ]+0f 7a 43 4a 04[ ]+phaddbq 0x4\(%rdx\),%xmm1 + [ ]+1173:[ ]+0f 7a 46 ca[ ]+phaddwd %xmm2,%xmm1 + [ ]+1177:[ ]+0f 7a 46 4a 04[ ]+phaddwd 0x4\(%rdx\),%xmm1 + [ ]+117c:[ ]+0f 7a 47 ca[ ]+phaddwq %xmm2,%xmm1 + [ ]+1180:[ ]+0f 7a 47 4a 04[ ]+phaddwq 0x4\(%rdx\),%xmm1 + [ ]+1185:[ ]+0f 7a 4b ca[ ]+phadddq %xmm2,%xmm1 + [ ]+1189:[ ]+0f 7a 4b 4a 04[ ]+phadddq 0x4\(%rdx\),%xmm1 + [ ]+118e:[ ]+0f 7a 51 ca[ ]+phaddubw %xmm2,%xmm1 + [ ]+1192:[ ]+0f 7a 51 4a 04[ ]+phaddubw 0x4\(%rdx\),%xmm1 + [ ]+1197:[ ]+0f 7a 52 ca[ ]+phaddubd %xmm2,%xmm1 + [ ]+119b:[ ]+0f 7a 52 4a 04[ ]+phaddubd 0x4\(%rdx\),%xmm1 + [ ]+11a0:[ ]+0f 7a 53 ca[ ]+phaddubq %xmm2,%xmm1 + [ ]+11a4:[ ]+0f 7a 53 4a 04[ ]+phaddubq 0x4\(%rdx\),%xmm1 + [ ]+11a9:[ ]+0f 7a 56 ca[ ]+phadduwd %xmm2,%xmm1 + [ ]+11ad:[ ]+0f 7a 56 4a 04[ ]+phadduwd 0x4\(%rdx\),%xmm1 + [ ]+11b2:[ ]+0f 7a 57 ca[ ]+phadduwq %xmm2,%xmm1 + [ ]+11b6:[ ]+0f 7a 57 4a 04[ ]+phadduwq 0x4\(%rdx\),%xmm1 + [ ]+11bb:[ ]+0f 7a 5b ca[ ]+phaddudq %xmm2,%xmm1 + [ ]+11bf:[ ]+0f 7a 5b 4a 04[ ]+phaddudq 0x4\(%rdx\),%xmm1 + [ ]+11c4:[ ]+0f 7a 61 ca[ ]+phsubbw %xmm2,%xmm1 + [ ]+11c8:[ ]+0f 7a 61 4a 04[ ]+phsubbw 0x4\(%rdx\),%xmm1 + [ ]+11cd:[ ]+0f 7a 62 ca[ ]+phsubbd %xmm2,%xmm1 + [ ]+11d1:[ ]+0f 7a 62 4a 04[ ]+phsubbd 0x4\(%rdx\),%xmm1 + [ ]+11d6:[ ]+0f 7a 63 ca[ ]+phsubbq %xmm2,%xmm1 + [ ]+11da:[ ]+0f 7a 63 4a 04[ ]+phsubbq 0x4\(%rdx\),%xmm1 + [ ]+11df:[ ]+45 0f 7a 41 dc[ ]+phaddbw %xmm12,%xmm11 + [ ]+11e4:[ ]+45 0f 7a 41 9f 00 00 10 00[ ]+phaddbw 0x100000\(%r15\),%xmm11 + [ ]+11ed:[ ]+45 0f 7a 42 dc[ ]+phaddbd %xmm12,%xmm11 + [ ]+11f2:[ ]+45 0f 7a 42 9f 00 00 10 00[ ]+phaddbd 0x100000\(%r15\),%xmm11 + [ ]+11fb:[ ]+45 0f 7a 43 dc[ ]+phaddbq %xmm12,%xmm11 + [ ]+1200:[ ]+45 0f 7a 43 9f 00 00 10 00[ ]+phaddbq 0x100000\(%r15\),%xmm11 + [ ]+1209:[ ]+45 0f 7a 46 dc[ ]+phaddwd %xmm12,%xmm11 + [ ]+120e:[ ]+45 0f 7a 46 9f 00 00 10 00[ ]+phaddwd 0x100000\(%r15\),%xmm11 + [ ]+1217:[ ]+45 0f 7a 47 dc[ ]+phaddwq %xmm12,%xmm11 + [ ]+121c:[ ]+45 0f 7a 47 9f 00 00 10 00[ ]+phaddwq 0x100000\(%r15\),%xmm11 + [ ]+1225:[ ]+45 0f 7a 4b dc[ ]+phadddq %xmm12,%xmm11 + [ ]+122a:[ ]+45 0f 7a 4b 9f 00 00 10 00[ ]+phadddq 0x100000\(%r15\),%xmm11 + [ ]+1233:[ ]+45 0f 7a 51 dc[ ]+phaddubw %xmm12,%xmm11 + [ ]+1238:[ ]+45 0f 7a 51 9f 00 00 10 00[ ]+phaddubw 0x100000\(%r15\),%xmm11 + [ ]+1241:[ ]+45 0f 7a 52 dc[ ]+phaddubd %xmm12,%xmm11 + [ ]+1246:[ ]+45 0f 7a 52 9f 00 00 10 00[ ]+phaddubd 0x100000\(%r15\),%xmm11 + [ ]+124f:[ ]+45 0f 7a 53 dc[ ]+phaddubq %xmm12,%xmm11 + [ ]+1254:[ ]+45 0f 7a 53 9f 00 00 10 00[ ]+phaddubq 0x100000\(%r15\),%xmm11 + [ ]+125d:[ ]+45 0f 7a 56 dc[ ]+phadduwd %xmm12,%xmm11 + [ ]+1262:[ ]+45 0f 7a 56 9f 00 00 10 00[ ]+phadduwd 0x100000\(%r15\),%xmm11 + [ ]+126b:[ ]+45 0f 7a 57 dc[ ]+phadduwq %xmm12,%xmm11 + [ ]+1270:[ ]+45 0f 7a 57 9f 00 00 10 00[ ]+phadduwq 0x100000\(%r15\),%xmm11 + [ ]+1279:[ ]+45 0f 7a 5b dc[ ]+phaddudq %xmm12,%xmm11 + [ ]+127e:[ ]+45 0f 7a 5b 9f 00 00 10 00[ ]+phaddudq 0x100000\(%r15\),%xmm11 + [ ]+1287:[ ]+45 0f 7a 61 dc[ ]+phsubbw %xmm12,%xmm11 + [ ]+128c:[ ]+45 0f 7a 61 9f 00 00 10 00[ ]+phsubbw 0x100000\(%r15\),%xmm11 + [ ]+1295:[ ]+45 0f 7a 62 dc[ ]+phsubbd %xmm12,%xmm11 + [ ]+129a:[ ]+45 0f 7a 62 9f 00 00 10 00[ ]+phsubbd 0x100000\(%r15\),%xmm11 + [ ]+12a3:[ ]+45 0f 7a 63 dc[ ]+phsubbq %xmm12,%xmm11 + [ ]+12a8:[ ]+45 0f 7a 63 9f 00 00 10 00[ ]+phsubbq 0x100000\(%r15\),%xmm11 + [ ]+12b1:[ ]+41 0f 7a 41 cc[ ]+phaddbw %xmm12,%xmm1 + [ ]+12b6:[ ]+0f 7a 41 4a 04[ ]+phaddbw 0x4\(%rdx\),%xmm1 + [ ]+12bb:[ ]+41 0f 7a 42 cc[ ]+phaddbd %xmm12,%xmm1 + [ ]+12c0:[ ]+0f 7a 42 4a 04[ ]+phaddbd 0x4\(%rdx\),%xmm1 + [ ]+12c5:[ ]+41 0f 7a 43 cc[ ]+phaddbq %xmm12,%xmm1 + [ ]+12ca:[ ]+0f 7a 43 4a 04[ ]+phaddbq 0x4\(%rdx\),%xmm1 + [ ]+12cf:[ ]+41 0f 7a 46 cc[ ]+phaddwd %xmm12,%xmm1 + [ ]+12d4:[ ]+0f 7a 46 4a 04[ ]+phaddwd 0x4\(%rdx\),%xmm1 + [ ]+12d9:[ ]+41 0f 7a 47 cc[ ]+phaddwq %xmm12,%xmm1 + [ ]+12de:[ ]+0f 7a 47 4a 04[ ]+phaddwq 0x4\(%rdx\),%xmm1 + [ ]+12e3:[ ]+41 0f 7a 4b cc[ ]+phadddq %xmm12,%xmm1 + [ ]+12e8:[ ]+0f 7a 4b 4a 04[ ]+phadddq 0x4\(%rdx\),%xmm1 + [ ]+12ed:[ ]+41 0f 7a 51 cc[ ]+phaddubw %xmm12,%xmm1 + [ ]+12f2:[ ]+0f 7a 51 4a 04[ ]+phaddubw 0x4\(%rdx\),%xmm1 + [ ]+12f7:[ ]+41 0f 7a 52 cc[ ]+phaddubd %xmm12,%xmm1 + [ ]+12fc:[ ]+0f 7a 52 4a 04[ ]+phaddubd 0x4\(%rdx\),%xmm1 + [ ]+1301:[ ]+41 0f 7a 53 cc[ ]+phaddubq %xmm12,%xmm1 + [ ]+1306:[ ]+0f 7a 53 4a 04[ ]+phaddubq 0x4\(%rdx\),%xmm1 + [ ]+130b:[ ]+41 0f 7a 56 cc[ ]+phadduwd %xmm12,%xmm1 + [ ]+1310:[ ]+0f 7a 56 4a 04[ ]+phadduwd 0x4\(%rdx\),%xmm1 + [ ]+1315:[ ]+41 0f 7a 57 cc[ ]+phadduwq %xmm12,%xmm1 + [ ]+131a:[ ]+0f 7a 57 4a 04[ ]+phadduwq 0x4\(%rdx\),%xmm1 + [ ]+131f:[ ]+41 0f 7a 5b cc[ ]+phaddudq %xmm12,%xmm1 + [ ]+1324:[ ]+0f 7a 5b 4a 04[ ]+phaddudq 0x4\(%rdx\),%xmm1 + [ ]+1329:[ ]+41 0f 7a 61 cc[ ]+phsubbw %xmm12,%xmm1 + [ ]+132e:[ ]+0f 7a 61 4a 04[ ]+phsubbw 0x4\(%rdx\),%xmm1 + [ ]+1333:[ ]+41 0f 7a 62 cc[ ]+phsubbd %xmm12,%xmm1 + [ ]+1338:[ ]+0f 7a 62 4a 04[ ]+phsubbd 0x4\(%rdx\),%xmm1 + [ ]+133d:[ ]+41 0f 7a 63 cc[ ]+phsubbq %xmm12,%xmm1 + [ ]+1342:[ ]+0f 7a 63 4a 04[ ]+phsubbq 0x4\(%rdx\),%xmm1 + [ ]+1347:[ ]+44 0f 7a 41 da[ ]+phaddbw %xmm2,%xmm11 + [ ]+134c:[ ]+44 0f 7a 41 5a 04[ ]+phaddbw 0x4\(%rdx\),%xmm11 + [ ]+1352:[ ]+44 0f 7a 42 da[ ]+phaddbd %xmm2,%xmm11 + [ ]+1357:[ ]+44 0f 7a 42 5a 04[ ]+phaddbd 0x4\(%rdx\),%xmm11 + [ ]+135d:[ ]+44 0f 7a 43 da[ ]+phaddbq %xmm2,%xmm11 + [ ]+1362:[ ]+44 0f 7a 43 5a 04[ ]+phaddbq 0x4\(%rdx\),%xmm11 + [ ]+1368:[ ]+44 0f 7a 46 da[ ]+phaddwd %xmm2,%xmm11 + [ ]+136d:[ ]+44 0f 7a 46 5a 04[ ]+phaddwd 0x4\(%rdx\),%xmm11 + [ ]+1373:[ ]+44 0f 7a 47 da[ ]+phaddwq %xmm2,%xmm11 + [ ]+1378:[ ]+44 0f 7a 47 5a 04[ ]+phaddwq 0x4\(%rdx\),%xmm11 + [ ]+137e:[ ]+44 0f 7a 4b da[ ]+phadddq %xmm2,%xmm11 + [ ]+1383:[ ]+44 0f 7a 4b 5a 04[ ]+phadddq 0x4\(%rdx\),%xmm11 + [ ]+1389:[ ]+44 0f 7a 51 da[ ]+phaddubw %xmm2,%xmm11 + [ ]+138e:[ ]+44 0f 7a 51 5a 04[ ]+phaddubw 0x4\(%rdx\),%xmm11 + [ ]+1394:[ ]+44 0f 7a 52 da[ ]+phaddubd %xmm2,%xmm11 + [ ]+1399:[ ]+44 0f 7a 52 5a 04[ ]+phaddubd 0x4\(%rdx\),%xmm11 + [ ]+139f:[ ]+44 0f 7a 53 da[ ]+phaddubq %xmm2,%xmm11 + [ ]+13a4:[ ]+44 0f 7a 53 5a 04[ ]+phaddubq 0x4\(%rdx\),%xmm11 + [ ]+13aa:[ ]+44 0f 7a 56 da[ ]+phadduwd %xmm2,%xmm11 + [ ]+13af:[ ]+44 0f 7a 56 5a 04[ ]+phadduwd 0x4\(%rdx\),%xmm11 + [ ]+13b5:[ ]+44 0f 7a 57 da[ ]+phadduwq %xmm2,%xmm11 + [ ]+13ba:[ ]+44 0f 7a 57 5a 04[ ]+phadduwq 0x4\(%rdx\),%xmm11 + [ ]+13c0:[ ]+44 0f 7a 5b da[ ]+phaddudq %xmm2,%xmm11 + [ ]+13c5:[ ]+44 0f 7a 5b 5a 04[ ]+phaddudq 0x4\(%rdx\),%xmm11 + [ ]+13cb:[ ]+44 0f 7a 61 da[ ]+phsubbw %xmm2,%xmm11 + [ ]+13d0:[ ]+44 0f 7a 61 5a 04[ ]+phsubbw 0x4\(%rdx\),%xmm11 + [ ]+13d6:[ ]+44 0f 7a 62 da[ ]+phsubbd %xmm2,%xmm11 + [ ]+13db:[ ]+44 0f 7a 62 5a 04[ ]+phsubbd 0x4\(%rdx\),%xmm11 + [ ]+13e1:[ ]+44 0f 7a 63 da[ ]+phsubbq %xmm2,%xmm11 + [ ]+13e6:[ ]+44 0f 7a 63 5a 04[ ]+phsubbq 0x4\(%rdx\),%xmm11 + [ ]+13ec:[ ]+0f 7a 41 ca[ ]+phaddbw %xmm2,%xmm1 + [ ]+13f0:[ ]+0f 7a 41 4a 04[ ]+phaddbw 0x4\(%rdx\),%xmm1 + [ ]+13f5:[ ]+0f 7a 42 ca[ ]+phaddbd %xmm2,%xmm1 + [ ]+13f9:[ ]+0f 7a 42 4a 04[ ]+phaddbd 0x4\(%rdx\),%xmm1 + [ ]+13fe:[ ]+0f 7a 43 ca[ ]+phaddbq %xmm2,%xmm1 + [ ]+1402:[ ]+0f 7a 43 4a 04[ ]+phaddbq 0x4\(%rdx\),%xmm1 + [ ]+1407:[ ]+0f 7a 46 ca[ ]+phaddwd %xmm2,%xmm1 + [ ]+140b:[ ]+0f 7a 46 4a 04[ ]+phaddwd 0x4\(%rdx\),%xmm1 + [ ]+1410:[ ]+0f 7a 47 ca[ ]+phaddwq %xmm2,%xmm1 + [ ]+1414:[ ]+0f 7a 47 4a 04[ ]+phaddwq 0x4\(%rdx\),%xmm1 + [ ]+1419:[ ]+0f 7a 4b ca[ ]+phadddq %xmm2,%xmm1 + [ ]+141d:[ ]+0f 7a 4b 4a 04[ ]+phadddq 0x4\(%rdx\),%xmm1 + [ ]+1422:[ ]+0f 7a 51 ca[ ]+phaddubw %xmm2,%xmm1 + [ ]+1426:[ ]+0f 7a 51 4a 04[ ]+phaddubw 0x4\(%rdx\),%xmm1 + [ ]+142b:[ ]+0f 7a 52 ca[ ]+phaddubd %xmm2,%xmm1 + [ ]+142f:[ ]+0f 7a 52 4a 04[ ]+phaddubd 0x4\(%rdx\),%xmm1 + [ ]+1434:[ ]+0f 7a 53 ca[ ]+phaddubq %xmm2,%xmm1 + [ ]+1438:[ ]+0f 7a 53 4a 04[ ]+phaddubq 0x4\(%rdx\),%xmm1 + [ ]+143d:[ ]+0f 7a 56 ca[ ]+phadduwd %xmm2,%xmm1 + [ ]+1441:[ ]+0f 7a 56 4a 04[ ]+phadduwd 0x4\(%rdx\),%xmm1 + [ ]+1446:[ ]+0f 7a 57 ca[ ]+phadduwq %xmm2,%xmm1 + [ ]+144a:[ ]+0f 7a 57 4a 04[ ]+phadduwq 0x4\(%rdx\),%xmm1 + [ ]+144f:[ ]+0f 7a 5b ca[ ]+phaddudq %xmm2,%xmm1 + [ ]+1453:[ ]+0f 7a 5b 4a 04[ ]+phaddudq 0x4\(%rdx\),%xmm1 + [ ]+1458:[ ]+0f 7a 61 ca[ ]+phsubbw %xmm2,%xmm1 + [ ]+145c:[ ]+0f 7a 61 4a 04[ ]+phsubbw 0x4\(%rdx\),%xmm1 + [ ]+1461:[ ]+0f 7a 62 ca[ ]+phsubbd %xmm2,%xmm1 + [ ]+1465:[ ]+0f 7a 62 4a 04[ ]+phsubbd 0x4\(%rdx\),%xmm1 + [ ]+146a:[ ]+0f 7a 63 ca[ ]+phsubbq %xmm2,%xmm1 + [ ]+146e:[ ]+0f 7a 63 4a 04[ ]+phsubbq 0x4\(%rdx\),%xmm1 + [ ]+1473:[ ]+0f 7a 41 ca[ ]+phaddbw %xmm2,%xmm1 + [ ]+1477:[ ]+41 0f 7a 41 8f 00 00 10 00[ ]+phaddbw 0x100000\(%r15\),%xmm1 + [ ]+1480:[ ]+0f 7a 42 ca[ ]+phaddbd %xmm2,%xmm1 + [ ]+1484:[ ]+41 0f 7a 42 8f 00 00 10 00[ ]+phaddbd 0x100000\(%r15\),%xmm1 + [ ]+148d:[ ]+0f 7a 43 ca[ ]+phaddbq %xmm2,%xmm1 + [ ]+1491:[ ]+41 0f 7a 43 8f 00 00 10 00[ ]+phaddbq 0x100000\(%r15\),%xmm1 + [ ]+149a:[ ]+0f 7a 46 ca[ ]+phaddwd %xmm2,%xmm1 + [ ]+149e:[ ]+41 0f 7a 46 8f 00 00 10 00[ ]+phaddwd 0x100000\(%r15\),%xmm1 + [ ]+14a7:[ ]+0f 7a 47 ca[ ]+phaddwq %xmm2,%xmm1 + [ ]+14ab:[ ]+41 0f 7a 47 8f 00 00 10 00[ ]+phaddwq 0x100000\(%r15\),%xmm1 + [ ]+14b4:[ ]+0f 7a 4b ca[ ]+phadddq %xmm2,%xmm1 + [ ]+14b8:[ ]+41 0f 7a 4b 8f 00 00 10 00[ ]+phadddq 0x100000\(%r15\),%xmm1 + [ ]+14c1:[ ]+0f 7a 51 ca[ ]+phaddubw %xmm2,%xmm1 + [ ]+14c5:[ ]+41 0f 7a 51 8f 00 00 10 00[ ]+phaddubw 0x100000\(%r15\),%xmm1 + [ ]+14ce:[ ]+0f 7a 52 ca[ ]+phaddubd %xmm2,%xmm1 + [ ]+14d2:[ ]+41 0f 7a 52 8f 00 00 10 00[ ]+phaddubd 0x100000\(%r15\),%xmm1 + [ ]+14db:[ ]+0f 7a 53 ca[ ]+phaddubq %xmm2,%xmm1 + [ ]+14df:[ ]+41 0f 7a 53 8f 00 00 10 00[ ]+phaddubq 0x100000\(%r15\),%xmm1 + [ ]+14e8:[ ]+0f 7a 56 ca[ ]+phadduwd %xmm2,%xmm1 + [ ]+14ec:[ ]+41 0f 7a 56 8f 00 00 10 00[ ]+phadduwd 0x100000\(%r15\),%xmm1 + [ ]+14f5:[ ]+0f 7a 57 ca[ ]+phadduwq %xmm2,%xmm1 + [ ]+14f9:[ ]+41 0f 7a 57 8f 00 00 10 00[ ]+phadduwq 0x100000\(%r15\),%xmm1 + [ ]+1502:[ ]+0f 7a 5b ca[ ]+phaddudq %xmm2,%xmm1 + [ ]+1506:[ ]+41 0f 7a 5b 8f 00 00 10 00[ ]+phaddudq 0x100000\(%r15\),%xmm1 + [ ]+150f:[ ]+0f 7a 61 ca[ ]+phsubbw %xmm2,%xmm1 + [ ]+1513:[ ]+41 0f 7a 61 8f 00 00 10 00[ ]+phsubbw 0x100000\(%r15\),%xmm1 + [ ]+151c:[ ]+0f 7a 62 ca[ ]+phsubbd %xmm2,%xmm1 + [ ]+1520:[ ]+41 0f 7a 62 8f 00 00 10 00[ ]+phsubbd 0x100000\(%r15\),%xmm1 + [ ]+1529:[ ]+0f 7a 63 ca[ ]+phsubbq %xmm2,%xmm1 + [ ]+152d:[ ]+41 0f 7a 63 8f 00 00 10 00[ ]+phsubbq 0x100000\(%r15\),%xmm1 + [ ]+1536:[ ]+0f 24 22 d3 10[ ]+pcmov[ ]+%xmm3,%xmm2,%xmm1,%xmm1 + [ ]+153b:[ ]+0f 24 22 52 10 04[ ]+pcmov[ ]+0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+1541:[ ]+0f 24 22 52 18 04[ ]+pcmov[ ]+%xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+1547:[ ]+0f 24 26 d3 10[ ]+pcmov[ ]+%xmm1,%xmm3,%xmm2,%xmm1 + [ ]+154c:[ ]+0f 24 26 52 10 04[ ]+pcmov[ ]+%xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1552:[ ]+0f 24 26 52 18 04[ ]+pcmov[ ]+%xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+1558:[ ]+0f 24 23 d3 10[ ]+pperm[ ]+%xmm3,%xmm2,%xmm1,%xmm1 + [ ]+155d:[ ]+0f 24 23 52 10 04[ ]+pperm[ ]+0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+1563:[ ]+0f 24 23 52 18 04[ ]+pperm[ ]+%xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+1569:[ ]+0f 24 27 d3 10[ ]+pperm[ ]+%xmm1,%xmm3,%xmm2,%xmm1 + [ ]+156e:[ ]+0f 24 27 52 10 04[ ]+pperm[ ]+%xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1574:[ ]+0f 24 27 52 18 04[ ]+pperm[ ]+%xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+157a:[ ]+0f 24 20 d3 10[ ]+permps %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+157f:[ ]+0f 24 20 52 10 04[ ]+permps 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+1585:[ ]+0f 24 20 52 18 04[ ]+permps %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+158b:[ ]+0f 24 24 d3 10[ ]+permps %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+1590:[ ]+0f 24 24 52 10 04[ ]+permps %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1596:[ ]+0f 24 24 52 18 04[ ]+permps %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+159c:[ ]+0f 24 21 d3 10[ ]+permpd %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+15a1:[ ]+0f 24 21 52 10 04[ ]+permpd 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+15a7:[ ]+0f 24 21 52 18 04[ ]+permpd %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+15ad:[ ]+0f 24 25 d3 10[ ]+permpd %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+15b2:[ ]+0f 24 25 52 10 04[ ]+permpd %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+15b8:[ ]+0f 24 25 52 18 04[ ]+permpd %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+15be:[ ]+0f 24 22 e5 b5[ ]+pcmov[ ]+%xmm13,%xmm12,%xmm11,%xmm11 + [ ]+15c3:[ ]+0f 24 22 a7 b5 00 00 10 00[ ]+pcmov[ ]+0x100000\(%r15\),%xmm12,%xmm11,%xmm11 + [ ]+15cc:[ ]+0f 24 22 a7 bd 00 00 10 00[ ]+pcmov[ ]+%xmm12,0x100000\(%r15\),%xmm11,%xmm11 + [ ]+15d5:[ ]+0f 24 26 e5 b5[ ]+pcmov[ ]+%xmm11,%xmm13,%xmm12,%xmm11 + [ ]+15da:[ ]+0f 24 26 a7 b5 00 00 10 00[ ]+pcmov[ ]+%xmm11,0x100000\(%r15\),%xmm12,%xmm11 + [ ]+15e3:[ ]+0f 24 26 a7 bd 00 00 10 00[ ]+pcmov[ ]+%xmm11,%xmm12,0x100000\(%r15\),%xmm11 + [ ]+15ec:[ ]+0f 24 23 e5 b5[ ]+pperm[ ]+%xmm13,%xmm12,%xmm11,%xmm11 + [ ]+15f1:[ ]+0f 24 23 a7 b5 00 00 10 00[ ]+pperm[ ]+0x100000\(%r15\),%xmm12,%xmm11,%xmm11 + [ ]+15fa:[ ]+0f 24 23 a7 bd 00 00 10 00[ ]+pperm[ ]+%xmm12,0x100000\(%r15\),%xmm11,%xmm11 + [ ]+1603:[ ]+0f 24 27 e5 b5[ ]+pperm[ ]+%xmm11,%xmm13,%xmm12,%xmm11 + [ ]+1608:[ ]+0f 24 27 a7 b5 00 00 10 00[ ]+pperm[ ]+%xmm11,0x100000\(%r15\),%xmm12,%xmm11 + [ ]+1611:[ ]+0f 24 27 a7 bd 00 00 10 00[ ]+pperm[ ]+%xmm11,%xmm12,0x100000\(%r15\),%xmm11 + [ ]+161a:[ ]+0f 24 20 e5 b5[ ]+permps %xmm13,%xmm12,%xmm11,%xmm11 + [ ]+161f:[ ]+0f 24 20 a7 b5 00 00 10 00[ ]+permps 0x100000\(%r15\),%xmm12,%xmm11,%xmm11 + [ ]+1628:[ ]+0f 24 20 a7 bd 00 00 10 00[ ]+permps %xmm12,0x100000\(%r15\),%xmm11,%xmm11 + [ ]+1631:[ ]+0f 24 24 e5 b5[ ]+permps %xmm11,%xmm13,%xmm12,%xmm11 + [ ]+1636:[ ]+0f 24 24 a7 b5 00 00 10 00[ ]+permps %xmm11,0x100000\(%r15\),%xmm12,%xmm11 + [ ]+163f:[ ]+0f 24 24 a7 bd 00 00 10 00[ ]+permps %xmm11,%xmm12,0x100000\(%r15\),%xmm11 + [ ]+1648:[ ]+0f 24 21 e5 b5[ ]+permpd %xmm13,%xmm12,%xmm11,%xmm11 + [ ]+164d:[ ]+0f 24 21 a7 b5 00 00 10 00[ ]+permpd 0x100000\(%r15\),%xmm12,%xmm11,%xmm11 + [ ]+1656:[ ]+0f 24 21 a7 bd 00 00 10 00[ ]+permpd %xmm12,0x100000\(%r15\),%xmm11,%xmm11 + [ ]+165f:[ ]+0f 24 25 e5 b5[ ]+permpd %xmm11,%xmm13,%xmm12,%xmm11 + [ ]+1664:[ ]+0f 24 25 a7 b5 00 00 10 00[ ]+permpd %xmm11,0x100000\(%r15\),%xmm12,%xmm11 + [ ]+166d:[ ]+0f 24 25 a7 bd 00 00 10 00[ ]+permpd %xmm11,%xmm12,0x100000\(%r15\),%xmm11 + [ ]+1676:[ ]+0f 24 22 e3 14[ ]+pcmov[ ]+%xmm3,%xmm12,%xmm1,%xmm1 + [ ]+167b:[ ]+0f 24 22 62 14 04[ ]+pcmov[ ]+0x4\(%rdx\),%xmm12,%xmm1,%xmm1 + [ ]+1681:[ ]+0f 24 22 62 1c 04[ ]+pcmov[ ]+%xmm12,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+1687:[ ]+0f 24 26 e3 14[ ]+pcmov[ ]+%xmm1,%xmm3,%xmm12,%xmm1 + [ ]+168c:[ ]+0f 24 26 62 14 04[ ]+pcmov[ ]+%xmm1,0x4\(%rdx\),%xmm12,%xmm1 + [ ]+1692:[ ]+0f 24 26 62 1c 04[ ]+pcmov[ ]+%xmm1,%xmm12,0x4\(%rdx\),%xmm1 + [ ]+1698:[ ]+0f 24 23 e3 14[ ]+pperm[ ]+%xmm3,%xmm12,%xmm1,%xmm1 + [ ]+169d:[ ]+0f 24 23 62 14 04[ ]+pperm[ ]+0x4\(%rdx\),%xmm12,%xmm1,%xmm1 + [ ]+16a3:[ ]+0f 24 23 62 1c 04[ ]+pperm[ ]+%xmm12,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+16a9:[ ]+0f 24 27 e3 14[ ]+pperm[ ]+%xmm1,%xmm3,%xmm12,%xmm1 + [ ]+16ae:[ ]+0f 24 27 62 14 04[ ]+pperm[ ]+%xmm1,0x4\(%rdx\),%xmm12,%xmm1 + [ ]+16b4:[ ]+0f 24 27 62 1c 04[ ]+pperm[ ]+%xmm1,%xmm12,0x4\(%rdx\),%xmm1 + [ ]+16ba:[ ]+0f 24 20 e3 14[ ]+permps %xmm3,%xmm12,%xmm1,%xmm1 + [ ]+16bf:[ ]+0f 24 20 62 14 04[ ]+permps 0x4\(%rdx\),%xmm12,%xmm1,%xmm1 + [ ]+16c5:[ ]+0f 24 20 62 1c 04[ ]+permps %xmm12,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+16cb:[ ]+0f 24 24 e3 14[ ]+permps %xmm1,%xmm3,%xmm12,%xmm1 + [ ]+16d0:[ ]+0f 24 24 62 14 04[ ]+permps %xmm1,0x4\(%rdx\),%xmm12,%xmm1 + [ ]+16d6:[ ]+0f 24 24 62 1c 04[ ]+permps %xmm1,%xmm12,0x4\(%rdx\),%xmm1 + [ ]+16dc:[ ]+0f 24 21 e3 14[ ]+permpd %xmm3,%xmm12,%xmm1,%xmm1 + [ ]+16e1:[ ]+0f 24 21 62 14 04[ ]+permpd 0x4\(%rdx\),%xmm12,%xmm1,%xmm1 + [ ]+16e7:[ ]+0f 24 21 62 1c 04[ ]+permpd %xmm12,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+16ed:[ ]+0f 24 25 e3 14[ ]+permpd %xmm1,%xmm3,%xmm12,%xmm1 + [ ]+16f2:[ ]+0f 24 25 62 14 04[ ]+permpd %xmm1,0x4\(%rdx\),%xmm12,%xmm1 + [ ]+16f8:[ ]+0f 24 25 62 1c 04[ ]+permpd %xmm1,%xmm12,0x4\(%rdx\),%xmm1 + [ ]+16fe:[ ]+0f 24 22 d3 b0[ ]+pcmov[ ]+%xmm3,%xmm2,%xmm11,%xmm11 + [ ]+1703:[ ]+0f 24 22 52 b0 04[ ]+pcmov[ ]+0x4\(%rdx\),%xmm2,%xmm11,%xmm11 + [ ]+1709:[ ]+0f 24 22 52 b8 04[ ]+pcmov[ ]+%xmm2,0x4\(%rdx\),%xmm11,%xmm11 + [ ]+170f:[ ]+0f 24 26 d3 b0[ ]+pcmov[ ]+%xmm11,%xmm3,%xmm2,%xmm11 + [ ]+1714:[ ]+0f 24 26 52 b0 04[ ]+pcmov[ ]+%xmm11,0x4\(%rdx\),%xmm2,%xmm11 + [ ]+171a:[ ]+0f 24 26 52 b8 04[ ]+pcmov[ ]+%xmm11,%xmm2,0x4\(%rdx\),%xmm11 + [ ]+1720:[ ]+0f 24 23 d3 b0[ ]+pperm[ ]+%xmm3,%xmm2,%xmm11,%xmm11 + [ ]+1725:[ ]+0f 24 23 52 b0 04[ ]+pperm[ ]+0x4\(%rdx\),%xmm2,%xmm11,%xmm11 + [ ]+172b:[ ]+0f 24 23 52 b8 04[ ]+pperm[ ]+%xmm2,0x4\(%rdx\),%xmm11,%xmm11 + [ ]+1731:[ ]+0f 24 27 d3 b0[ ]+pperm[ ]+%xmm11,%xmm3,%xmm2,%xmm11 + [ ]+1736:[ ]+0f 24 27 52 b0 04[ ]+pperm[ ]+%xmm11,0x4\(%rdx\),%xmm2,%xmm11 + [ ]+173c:[ ]+0f 24 27 52 b8 04[ ]+pperm[ ]+%xmm11,%xmm2,0x4\(%rdx\),%xmm11 + [ ]+1742:[ ]+0f 24 20 d3 b0[ ]+permps %xmm3,%xmm2,%xmm11,%xmm11 + [ ]+1747:[ ]+0f 24 20 52 b0 04[ ]+permps 0x4\(%rdx\),%xmm2,%xmm11,%xmm11 + [ ]+174d:[ ]+0f 24 20 52 b8 04[ ]+permps %xmm2,0x4\(%rdx\),%xmm11,%xmm11 + [ ]+1753:[ ]+0f 24 24 d3 b0[ ]+permps %xmm11,%xmm3,%xmm2,%xmm11 + [ ]+1758:[ ]+0f 24 24 52 b0 04[ ]+permps %xmm11,0x4\(%rdx\),%xmm2,%xmm11 + [ ]+175e:[ ]+0f 24 24 52 b8 04[ ]+permps %xmm11,%xmm2,0x4\(%rdx\),%xmm11 + [ ]+1764:[ ]+0f 24 21 d3 b0[ ]+permpd %xmm3,%xmm2,%xmm11,%xmm11 + [ ]+1769:[ ]+0f 24 21 52 b0 04[ ]+permpd 0x4\(%rdx\),%xmm2,%xmm11,%xmm11 + [ ]+176f:[ ]+0f 24 21 52 b8 04[ ]+permpd %xmm2,0x4\(%rdx\),%xmm11,%xmm11 + [ ]+1775:[ ]+0f 24 25 d3 b0[ ]+permpd %xmm11,%xmm3,%xmm2,%xmm11 + [ ]+177a:[ ]+0f 24 25 52 b0 04[ ]+permpd %xmm11,0x4\(%rdx\),%xmm2,%xmm11 + [ ]+1780:[ ]+0f 24 25 52 b8 04[ ]+permpd %xmm11,%xmm2,0x4\(%rdx\),%xmm11 + [ ]+1786:[ ]+0f 24 22 d5 11[ ]+pcmov[ ]+%xmm13,%xmm2,%xmm1,%xmm1 + [ ]+178b:[ ]+0f 24 22 52 10 04[ ]+pcmov[ ]+0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+1791:[ ]+0f 24 22 52 18 04[ ]+pcmov[ ]+%xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+1797:[ ]+0f 24 26 d5 11[ ]+pcmov[ ]+%xmm1,%xmm13,%xmm2,%xmm1 + [ ]+179c:[ ]+0f 24 26 52 10 04[ ]+pcmov[ ]+%xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+17a2:[ ]+0f 24 26 52 18 04[ ]+pcmov[ ]+%xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+17a8:[ ]+0f 24 23 d5 11[ ]+pperm[ ]+%xmm13,%xmm2,%xmm1,%xmm1 + [ ]+17ad:[ ]+0f 24 23 52 10 04[ ]+pperm[ ]+0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+17b3:[ ]+0f 24 23 52 18 04[ ]+pperm[ ]+%xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+17b9:[ ]+0f 24 27 d5 11[ ]+pperm[ ]+%xmm1,%xmm13,%xmm2,%xmm1 + [ ]+17be:[ ]+0f 24 27 52 10 04[ ]+pperm[ ]+%xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+17c4:[ ]+0f 24 27 52 18 04[ ]+pperm[ ]+%xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+17ca:[ ]+0f 24 20 d5 11[ ]+permps %xmm13,%xmm2,%xmm1,%xmm1 + [ ]+17cf:[ ]+0f 24 20 52 10 04[ ]+permps 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+17d5:[ ]+0f 24 20 52 18 04[ ]+permps %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+17db:[ ]+0f 24 24 d5 11[ ]+permps %xmm1,%xmm13,%xmm2,%xmm1 + [ ]+17e0:[ ]+0f 24 24 52 10 04[ ]+permps %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+17e6:[ ]+0f 24 24 52 18 04[ ]+permps %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+17ec:[ ]+0f 24 21 d5 11[ ]+permpd %xmm13,%xmm2,%xmm1,%xmm1 + [ ]+17f1:[ ]+0f 24 21 52 10 04[ ]+permpd 0x4\(%rdx\),%xmm2,%xmm1,%xmm1 + [ ]+17f7:[ ]+0f 24 21 52 18 04[ ]+permpd %xmm2,0x4\(%rdx\),%xmm1,%xmm1 + [ ]+17fd:[ ]+0f 24 25 d5 11[ ]+permpd %xmm1,%xmm13,%xmm2,%xmm1 + [ ]+1802:[ ]+0f 24 25 52 10 04[ ]+permpd %xmm1,0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1808:[ ]+0f 24 25 52 18 04[ ]+permpd %xmm1,%xmm2,0x4\(%rdx\),%xmm1 + [ ]+180e:[ ]+0f 24 22 d3 10[ ]+pcmov[ ]+%xmm3,%xmm2,%xmm1,%xmm1 + [ ]+1813:[ ]+0f 24 22 97 11 00 00 10 00[ ]+pcmov[ ]+0x100000\(%r15\),%xmm2,%xmm1,%xmm1 + [ ]+181c:[ ]+0f 24 22 97 19 00 00 10 00[ ]+pcmov[ ]+%xmm2,0x100000\(%r15\),%xmm1,%xmm1 + [ ]+1825:[ ]+0f 24 26 d3 10[ ]+pcmov[ ]+%xmm1,%xmm3,%xmm2,%xmm1 + [ ]+182a:[ ]+0f 24 26 97 11 00 00 10 00[ ]+pcmov[ ]+%xmm1,0x100000\(%r15\),%xmm2,%xmm1 + [ ]+1833:[ ]+0f 24 26 97 19 00 00 10 00[ ]+pcmov[ ]+%xmm1,%xmm2,0x100000\(%r15\),%xmm1 + [ ]+183c:[ ]+0f 24 23 d3 10[ ]+pperm[ ]+%xmm3,%xmm2,%xmm1,%xmm1 + [ ]+1841:[ ]+0f 24 23 97 11 00 00 10 00[ ]+pperm[ ]+0x100000\(%r15\),%xmm2,%xmm1,%xmm1 + [ ]+184a:[ ]+0f 24 23 97 19 00 00 10 00[ ]+pperm[ ]+%xmm2,0x100000\(%r15\),%xmm1,%xmm1 + [ ]+1853:[ ]+0f 24 27 d3 10[ ]+pperm[ ]+%xmm1,%xmm3,%xmm2,%xmm1 + [ ]+1858:[ ]+0f 24 27 97 11 00 00 10 00[ ]+pperm[ ]+%xmm1,0x100000\(%r15\),%xmm2,%xmm1 + [ ]+1861:[ ]+0f 24 27 97 19 00 00 10 00[ ]+pperm[ ]+%xmm1,%xmm2,0x100000\(%r15\),%xmm1 + [ ]+186a:[ ]+0f 24 20 d3 10[ ]+permps %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+186f:[ ]+0f 24 20 97 11 00 00 10 00[ ]+permps 0x100000\(%r15\),%xmm2,%xmm1,%xmm1 + [ ]+1878:[ ]+0f 24 20 97 19 00 00 10 00[ ]+permps %xmm2,0x100000\(%r15\),%xmm1,%xmm1 + [ ]+1881:[ ]+0f 24 24 d3 10[ ]+permps %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+1886:[ ]+0f 24 24 97 11 00 00 10 00[ ]+permps %xmm1,0x100000\(%r15\),%xmm2,%xmm1 + [ ]+188f:[ ]+0f 24 24 97 19 00 00 10 00[ ]+permps %xmm1,%xmm2,0x100000\(%r15\),%xmm1 + [ ]+1898:[ ]+0f 24 21 d3 10[ ]+permpd %xmm3,%xmm2,%xmm1,%xmm1 + [ ]+189d:[ ]+0f 24 21 97 11 00 00 10 00[ ]+permpd 0x100000\(%r15\),%xmm2,%xmm1,%xmm1 + [ ]+18a6:[ ]+0f 24 21 97 19 00 00 10 00[ ]+permpd %xmm2,0x100000\(%r15\),%xmm1,%xmm1 + [ ]+18af:[ ]+0f 24 25 d3 10[ ]+permpd %xmm1,%xmm3,%xmm2,%xmm1 + [ ]+18b4:[ ]+0f 24 25 97 11 00 00 10 00[ ]+permpd %xmm1,0x100000\(%r15\),%xmm2,%xmm1 + [ ]+18bd:[ ]+0f 24 25 97 19 00 00 10 00[ ]+permpd %xmm1,%xmm2,0x100000\(%r15\),%xmm1 + [ ]+18c6:[ ]+0f 24 40 d3 10[ ]+protb[ ]+%xmm3,%xmm2,%xmm1 + [ ]+18cb:[ ]+0f 24 40 52 10 04[ ]+protb[ ]+0x4\(%rdx\),%xmm2,%xmm1 + [ ]+18d1:[ ]+0f 24 40 52 18 04[ ]+protb[ ]+%xmm2,0x4\(%rdx\),%xmm1 + [ ]+18d7:[ ]+0f 7b 40 ca 04[ ]+protb[ ]+\$0x4,%xmm2,%xmm1 + [ ]+18dc:[ ]+0f 24 41 d3 10[ ]+protw[ ]+%xmm3,%xmm2,%xmm1 + [ ]+18e1:[ ]+0f 24 41 52 10 04[ ]+protw[ ]+0x4\(%rdx\),%xmm2,%xmm1 + [ ]+18e7:[ ]+0f 24 41 52 18 04[ ]+protw[ ]+%xmm2,0x4\(%rdx\),%xmm1 + [ ]+18ed:[ ]+0f 7b 41 ca 04[ ]+protw[ ]+\$0x4,%xmm2,%xmm1 + [ ]+18f2:[ ]+0f 24 42 d3 10[ ]+protd[ ]+%xmm3,%xmm2,%xmm1 + [ ]+18f7:[ ]+0f 24 42 52 10 04[ ]+protd[ ]+0x4\(%rdx\),%xmm2,%xmm1 + [ ]+18fd:[ ]+0f 24 42 52 18 04[ ]+protd[ ]+%xmm2,0x4\(%rdx\),%xmm1 + [ ]+1903:[ ]+0f 7b 42 ca 04[ ]+protd[ ]+\$0x4,%xmm2,%xmm1 + [ ]+1908:[ ]+0f 24 43 d3 10[ ]+protq[ ]+%xmm3,%xmm2,%xmm1 + [ ]+190d:[ ]+0f 24 43 52 10 04[ ]+protq[ ]+0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1913:[ ]+0f 24 43 52 18 04[ ]+protq[ ]+%xmm2,0x4\(%rdx\),%xmm1 + [ ]+1919:[ ]+0f 7b 43 ca 04[ ]+protq[ ]+\$0x4,%xmm2,%xmm1 + [ ]+191e:[ ]+0f 24 40 e5 b5[ ]+protb[ ]+%xmm13,%xmm12,%xmm11 + [ ]+1923:[ ]+0f 24 40 a7 b5 00 00 10 00[ ]+protb[ ]+0x100000\(%r15\),%xmm12,%xmm11 + [ ]+192c:[ ]+0f 24 40 a7 bd 00 00 10 00[ ]+protb[ ]+%xmm12,0x100000\(%r15\),%xmm11 + [ ]+1935:[ ]+45 0f 7b 40 dc 04[ ]+protb[ ]+\$0x4,%xmm12,%xmm11 + [ ]+193b:[ ]+0f 24 41 e5 b5[ ]+protw[ ]+%xmm13,%xmm12,%xmm11 + [ ]+1940:[ ]+0f 24 41 a7 b5 00 00 10 00[ ]+protw[ ]+0x100000\(%r15\),%xmm12,%xmm11 + [ ]+1949:[ ]+0f 24 41 a7 bd 00 00 10 00[ ]+protw[ ]+%xmm12,0x100000\(%r15\),%xmm11 + [ ]+1952:[ ]+45 0f 7b 41 dc 04[ ]+protw[ ]+\$0x4,%xmm12,%xmm11 + [ ]+1958:[ ]+0f 24 42 e5 b5[ ]+protd[ ]+%xmm13,%xmm12,%xmm11 + [ ]+195d:[ ]+0f 24 42 a7 b5 00 00 10 00[ ]+protd[ ]+0x100000\(%r15\),%xmm12,%xmm11 + [ ]+1966:[ ]+0f 24 42 a7 bd 00 00 10 00[ ]+protd[ ]+%xmm12,0x100000\(%r15\),%xmm11 + [ ]+196f:[ ]+45 0f 7b 42 dc 04[ ]+protd[ ]+\$0x4,%xmm12,%xmm11 + [ ]+1975:[ ]+0f 24 43 e5 b5[ ]+protq[ ]+%xmm13,%xmm12,%xmm11 + [ ]+197a:[ ]+0f 24 43 a7 b5 00 00 10 00[ ]+protq[ ]+0x100000\(%r15\),%xmm12,%xmm11 + [ ]+1983:[ ]+0f 24 43 a7 bd 00 00 10 00[ ]+protq[ ]+%xmm12,0x100000\(%r15\),%xmm11 + [ ]+198c:[ ]+45 0f 7b 43 dc 04[ ]+protq[ ]+\$0x4,%xmm12,%xmm11 + [ ]+1992:[ ]+0f 24 40 e3 14[ ]+protb[ ]+%xmm3,%xmm12,%xmm1 + [ ]+1997:[ ]+0f 24 40 62 14 04[ ]+protb[ ]+0x4\(%rdx\),%xmm12,%xmm1 + [ ]+199d:[ ]+0f 24 40 62 1c 04[ ]+protb[ ]+%xmm12,0x4\(%rdx\),%xmm1 + [ ]+19a3:[ ]+41 0f 7b 40 cc 04[ ]+protb[ ]+\$0x4,%xmm12,%xmm1 + [ ]+19a9:[ ]+0f 24 41 e3 14[ ]+protw[ ]+%xmm3,%xmm12,%xmm1 + [ ]+19ae:[ ]+0f 24 41 62 14 04[ ]+protw[ ]+0x4\(%rdx\),%xmm12,%xmm1 + [ ]+19b4:[ ]+0f 24 41 62 1c 04[ ]+protw[ ]+%xmm12,0x4\(%rdx\),%xmm1 + [ ]+19ba:[ ]+41 0f 7b 41 cc 04[ ]+protw[ ]+\$0x4,%xmm12,%xmm1 + [ ]+19c0:[ ]+0f 24 42 e3 14[ ]+protd[ ]+%xmm3,%xmm12,%xmm1 + [ ]+19c5:[ ]+0f 24 42 62 14 04[ ]+protd[ ]+0x4\(%rdx\),%xmm12,%xmm1 + [ ]+19cb:[ ]+0f 24 42 62 1c 04[ ]+protd[ ]+%xmm12,0x4\(%rdx\),%xmm1 + [ ]+19d1:[ ]+41 0f 7b 42 cc 04[ ]+protd[ ]+\$0x4,%xmm12,%xmm1 + [ ]+19d7:[ ]+0f 24 43 e3 14[ ]+protq[ ]+%xmm3,%xmm12,%xmm1 + [ ]+19dc:[ ]+0f 24 43 62 14 04[ ]+protq[ ]+0x4\(%rdx\),%xmm12,%xmm1 + [ ]+19e2:[ ]+0f 24 43 62 1c 04[ ]+protq[ ]+%xmm12,0x4\(%rdx\),%xmm1 + [ ]+19e8:[ ]+41 0f 7b 43 cc 04[ ]+protq[ ]+\$0x4,%xmm12,%xmm1 + [ ]+19ee:[ ]+0f 24 40 d3 b0[ ]+protb[ ]+%xmm3,%xmm2,%xmm11 + [ ]+19f3:[ ]+0f 24 40 52 b0 04[ ]+protb[ ]+0x4\(%rdx\),%xmm2,%xmm11 + [ ]+19f9:[ ]+0f 24 40 52 b8 04[ ]+protb[ ]+%xmm2,0x4\(%rdx\),%xmm11 + [ ]+19ff:[ ]+44 0f 7b 40 da 04[ ]+protb[ ]+\$0x4,%xmm2,%xmm11 + [ ]+1a05:[ ]+0f 24 41 d3 b0[ ]+protw[ ]+%xmm3,%xmm2,%xmm11 + [ ]+1a0a:[ ]+0f 24 41 52 b0 04[ ]+protw[ ]+0x4\(%rdx\),%xmm2,%xmm11 + [ ]+1a10:[ ]+0f 24 41 52 b8 04[ ]+protw[ ]+%xmm2,0x4\(%rdx\),%xmm11 + [ ]+1a16:[ ]+44 0f 7b 41 da 04[ ]+protw[ ]+\$0x4,%xmm2,%xmm11 + [ ]+1a1c:[ ]+0f 24 42 d3 b0[ ]+protd[ ]+%xmm3,%xmm2,%xmm11 + [ ]+1a21:[ ]+0f 24 42 52 b0 04[ ]+protd[ ]+0x4\(%rdx\),%xmm2,%xmm11 + [ ]+1a27:[ ]+0f 24 42 52 b8 04[ ]+protd[ ]+%xmm2,0x4\(%rdx\),%xmm11 + [ ]+1a2d:[ ]+44 0f 7b 42 da 04[ ]+protd[ ]+\$0x4,%xmm2,%xmm11 + [ ]+1a33:[ ]+0f 24 43 d3 b0[ ]+protq[ ]+%xmm3,%xmm2,%xmm11 + [ ]+1a38:[ ]+0f 24 43 52 b0 04[ ]+protq[ ]+0x4\(%rdx\),%xmm2,%xmm11 + [ ]+1a3e:[ ]+0f 24 43 52 b8 04[ ]+protq[ ]+%xmm2,0x4\(%rdx\),%xmm11 + [ ]+1a44:[ ]+44 0f 7b 43 da 04[ ]+protq[ ]+\$0x4,%xmm2,%xmm11 + [ ]+1a4a:[ ]+0f 24 40 d5 11[ ]+protb[ ]+%xmm13,%xmm2,%xmm1 + [ ]+1a4f:[ ]+0f 24 40 52 10 04[ ]+protb[ ]+0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1a55:[ ]+0f 24 40 52 18 04[ ]+protb[ ]+%xmm2,0x4\(%rdx\),%xmm1 + [ ]+1a5b:[ ]+0f 7b 40 ca 04[ ]+protb[ ]+\$0x4,%xmm2,%xmm1 + [ ]+1a60:[ ]+0f 24 41 d5 11[ ]+protw[ ]+%xmm13,%xmm2,%xmm1 + [ ]+1a65:[ ]+0f 24 41 52 10 04[ ]+protw[ ]+0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1a6b:[ ]+0f 24 41 52 18 04[ ]+protw[ ]+%xmm2,0x4\(%rdx\),%xmm1 + [ ]+1a71:[ ]+0f 7b 41 ca 04[ ]+protw[ ]+\$0x4,%xmm2,%xmm1 + [ ]+1a76:[ ]+0f 24 42 d5 11[ ]+protd[ ]+%xmm13,%xmm2,%xmm1 + [ ]+1a7b:[ ]+0f 24 42 52 10 04[ ]+protd[ ]+0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1a81:[ ]+0f 24 42 52 18 04[ ]+protd[ ]+%xmm2,0x4\(%rdx\),%xmm1 + [ ]+1a87:[ ]+0f 7b 42 ca 04[ ]+protd[ ]+\$0x4,%xmm2,%xmm1 + [ ]+1a8c:[ ]+0f 24 43 d5 11[ ]+protq[ ]+%xmm13,%xmm2,%xmm1 + [ ]+1a91:[ ]+0f 24 43 52 10 04[ ]+protq[ ]+0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1a97:[ ]+0f 24 43 52 18 04[ ]+protq[ ]+%xmm2,0x4\(%rdx\),%xmm1 + [ ]+1a9d:[ ]+0f 7b 43 ca 04[ ]+protq[ ]+\$0x4,%xmm2,%xmm1 + [ ]+1aa2:[ ]+0f 24 40 d3 10[ ]+protb[ ]+%xmm3,%xmm2,%xmm1 + [ ]+1aa7:[ ]+0f 24 40 97 11 00 00 10 00[ ]+protb[ ]+0x100000\(%r15\),%xmm2,%xmm1 + [ ]+1ab0:[ ]+0f 24 40 97 19 00 00 10 00[ ]+protb[ ]+%xmm2,0x100000\(%r15\),%xmm1 + [ ]+1ab9:[ ]+0f 7b 40 ca 04[ ]+protb[ ]+\$0x4,%xmm2,%xmm1 + [ ]+1abe:[ ]+0f 24 41 d3 10[ ]+protw[ ]+%xmm3,%xmm2,%xmm1 + [ ]+1ac3:[ ]+0f 24 41 97 11 00 00 10 00[ ]+protw[ ]+0x100000\(%r15\),%xmm2,%xmm1 + [ ]+1acc:[ ]+0f 24 41 97 19 00 00 10 00[ ]+protw[ ]+%xmm2,0x100000\(%r15\),%xmm1 + [ ]+1ad5:[ ]+0f 7b 41 ca 04[ ]+protw[ ]+\$0x4,%xmm2,%xmm1 + [ ]+1ada:[ ]+0f 24 42 d3 10[ ]+protd[ ]+%xmm3,%xmm2,%xmm1 + [ ]+1adf:[ ]+0f 24 42 97 11 00 00 10 00[ ]+protd[ ]+0x100000\(%r15\),%xmm2,%xmm1 + [ ]+1ae8:[ ]+0f 24 42 97 19 00 00 10 00[ ]+protd[ ]+%xmm2,0x100000\(%r15\),%xmm1 + [ ]+1af1:[ ]+0f 7b 42 ca 04[ ]+protd[ ]+\$0x4,%xmm2,%xmm1 + [ ]+1af6:[ ]+0f 24 43 d3 10[ ]+protq[ ]+%xmm3,%xmm2,%xmm1 + [ ]+1afb:[ ]+0f 24 43 97 11 00 00 10 00[ ]+protq[ ]+0x100000\(%r15\),%xmm2,%xmm1 + [ ]+1b04:[ ]+0f 24 43 97 19 00 00 10 00[ ]+protq[ ]+%xmm2,0x100000\(%r15\),%xmm1 + [ ]+1b0d:[ ]+0f 7b 43 ca 04[ ]+protq[ ]+\$0x4,%xmm2,%xmm1 + [ ]+1b12:[ ]+0f 24 44 d3 10[ ]+pshlb[ ]+%xmm3,%xmm2,%xmm1 + [ ]+1b17:[ ]+0f 24 44 52 10 04[ ]+pshlb[ ]+0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1b1d:[ ]+0f 24 44 52 18 04[ ]+pshlb[ ]+%xmm2,0x4\(%rdx\),%xmm1 + [ ]+1b23:[ ]+0f 24 45 d3 10[ ]+pshlw[ ]+%xmm3,%xmm2,%xmm1 + [ ]+1b28:[ ]+0f 24 45 52 10 04[ ]+pshlw[ ]+0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1b2e:[ ]+0f 24 45 52 18 04[ ]+pshlw[ ]+%xmm2,0x4\(%rdx\),%xmm1 + [ ]+1b34:[ ]+0f 24 46 d3 10[ ]+pshld[ ]+%xmm3,%xmm2,%xmm1 + [ ]+1b39:[ ]+0f 24 46 52 10 04[ ]+pshld[ ]+0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1b3f:[ ]+0f 24 46 52 18 04[ ]+pshld[ ]+%xmm2,0x4\(%rdx\),%xmm1 + [ ]+1b45:[ ]+0f 24 47 d3 10[ ]+pshlq[ ]+%xmm3,%xmm2,%xmm1 + [ ]+1b4a:[ ]+0f 24 47 52 10 04[ ]+pshlq[ ]+0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1b50:[ ]+0f 24 47 52 18 04[ ]+pshlq[ ]+%xmm2,0x4\(%rdx\),%xmm1 + [ ]+1b56:[ ]+0f 24 48 d3 10[ ]+pshab[ ]+%xmm3,%xmm2,%xmm1 + [ ]+1b5b:[ ]+0f 24 48 52 10 04[ ]+pshab[ ]+0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1b61:[ ]+0f 24 48 52 18 04[ ]+pshab[ ]+%xmm2,0x4\(%rdx\),%xmm1 + [ ]+1b67:[ ]+0f 24 49 d3 10[ ]+pshaw[ ]+%xmm3,%xmm2,%xmm1 + [ ]+1b6c:[ ]+0f 24 49 52 10 04[ ]+pshaw[ ]+0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1b72:[ ]+0f 24 49 52 18 04[ ]+pshaw[ ]+%xmm2,0x4\(%rdx\),%xmm1 + [ ]+1b78:[ ]+0f 24 4a d3 10[ ]+pshad[ ]+%xmm3,%xmm2,%xmm1 + [ ]+1b7d:[ ]+0f 24 4a 52 10 04[ ]+pshad[ ]+0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1b83:[ ]+0f 24 4a 52 18 04[ ]+pshad[ ]+%xmm2,0x4\(%rdx\),%xmm1 + [ ]+1b89:[ ]+0f 24 4b d3 10[ ]+pshaq[ ]+%xmm3,%xmm2,%xmm1 + [ ]+1b8e:[ ]+0f 24 4b 52 10 04[ ]+pshaq[ ]+0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1b94:[ ]+0f 24 4b 52 18 04[ ]+pshaq[ ]+%xmm2,0x4\(%rdx\),%xmm1 + [ ]+1b9a:[ ]+0f 24 44 e5 b5[ ]+pshlb[ ]+%xmm13,%xmm12,%xmm11 + [ ]+1b9f:[ ]+0f 24 44 a7 b5 00 00 10 00[ ]+pshlb[ ]+0x100000\(%r15\),%xmm12,%xmm11 + [ ]+1ba8:[ ]+0f 24 44 a7 bd 00 00 10 00[ ]+pshlb[ ]+%xmm12,0x100000\(%r15\),%xmm11 + [ ]+1bb1:[ ]+0f 24 45 e5 b5[ ]+pshlw[ ]+%xmm13,%xmm12,%xmm11 + [ ]+1bb6:[ ]+0f 24 45 a7 b5 00 00 10 00[ ]+pshlw[ ]+0x100000\(%r15\),%xmm12,%xmm11 + [ ]+1bbf:[ ]+0f 24 45 a7 bd 00 00 10 00[ ]+pshlw[ ]+%xmm12,0x100000\(%r15\),%xmm11 + [ ]+1bc8:[ ]+0f 24 46 e5 b5[ ]+pshld[ ]+%xmm13,%xmm12,%xmm11 + [ ]+1bcd:[ ]+0f 24 46 a7 b5 00 00 10 00[ ]+pshld[ ]+0x100000\(%r15\),%xmm12,%xmm11 + [ ]+1bd6:[ ]+0f 24 46 a7 bd 00 00 10 00[ ]+pshld[ ]+%xmm12,0x100000\(%r15\),%xmm11 + [ ]+1bdf:[ ]+0f 24 47 e5 b5[ ]+pshlq[ ]+%xmm13,%xmm12,%xmm11 + [ ]+1be4:[ ]+0f 24 47 a7 b5 00 00 10 00[ ]+pshlq[ ]+0x100000\(%r15\),%xmm12,%xmm11 + [ ]+1bed:[ ]+0f 24 47 a7 bd 00 00 10 00[ ]+pshlq[ ]+%xmm12,0x100000\(%r15\),%xmm11 + [ ]+1bf6:[ ]+0f 24 48 e5 b5[ ]+pshab[ ]+%xmm13,%xmm12,%xmm11 + [ ]+1bfb:[ ]+0f 24 48 a7 b5 00 00 10 00[ ]+pshab[ ]+0x100000\(%r15\),%xmm12,%xmm11 + [ ]+1c04:[ ]+0f 24 48 a7 bd 00 00 10 00[ ]+pshab[ ]+%xmm12,0x100000\(%r15\),%xmm11 + [ ]+1c0d:[ ]+0f 24 49 e5 b5[ ]+pshaw[ ]+%xmm13,%xmm12,%xmm11 + [ ]+1c12:[ ]+0f 24 49 a7 b5 00 00 10 00[ ]+pshaw[ ]+0x100000\(%r15\),%xmm12,%xmm11 + [ ]+1c1b:[ ]+0f 24 49 a7 bd 00 00 10 00[ ]+pshaw[ ]+%xmm12,0x100000\(%r15\),%xmm11 + [ ]+1c24:[ ]+0f 24 4a e5 b5[ ]+pshad[ ]+%xmm13,%xmm12,%xmm11 + [ ]+1c29:[ ]+0f 24 4a a7 b5 00 00 10 00[ ]+pshad[ ]+0x100000\(%r15\),%xmm12,%xmm11 + [ ]+1c32:[ ]+0f 24 4a a7 bd 00 00 10 00[ ]+pshad[ ]+%xmm12,0x100000\(%r15\),%xmm11 + [ ]+1c3b:[ ]+0f 24 4b e5 b5[ ]+pshaq[ ]+%xmm13,%xmm12,%xmm11 + [ ]+1c40:[ ]+0f 24 4b a7 b5 00 00 10 00[ ]+pshaq[ ]+0x100000\(%r15\),%xmm12,%xmm11 + [ ]+1c49:[ ]+0f 24 4b a7 bd 00 00 10 00[ ]+pshaq[ ]+%xmm12,0x100000\(%r15\),%xmm11 + [ ]+1c52:[ ]+0f 24 44 e3 14[ ]+pshlb[ ]+%xmm3,%xmm12,%xmm1 + [ ]+1c57:[ ]+0f 24 44 62 14 04[ ]+pshlb[ ]+0x4\(%rdx\),%xmm12,%xmm1 + [ ]+1c5d:[ ]+0f 24 44 62 1c 04[ ]+pshlb[ ]+%xmm12,0x4\(%rdx\),%xmm1 + [ ]+1c63:[ ]+0f 24 45 e3 14[ ]+pshlw[ ]+%xmm3,%xmm12,%xmm1 + [ ]+1c68:[ ]+0f 24 45 62 14 04[ ]+pshlw[ ]+0x4\(%rdx\),%xmm12,%xmm1 + [ ]+1c6e:[ ]+0f 24 45 62 1c 04[ ]+pshlw[ ]+%xmm12,0x4\(%rdx\),%xmm1 + [ ]+1c74:[ ]+0f 24 46 e3 14[ ]+pshld[ ]+%xmm3,%xmm12,%xmm1 + [ ]+1c79:[ ]+0f 24 46 62 14 04[ ]+pshld[ ]+0x4\(%rdx\),%xmm12,%xmm1 + [ ]+1c7f:[ ]+0f 24 46 62 1c 04[ ]+pshld[ ]+%xmm12,0x4\(%rdx\),%xmm1 + [ ]+1c85:[ ]+0f 24 47 e3 14[ ]+pshlq[ ]+%xmm3,%xmm12,%xmm1 + [ ]+1c8a:[ ]+0f 24 47 62 14 04[ ]+pshlq[ ]+0x4\(%rdx\),%xmm12,%xmm1 + [ ]+1c90:[ ]+0f 24 47 62 1c 04[ ]+pshlq[ ]+%xmm12,0x4\(%rdx\),%xmm1 + [ ]+1c96:[ ]+0f 24 48 e3 14[ ]+pshab[ ]+%xmm3,%xmm12,%xmm1 + [ ]+1c9b:[ ]+0f 24 48 62 14 04[ ]+pshab[ ]+0x4\(%rdx\),%xmm12,%xmm1 + [ ]+1ca1:[ ]+0f 24 48 62 1c 04[ ]+pshab[ ]+%xmm12,0x4\(%rdx\),%xmm1 + [ ]+1ca7:[ ]+0f 24 49 e3 14[ ]+pshaw[ ]+%xmm3,%xmm12,%xmm1 + [ ]+1cac:[ ]+0f 24 49 62 14 04[ ]+pshaw[ ]+0x4\(%rdx\),%xmm12,%xmm1 + [ ]+1cb2:[ ]+0f 24 49 62 1c 04[ ]+pshaw[ ]+%xmm12,0x4\(%rdx\),%xmm1 + [ ]+1cb8:[ ]+0f 24 4a e3 14[ ]+pshad[ ]+%xmm3,%xmm12,%xmm1 + [ ]+1cbd:[ ]+0f 24 4a 62 14 04[ ]+pshad[ ]+0x4\(%rdx\),%xmm12,%xmm1 + [ ]+1cc3:[ ]+0f 24 4a 62 1c 04[ ]+pshad[ ]+%xmm12,0x4\(%rdx\),%xmm1 + [ ]+1cc9:[ ]+0f 24 4b e3 14[ ]+pshaq[ ]+%xmm3,%xmm12,%xmm1 + [ ]+1cce:[ ]+0f 24 4b 62 14 04[ ]+pshaq[ ]+0x4\(%rdx\),%xmm12,%xmm1 + [ ]+1cd4:[ ]+0f 24 4b 62 1c 04[ ]+pshaq[ ]+%xmm12,0x4\(%rdx\),%xmm1 + [ ]+1cda:[ ]+0f 24 44 d3 b0[ ]+pshlb[ ]+%xmm3,%xmm2,%xmm11 + [ ]+1cdf:[ ]+0f 24 44 52 b0 04[ ]+pshlb[ ]+0x4\(%rdx\),%xmm2,%xmm11 + [ ]+1ce5:[ ]+0f 24 44 52 b8 04[ ]+pshlb[ ]+%xmm2,0x4\(%rdx\),%xmm11 + [ ]+1ceb:[ ]+0f 24 45 d3 b0[ ]+pshlw[ ]+%xmm3,%xmm2,%xmm11 + [ ]+1cf0:[ ]+0f 24 45 52 b0 04[ ]+pshlw[ ]+0x4\(%rdx\),%xmm2,%xmm11 + [ ]+1cf6:[ ]+0f 24 45 52 b8 04[ ]+pshlw[ ]+%xmm2,0x4\(%rdx\),%xmm11 + [ ]+1cfc:[ ]+0f 24 46 d3 b0[ ]+pshld[ ]+%xmm3,%xmm2,%xmm11 + [ ]+1d01:[ ]+0f 24 46 52 b0 04[ ]+pshld[ ]+0x4\(%rdx\),%xmm2,%xmm11 + [ ]+1d07:[ ]+0f 24 46 52 b8 04[ ]+pshld[ ]+%xmm2,0x4\(%rdx\),%xmm11 + [ ]+1d0d:[ ]+0f 24 47 d3 b0[ ]+pshlq[ ]+%xmm3,%xmm2,%xmm11 + [ ]+1d12:[ ]+0f 24 47 52 b0 04[ ]+pshlq[ ]+0x4\(%rdx\),%xmm2,%xmm11 + [ ]+1d18:[ ]+0f 24 47 52 b8 04[ ]+pshlq[ ]+%xmm2,0x4\(%rdx\),%xmm11 + [ ]+1d1e:[ ]+0f 24 48 d3 b0[ ]+pshab[ ]+%xmm3,%xmm2,%xmm11 + [ ]+1d23:[ ]+0f 24 48 52 b0 04[ ]+pshab[ ]+0x4\(%rdx\),%xmm2,%xmm11 + [ ]+1d29:[ ]+0f 24 48 52 b8 04[ ]+pshab[ ]+%xmm2,0x4\(%rdx\),%xmm11 + [ ]+1d2f:[ ]+0f 24 49 d3 b0[ ]+pshaw[ ]+%xmm3,%xmm2,%xmm11 + [ ]+1d34:[ ]+0f 24 49 52 b0 04[ ]+pshaw[ ]+0x4\(%rdx\),%xmm2,%xmm11 + [ ]+1d3a:[ ]+0f 24 49 52 b8 04[ ]+pshaw[ ]+%xmm2,0x4\(%rdx\),%xmm11 + [ ]+1d40:[ ]+0f 24 4a d3 b0[ ]+pshad[ ]+%xmm3,%xmm2,%xmm11 + [ ]+1d45:[ ]+0f 24 4a 52 b0 04[ ]+pshad[ ]+0x4\(%rdx\),%xmm2,%xmm11 + [ ]+1d4b:[ ]+0f 24 4a 52 b8 04[ ]+pshad[ ]+%xmm2,0x4\(%rdx\),%xmm11 + [ ]+1d51:[ ]+0f 24 4b d3 b0[ ]+pshaq[ ]+%xmm3,%xmm2,%xmm11 + [ ]+1d56:[ ]+0f 24 4b 52 b0 04[ ]+pshaq[ ]+0x4\(%rdx\),%xmm2,%xmm11 + [ ]+1d5c:[ ]+0f 24 4b 52 b8 04[ ]+pshaq[ ]+%xmm2,0x4\(%rdx\),%xmm11 + [ ]+1d62:[ ]+0f 24 44 d5 11[ ]+pshlb[ ]+%xmm13,%xmm2,%xmm1 + [ ]+1d67:[ ]+0f 24 44 52 10 04[ ]+pshlb[ ]+0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1d6d:[ ]+0f 24 44 52 18 04[ ]+pshlb[ ]+%xmm2,0x4\(%rdx\),%xmm1 + [ ]+1d73:[ ]+0f 24 45 d5 11[ ]+pshlw[ ]+%xmm13,%xmm2,%xmm1 + [ ]+1d78:[ ]+0f 24 45 52 10 04[ ]+pshlw[ ]+0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1d7e:[ ]+0f 24 45 52 18 04[ ]+pshlw[ ]+%xmm2,0x4\(%rdx\),%xmm1 + [ ]+1d84:[ ]+0f 24 46 d5 11[ ]+pshld[ ]+%xmm13,%xmm2,%xmm1 + [ ]+1d89:[ ]+0f 24 46 52 10 04[ ]+pshld[ ]+0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1d8f:[ ]+0f 24 46 52 18 04[ ]+pshld[ ]+%xmm2,0x4\(%rdx\),%xmm1 + [ ]+1d95:[ ]+0f 24 47 d5 11[ ]+pshlq[ ]+%xmm13,%xmm2,%xmm1 + [ ]+1d9a:[ ]+0f 24 47 52 10 04[ ]+pshlq[ ]+0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1da0:[ ]+0f 24 47 52 18 04[ ]+pshlq[ ]+%xmm2,0x4\(%rdx\),%xmm1 + [ ]+1da6:[ ]+0f 24 48 d5 11[ ]+pshab[ ]+%xmm13,%xmm2,%xmm1 + [ ]+1dab:[ ]+0f 24 48 52 10 04[ ]+pshab[ ]+0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1db1:[ ]+0f 24 48 52 18 04[ ]+pshab[ ]+%xmm2,0x4\(%rdx\),%xmm1 + [ ]+1db7:[ ]+0f 24 49 d5 11[ ]+pshaw[ ]+%xmm13,%xmm2,%xmm1 + [ ]+1dbc:[ ]+0f 24 49 52 10 04[ ]+pshaw[ ]+0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1dc2:[ ]+0f 24 49 52 18 04[ ]+pshaw[ ]+%xmm2,0x4\(%rdx\),%xmm1 + [ ]+1dc8:[ ]+0f 24 4a d5 11[ ]+pshad[ ]+%xmm13,%xmm2,%xmm1 + [ ]+1dcd:[ ]+0f 24 4a 52 10 04[ ]+pshad[ ]+0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1dd3:[ ]+0f 24 4a 52 18 04[ ]+pshad[ ]+%xmm2,0x4\(%rdx\),%xmm1 + [ ]+1dd9:[ ]+0f 24 4b d5 11[ ]+pshaq[ ]+%xmm13,%xmm2,%xmm1 + [ ]+1dde:[ ]+0f 24 4b 52 10 04[ ]+pshaq[ ]+0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1de4:[ ]+0f 24 4b 52 18 04[ ]+pshaq[ ]+%xmm2,0x4\(%rdx\),%xmm1 + [ ]+1dea:[ ]+0f 24 44 d3 10[ ]+pshlb[ ]+%xmm3,%xmm2,%xmm1 + [ ]+1def:[ ]+0f 24 44 97 11 00 00 10 00[ ]+pshlb[ ]+0x100000\(%r15\),%xmm2,%xmm1 + [ ]+1df8:[ ]+0f 24 44 97 19 00 00 10 00[ ]+pshlb[ ]+%xmm2,0x100000\(%r15\),%xmm1 + [ ]+1e01:[ ]+0f 24 45 d3 10[ ]+pshlw[ ]+%xmm3,%xmm2,%xmm1 + [ ]+1e06:[ ]+0f 24 45 97 11 00 00 10 00[ ]+pshlw[ ]+0x100000\(%r15\),%xmm2,%xmm1 + [ ]+1e0f:[ ]+0f 24 45 97 19 00 00 10 00[ ]+pshlw[ ]+%xmm2,0x100000\(%r15\),%xmm1 + [ ]+1e18:[ ]+0f 24 46 d3 10[ ]+pshld[ ]+%xmm3,%xmm2,%xmm1 + [ ]+1e1d:[ ]+0f 24 46 97 11 00 00 10 00[ ]+pshld[ ]+0x100000\(%r15\),%xmm2,%xmm1 + [ ]+1e26:[ ]+0f 24 46 97 19 00 00 10 00[ ]+pshld[ ]+%xmm2,0x100000\(%r15\),%xmm1 + [ ]+1e2f:[ ]+0f 24 47 d3 10[ ]+pshlq[ ]+%xmm3,%xmm2,%xmm1 + [ ]+1e34:[ ]+0f 24 47 97 11 00 00 10 00[ ]+pshlq[ ]+0x100000\(%r15\),%xmm2,%xmm1 + [ ]+1e3d:[ ]+0f 24 47 97 19 00 00 10 00[ ]+pshlq[ ]+%xmm2,0x100000\(%r15\),%xmm1 + [ ]+1e46:[ ]+0f 24 48 d3 10[ ]+pshab[ ]+%xmm3,%xmm2,%xmm1 + [ ]+1e4b:[ ]+0f 24 48 97 11 00 00 10 00[ ]+pshab[ ]+0x100000\(%r15\),%xmm2,%xmm1 + [ ]+1e54:[ ]+0f 24 48 97 19 00 00 10 00[ ]+pshab[ ]+%xmm2,0x100000\(%r15\),%xmm1 + [ ]+1e5d:[ ]+0f 24 49 d3 10[ ]+pshaw[ ]+%xmm3,%xmm2,%xmm1 + [ ]+1e62:[ ]+0f 24 49 97 11 00 00 10 00[ ]+pshaw[ ]+0x100000\(%r15\),%xmm2,%xmm1 + [ ]+1e6b:[ ]+0f 24 49 97 19 00 00 10 00[ ]+pshaw[ ]+%xmm2,0x100000\(%r15\),%xmm1 + [ ]+1e74:[ ]+0f 24 4a d3 10[ ]+pshad[ ]+%xmm3,%xmm2,%xmm1 + [ ]+1e79:[ ]+0f 24 4a 97 11 00 00 10 00[ ]+pshad[ ]+0x100000\(%r15\),%xmm2,%xmm1 + [ ]+1e82:[ ]+0f 24 4a 97 19 00 00 10 00[ ]+pshad[ ]+%xmm2,0x100000\(%r15\),%xmm1 + [ ]+1e8b:[ ]+0f 24 4b d3 10[ ]+pshaq[ ]+%xmm3,%xmm2,%xmm1 + [ ]+1e90:[ ]+0f 24 4b 97 11 00 00 10 00[ ]+pshaq[ ]+0x100000\(%r15\),%xmm2,%xmm1 + [ ]+1e99:[ ]+0f 24 4b 97 19 00 00 10 00[ ]+pshaq[ ]+%xmm2,0x100000\(%r15\),%xmm1 + [ ]+1ea2:[ ]+0f 25 2e d3 10 04[ ]+comness %xmm3,%xmm2,%xmm1 + [ ]+1ea8:[ ]+0f 25 2e 52 10 04 04[ ]+comness 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1eaf:[ ]+0f 25 2e d3 10 00[ ]+comeqss %xmm3,%xmm2,%xmm1 + [ ]+1eb5:[ ]+0f 25 2e d3 10 01[ ]+comltss %xmm3,%xmm2,%xmm1 + [ ]+1ebb:[ ]+0f 25 2e d3 10 02[ ]+comless %xmm3,%xmm2,%xmm1 + [ ]+1ec1:[ ]+0f 25 2e d3 10 03[ ]+comunordss %xmm3,%xmm2,%xmm1 + [ ]+1ec7:[ ]+0f 25 2e d3 10 04[ ]+comness %xmm3,%xmm2,%xmm1 + [ ]+1ecd:[ ]+0f 25 2e d3 10 05[ ]+comnltss %xmm3,%xmm2,%xmm1 + [ ]+1ed3:[ ]+0f 25 2e d3 10 06[ ]+comnless %xmm3,%xmm2,%xmm1 + [ ]+1ed9:[ ]+0f 25 2e d3 10 07[ ]+comordss %xmm3,%xmm2,%xmm1 + [ ]+1edf:[ ]+0f 25 2e d3 10 08[ ]+comueqss %xmm3,%xmm2,%xmm1 + [ ]+1ee5:[ ]+0f 25 2e d3 10 09[ ]+comultss %xmm3,%xmm2,%xmm1 + [ ]+1eeb:[ ]+0f 25 2e d3 10 0a[ ]+comuless %xmm3,%xmm2,%xmm1 + [ ]+1ef1:[ ]+0f 25 2e d3 10 0b[ ]+comfalsess %xmm3,%xmm2,%xmm1 + [ ]+1ef7:[ ]+0f 25 2e d3 10 0c[ ]+comuness %xmm3,%xmm2,%xmm1 + [ ]+1efd:[ ]+0f 25 2e d3 10 0d[ ]+comunltss %xmm3,%xmm2,%xmm1 + [ ]+1f03:[ ]+0f 25 2e d3 10 0e[ ]+comunless %xmm3,%xmm2,%xmm1 + [ ]+1f09:[ ]+0f 25 2e d3 10 0f[ ]+comtruess %xmm3,%xmm2,%xmm1 + [ ]+1f0f:[ ]+0f 25 2e 52 10 04 00[ ]+comeqss 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1f16:[ ]+0f 25 2e 52 10 04 01[ ]+comltss 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1f1d:[ ]+0f 25 2e 52 10 04 02[ ]+comless 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1f24:[ ]+0f 25 2e 52 10 04 03[ ]+comunordss 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1f2b:[ ]+0f 25 2e 52 10 04 04[ ]+comness 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1f32:[ ]+0f 25 2e 52 10 04 05[ ]+comnltss 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1f39:[ ]+0f 25 2e 52 10 04 06[ ]+comnless 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1f40:[ ]+0f 25 2e 52 10 04 07[ ]+comordss 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1f47:[ ]+0f 25 2e 52 10 04 08[ ]+comueqss 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1f4e:[ ]+0f 25 2e 52 10 04 09[ ]+comultss 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1f55:[ ]+0f 25 2e 52 10 04 0a[ ]+comuless 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1f5c:[ ]+0f 25 2e 52 10 04 0b[ ]+comfalsess 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1f63:[ ]+0f 25 2e 52 10 04 0c[ ]+comuness 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1f6a:[ ]+0f 25 2e 52 10 04 0d[ ]+comunltss 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1f71:[ ]+0f 25 2e 52 10 04 0e[ ]+comunless 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1f78:[ ]+0f 25 2e 52 10 04 0f[ ]+comtruess 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1f7f:[ ]+0f 25 2f d3 10 04[ ]+comnesd %xmm3,%xmm2,%xmm1 + [ ]+1f85:[ ]+0f 25 2f 52 10 04 04[ ]+comnesd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1f8c:[ ]+0f 25 2f d3 10 00[ ]+comeqsd %xmm3,%xmm2,%xmm1 + [ ]+1f92:[ ]+0f 25 2f d3 10 01[ ]+comltsd %xmm3,%xmm2,%xmm1 + [ ]+1f98:[ ]+0f 25 2f d3 10 02[ ]+comlesd %xmm3,%xmm2,%xmm1 + [ ]+1f9e:[ ]+0f 25 2f d3 10 03[ ]+comunordsd %xmm3,%xmm2,%xmm1 + [ ]+1fa4:[ ]+0f 25 2f d3 10 04[ ]+comnesd %xmm3,%xmm2,%xmm1 + [ ]+1faa:[ ]+0f 25 2f d3 10 05[ ]+comnltsd %xmm3,%xmm2,%xmm1 + [ ]+1fb0:[ ]+0f 25 2f d3 10 06[ ]+comnlesd %xmm3,%xmm2,%xmm1 + [ ]+1fb6:[ ]+0f 25 2f d3 10 07[ ]+comordsd %xmm3,%xmm2,%xmm1 + [ ]+1fbc:[ ]+0f 25 2f d3 10 08[ ]+comueqsd %xmm3,%xmm2,%xmm1 + [ ]+1fc2:[ ]+0f 25 2f d3 10 09[ ]+comultsd %xmm3,%xmm2,%xmm1 + [ ]+1fc8:[ ]+0f 25 2f d3 10 0a[ ]+comulesd %xmm3,%xmm2,%xmm1 + [ ]+1fce:[ ]+0f 25 2f d3 10 0b[ ]+comfalsesd %xmm3,%xmm2,%xmm1 + [ ]+1fd4:[ ]+0f 25 2f d3 10 0c[ ]+comunesd %xmm3,%xmm2,%xmm1 + [ ]+1fda:[ ]+0f 25 2f d3 10 0d[ ]+comunltsd %xmm3,%xmm2,%xmm1 + [ ]+1fe0:[ ]+0f 25 2f d3 10 0e[ ]+comunlesd %xmm3,%xmm2,%xmm1 + [ ]+1fe6:[ ]+0f 25 2f d3 10 0f[ ]+comtruesd %xmm3,%xmm2,%xmm1 + [ ]+1fec:[ ]+0f 25 2f 52 10 04 00[ ]+comeqsd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1ff3:[ ]+0f 25 2f 52 10 04 01[ ]+comltsd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+1ffa:[ ]+0f 25 2f 52 10 04 02[ ]+comlesd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2001:[ ]+0f 25 2f 52 10 04 03[ ]+comunordsd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2008:[ ]+0f 25 2f 52 10 04 04[ ]+comnesd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+200f:[ ]+0f 25 2f 52 10 04 05[ ]+comnltsd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2016:[ ]+0f 25 2f 52 10 04 06[ ]+comnlesd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+201d:[ ]+0f 25 2f 52 10 04 07[ ]+comordsd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2024:[ ]+0f 25 2f 52 10 04 08[ ]+comueqsd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+202b:[ ]+0f 25 2f 52 10 04 09[ ]+comultsd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2032:[ ]+0f 25 2f 52 10 04 0a[ ]+comulesd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2039:[ ]+0f 25 2f 52 10 04 0b[ ]+comfalsesd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2040:[ ]+0f 25 2f 52 10 04 0c[ ]+comunesd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2047:[ ]+0f 25 2f 52 10 04 0d[ ]+comunltsd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+204e:[ ]+0f 25 2f 52 10 04 0e[ ]+comunlesd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2055:[ ]+0f 25 2f 52 10 04 0f[ ]+comtruesd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+205c:[ ]+0f 25 2c d3 10 04[ ]+comneps %xmm3,%xmm2,%xmm1 + [ ]+2062:[ ]+0f 25 2c 52 10 04 04[ ]+comneps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2069:[ ]+0f 25 2c d3 10 00[ ]+comeqps %xmm3,%xmm2,%xmm1 + [ ]+206f:[ ]+0f 25 2c d3 10 01[ ]+comltps %xmm3,%xmm2,%xmm1 + [ ]+2075:[ ]+0f 25 2c d3 10 02[ ]+comleps %xmm3,%xmm2,%xmm1 + [ ]+207b:[ ]+0f 25 2c d3 10 03[ ]+comunordps %xmm3,%xmm2,%xmm1 + [ ]+2081:[ ]+0f 25 2c d3 10 04[ ]+comneps %xmm3,%xmm2,%xmm1 + [ ]+2087:[ ]+0f 25 2c d3 10 05[ ]+comnltps %xmm3,%xmm2,%xmm1 + [ ]+208d:[ ]+0f 25 2c d3 10 06[ ]+comnleps %xmm3,%xmm2,%xmm1 + [ ]+2093:[ ]+0f 25 2c d3 10 07[ ]+comordps %xmm3,%xmm2,%xmm1 + [ ]+2099:[ ]+0f 25 2c d3 10 08[ ]+comueqps %xmm3,%xmm2,%xmm1 + [ ]+209f:[ ]+0f 25 2c d3 10 09[ ]+comultps %xmm3,%xmm2,%xmm1 + [ ]+20a5:[ ]+0f 25 2c d3 10 0a[ ]+comuleps %xmm3,%xmm2,%xmm1 + [ ]+20ab:[ ]+0f 25 2c d3 10 0b[ ]+comfalseps %xmm3,%xmm2,%xmm1 + [ ]+20b1:[ ]+0f 25 2c d3 10 0c[ ]+comuneps %xmm3,%xmm2,%xmm1 + [ ]+20b7:[ ]+0f 25 2c d3 10 0d[ ]+comunltps %xmm3,%xmm2,%xmm1 + [ ]+20bd:[ ]+0f 25 2c d3 10 0e[ ]+comunleps %xmm3,%xmm2,%xmm1 + [ ]+20c3:[ ]+0f 25 2c d3 10 0f[ ]+comtrueps %xmm3,%xmm2,%xmm1 + [ ]+20c9:[ ]+0f 25 2c 52 10 04 00[ ]+comeqps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+20d0:[ ]+0f 25 2c 52 10 04 01[ ]+comltps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+20d7:[ ]+0f 25 2c 52 10 04 02[ ]+comleps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+20de:[ ]+0f 25 2c 52 10 04 03[ ]+comunordps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+20e5:[ ]+0f 25 2c 52 10 04 04[ ]+comneps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+20ec:[ ]+0f 25 2c 52 10 04 05[ ]+comnltps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+20f3:[ ]+0f 25 2c 52 10 04 06[ ]+comnleps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+20fa:[ ]+0f 25 2c 52 10 04 07[ ]+comordps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2101:[ ]+0f 25 2c 52 10 04 08[ ]+comueqps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2108:[ ]+0f 25 2c 52 10 04 09[ ]+comultps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+210f:[ ]+0f 25 2c 52 10 04 0a[ ]+comuleps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2116:[ ]+0f 25 2c 52 10 04 0b[ ]+comfalseps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+211d:[ ]+0f 25 2c 52 10 04 0c[ ]+comuneps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2124:[ ]+0f 25 2c 52 10 04 0d[ ]+comunltps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+212b:[ ]+0f 25 2c 52 10 04 0e[ ]+comunleps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2132:[ ]+0f 25 2c 52 10 04 0f[ ]+comtrueps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2139:[ ]+0f 25 2d d3 10 04[ ]+comnepd %xmm3,%xmm2,%xmm1 + [ ]+213f:[ ]+0f 25 2d 52 10 04 04[ ]+comnepd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2146:[ ]+0f 25 2d d3 10 00[ ]+comeqpd %xmm3,%xmm2,%xmm1 + [ ]+214c:[ ]+0f 25 2d d3 10 01[ ]+comltpd %xmm3,%xmm2,%xmm1 + [ ]+2152:[ ]+0f 25 2d d3 10 02[ ]+comlepd %xmm3,%xmm2,%xmm1 + [ ]+2158:[ ]+0f 25 2d d3 10 03[ ]+comunordpd %xmm3,%xmm2,%xmm1 + [ ]+215e:[ ]+0f 25 2d d3 10 04[ ]+comnepd %xmm3,%xmm2,%xmm1 + [ ]+2164:[ ]+0f 25 2d d3 10 05[ ]+comnltpd %xmm3,%xmm2,%xmm1 + [ ]+216a:[ ]+0f 25 2d d3 10 06[ ]+comnlepd %xmm3,%xmm2,%xmm1 + [ ]+2170:[ ]+0f 25 2d d3 10 07[ ]+comordpd %xmm3,%xmm2,%xmm1 + [ ]+2176:[ ]+0f 25 2d d3 10 08[ ]+comueqpd %xmm3,%xmm2,%xmm1 + [ ]+217c:[ ]+0f 25 2d d3 10 09[ ]+comultpd %xmm3,%xmm2,%xmm1 + [ ]+2182:[ ]+0f 25 2d d3 10 0a[ ]+comulepd %xmm3,%xmm2,%xmm1 + [ ]+2188:[ ]+0f 25 2d d3 10 0b[ ]+comfalsepd %xmm3,%xmm2,%xmm1 + [ ]+218e:[ ]+0f 25 2d d3 10 0c[ ]+comunepd %xmm3,%xmm2,%xmm1 + [ ]+2194:[ ]+0f 25 2d d3 10 0d[ ]+comunltpd %xmm3,%xmm2,%xmm1 + [ ]+219a:[ ]+0f 25 2d d3 10 0e[ ]+comunlepd %xmm3,%xmm2,%xmm1 + [ ]+21a0:[ ]+0f 25 2d d3 10 0f[ ]+comtruepd %xmm3,%xmm2,%xmm1 + [ ]+21a6:[ ]+0f 25 2d 52 10 04 00[ ]+comeqpd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+21ad:[ ]+0f 25 2d 52 10 04 01[ ]+comltpd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+21b4:[ ]+0f 25 2d 52 10 04 02[ ]+comlepd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+21bb:[ ]+0f 25 2d 52 10 04 03[ ]+comunordpd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+21c2:[ ]+0f 25 2d 52 10 04 04[ ]+comnepd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+21c9:[ ]+0f 25 2d 52 10 04 05[ ]+comnltpd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+21d0:[ ]+0f 25 2d 52 10 04 06[ ]+comnlepd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+21d7:[ ]+0f 25 2d 52 10 04 07[ ]+comordpd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+21de:[ ]+0f 25 2d 52 10 04 08[ ]+comueqpd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+21e5:[ ]+0f 25 2d 52 10 04 09[ ]+comultpd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+21ec:[ ]+0f 25 2d 52 10 04 0a[ ]+comulepd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+21f3:[ ]+0f 25 2d 52 10 04 0b[ ]+comfalsepd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+21fa:[ ]+0f 25 2d 52 10 04 0c[ ]+comunepd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2201:[ ]+0f 25 2d 52 10 04 0d[ ]+comunltpd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2208:[ ]+0f 25 2d 52 10 04 0e[ ]+comunlepd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+220f:[ ]+0f 25 2d 52 10 04 0f[ ]+comtruepd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2216:[ ]+0f 25 4c d3 10 04[ ]+pcomeqb %xmm3,%xmm2,%xmm1 + [ ]+221c:[ ]+0f 25 4c 52 10 04 04[ ]+pcomeqb 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2223:[ ]+0f 25 4c d3 10 00[ ]+pcomltb %xmm3,%xmm2,%xmm1 + [ ]+2229:[ ]+0f 25 4c d3 10 01[ ]+pcomleb %xmm3,%xmm2,%xmm1 + [ ]+222f:[ ]+0f 25 4c d3 10 02[ ]+pcomgtb %xmm3,%xmm2,%xmm1 + [ ]+2235:[ ]+0f 25 4c d3 10 03[ ]+pcomgeb %xmm3,%xmm2,%xmm1 + [ ]+223b:[ ]+0f 25 4c d3 10 04[ ]+pcomeqb %xmm3,%xmm2,%xmm1 + [ ]+2241:[ ]+0f 25 4c d3 10 05[ ]+pcomneb %xmm3,%xmm2,%xmm1 + [ ]+2247:[ ]+0f 25 4c 52 10 04 00[ ]+pcomltb 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+224e:[ ]+0f 25 4c 52 10 04 01[ ]+pcomleb 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2255:[ ]+0f 25 4c 52 10 04 02[ ]+pcomgtb 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+225c:[ ]+0f 25 4c 52 10 04 03[ ]+pcomgeb 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2263:[ ]+0f 25 4c 52 10 04 04[ ]+pcomeqb 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+226a:[ ]+0f 25 4c 52 10 04 05[ ]+pcomneb 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2271:[ ]+0f 25 4d d3 10 04[ ]+pcomeqw %xmm3,%xmm2,%xmm1 + [ ]+2277:[ ]+0f 25 4d 52 10 04 04[ ]+pcomeqw 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+227e:[ ]+0f 25 4d d3 10 00[ ]+pcomltw %xmm3,%xmm2,%xmm1 + [ ]+2284:[ ]+0f 25 4d d3 10 01[ ]+pcomlew %xmm3,%xmm2,%xmm1 + [ ]+228a:[ ]+0f 25 4d d3 10 02[ ]+pcomgtw %xmm3,%xmm2,%xmm1 + [ ]+2290:[ ]+0f 25 4d d3 10 03[ ]+pcomgew %xmm3,%xmm2,%xmm1 + [ ]+2296:[ ]+0f 25 4d d3 10 04[ ]+pcomeqw %xmm3,%xmm2,%xmm1 + [ ]+229c:[ ]+0f 25 4d d3 10 05[ ]+pcomnew %xmm3,%xmm2,%xmm1 + [ ]+22a2:[ ]+0f 25 4d 52 10 04 00[ ]+pcomltw 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+22a9:[ ]+0f 25 4d 52 10 04 01[ ]+pcomlew 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+22b0:[ ]+0f 25 4d 52 10 04 02[ ]+pcomgtw 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+22b7:[ ]+0f 25 4d 52 10 04 03[ ]+pcomgew 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+22be:[ ]+0f 25 4d 52 10 04 04[ ]+pcomeqw 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+22c5:[ ]+0f 25 4d 52 10 04 05[ ]+pcomnew 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+22cc:[ ]+0f 25 4e d3 10 04[ ]+pcomeqd %xmm3,%xmm2,%xmm1 + [ ]+22d2:[ ]+0f 25 4e 52 10 04 04[ ]+pcomeqd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+22d9:[ ]+0f 25 4e d3 10 00[ ]+pcomltd %xmm3,%xmm2,%xmm1 + [ ]+22df:[ ]+0f 25 4e d3 10 01[ ]+pcomled %xmm3,%xmm2,%xmm1 + [ ]+22e5:[ ]+0f 25 4e d3 10 02[ ]+pcomgtd %xmm3,%xmm2,%xmm1 + [ ]+22eb:[ ]+0f 25 4e d3 10 03[ ]+pcomged %xmm3,%xmm2,%xmm1 + [ ]+22f1:[ ]+0f 25 4e d3 10 04[ ]+pcomeqd %xmm3,%xmm2,%xmm1 + [ ]+22f7:[ ]+0f 25 4e d3 10 05[ ]+pcomned %xmm3,%xmm2,%xmm1 + [ ]+22fd:[ ]+0f 25 4e 52 10 04 00[ ]+pcomltd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2304:[ ]+0f 25 4e 52 10 04 01[ ]+pcomled 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+230b:[ ]+0f 25 4e 52 10 04 02[ ]+pcomgtd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2312:[ ]+0f 25 4e 52 10 04 03[ ]+pcomged 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2319:[ ]+0f 25 4e 52 10 04 04[ ]+pcomeqd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2320:[ ]+0f 25 4e 52 10 04 05[ ]+pcomned 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2327:[ ]+0f 25 4f d3 10 04[ ]+pcomeqq %xmm3,%xmm2,%xmm1 + [ ]+232d:[ ]+0f 25 4f 52 10 04 04[ ]+pcomeqq 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2334:[ ]+0f 25 4f d3 10 00[ ]+pcomltq %xmm3,%xmm2,%xmm1 + [ ]+233a:[ ]+0f 25 4f d3 10 01[ ]+pcomleq %xmm3,%xmm2,%xmm1 + [ ]+2340:[ ]+0f 25 4f d3 10 02[ ]+pcomgtq %xmm3,%xmm2,%xmm1 + [ ]+2346:[ ]+0f 25 4f d3 10 03[ ]+pcomgeq %xmm3,%xmm2,%xmm1 + [ ]+234c:[ ]+0f 25 4f d3 10 04[ ]+pcomeqq %xmm3,%xmm2,%xmm1 + [ ]+2352:[ ]+0f 25 4f d3 10 05[ ]+pcomneq %xmm3,%xmm2,%xmm1 + [ ]+2358:[ ]+0f 25 4f 52 10 04 00[ ]+pcomltq 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+235f:[ ]+0f 25 4f 52 10 04 01[ ]+pcomleq 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2366:[ ]+0f 25 4f 52 10 04 02[ ]+pcomgtq 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+236d:[ ]+0f 25 4f 52 10 04 03[ ]+pcomgeq 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2374:[ ]+0f 25 4f 52 10 04 04[ ]+pcomeqq 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+237b:[ ]+0f 25 4f 52 10 04 05[ ]+pcomneq 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2382:[ ]+0f 25 6c d3 10 04[ ]+pcomequb %xmm3,%xmm2,%xmm1 + [ ]+2388:[ ]+0f 25 6c 52 10 04 04[ ]+pcomequb 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+238f:[ ]+0f 25 6c d3 10 00[ ]+pcomltub %xmm3,%xmm2,%xmm1 + [ ]+2395:[ ]+0f 25 6c d3 10 01[ ]+pcomleub %xmm3,%xmm2,%xmm1 + [ ]+239b:[ ]+0f 25 6c d3 10 02[ ]+pcomgtub %xmm3,%xmm2,%xmm1 + [ ]+23a1:[ ]+0f 25 6c d3 10 03[ ]+pcomgeub %xmm3,%xmm2,%xmm1 + [ ]+23a7:[ ]+0f 25 6c d3 10 04[ ]+pcomequb %xmm3,%xmm2,%xmm1 + [ ]+23ad:[ ]+0f 25 6c d3 10 05[ ]+pcomneub %xmm3,%xmm2,%xmm1 + [ ]+23b3:[ ]+0f 25 6c 52 10 04 00[ ]+pcomltub 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+23ba:[ ]+0f 25 6c 52 10 04 01[ ]+pcomleub 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+23c1:[ ]+0f 25 6c 52 10 04 02[ ]+pcomgtub 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+23c8:[ ]+0f 25 6c 52 10 04 03[ ]+pcomgeub 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+23cf:[ ]+0f 25 6c 52 10 04 04[ ]+pcomequb 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+23d6:[ ]+0f 25 6c 52 10 04 05[ ]+pcomneub 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+23dd:[ ]+0f 25 6d d3 10 04[ ]+pcomequw %xmm3,%xmm2,%xmm1 + [ ]+23e3:[ ]+0f 25 6d 52 10 04 04[ ]+pcomequw 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+23ea:[ ]+0f 25 6d d3 10 00[ ]+pcomltuw %xmm3,%xmm2,%xmm1 + [ ]+23f0:[ ]+0f 25 6d d3 10 01[ ]+pcomleuw %xmm3,%xmm2,%xmm1 + [ ]+23f6:[ ]+0f 25 6d d3 10 02[ ]+pcomgtuw %xmm3,%xmm2,%xmm1 + [ ]+23fc:[ ]+0f 25 6d d3 10 03[ ]+pcomgeuw %xmm3,%xmm2,%xmm1 + [ ]+2402:[ ]+0f 25 6d d3 10 04[ ]+pcomequw %xmm3,%xmm2,%xmm1 + [ ]+2408:[ ]+0f 25 6d d3 10 05[ ]+pcomneuw %xmm3,%xmm2,%xmm1 + [ ]+240e:[ ]+0f 25 6d 52 10 04 00[ ]+pcomltuw 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2415:[ ]+0f 25 6d 52 10 04 01[ ]+pcomleuw 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+241c:[ ]+0f 25 6d 52 10 04 02[ ]+pcomgtuw 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2423:[ ]+0f 25 6d 52 10 04 03[ ]+pcomgeuw 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+242a:[ ]+0f 25 6d 52 10 04 04[ ]+pcomequw 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2431:[ ]+0f 25 6d 52 10 04 05[ ]+pcomneuw 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2438:[ ]+0f 25 6e d3 10 04[ ]+pcomequd %xmm3,%xmm2,%xmm1 + [ ]+243e:[ ]+0f 25 6e 52 10 04 04[ ]+pcomequd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2445:[ ]+0f 25 6e d3 10 00[ ]+pcomltud %xmm3,%xmm2,%xmm1 + [ ]+244b:[ ]+0f 25 6e d3 10 01[ ]+pcomleud %xmm3,%xmm2,%xmm1 + [ ]+2451:[ ]+0f 25 6e d3 10 02[ ]+pcomgtud %xmm3,%xmm2,%xmm1 + [ ]+2457:[ ]+0f 25 6e d3 10 03[ ]+pcomgeud %xmm3,%xmm2,%xmm1 + [ ]+245d:[ ]+0f 25 6e d3 10 04[ ]+pcomequd %xmm3,%xmm2,%xmm1 + [ ]+2463:[ ]+0f 25 6e d3 10 05[ ]+pcomneud %xmm3,%xmm2,%xmm1 + [ ]+2469:[ ]+0f 25 6e 52 10 04 00[ ]+pcomltud 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2470:[ ]+0f 25 6e 52 10 04 01[ ]+pcomleud 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2477:[ ]+0f 25 6e 52 10 04 02[ ]+pcomgtud 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+247e:[ ]+0f 25 6e 52 10 04 03[ ]+pcomgeud 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2485:[ ]+0f 25 6e 52 10 04 04[ ]+pcomequd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+248c:[ ]+0f 25 6e 52 10 04 05[ ]+pcomneud 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+2493:[ ]+0f 25 6f d3 10 04[ ]+pcomequq %xmm3,%xmm2,%xmm1 + [ ]+2499:[ ]+0f 25 6f 52 10 04 04[ ]+pcomequq 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+24a0:[ ]+0f 25 6f d3 10 00[ ]+pcomltuq %xmm3,%xmm2,%xmm1 + [ ]+24a6:[ ]+0f 25 6f d3 10 01[ ]+pcomleuq %xmm3,%xmm2,%xmm1 + [ ]+24ac:[ ]+0f 25 6f d3 10 02[ ]+pcomgtuq %xmm3,%xmm2,%xmm1 + [ ]+24b2:[ ]+0f 25 6f d3 10 03[ ]+pcomgeuq %xmm3,%xmm2,%xmm1 + [ ]+24b8:[ ]+0f 25 6f d3 10 04[ ]+pcomequq %xmm3,%xmm2,%xmm1 + [ ]+24be:[ ]+0f 25 6f d3 10 05[ ]+pcomneuq %xmm3,%xmm2,%xmm1 + [ ]+24c4:[ ]+0f 25 6f 52 10 04 00[ ]+pcomltuq 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+24cb:[ ]+0f 25 6f 52 10 04 01[ ]+pcomleuq 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+24d2:[ ]+0f 25 6f 52 10 04 02[ ]+pcomgtuq 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+24d9:[ ]+0f 25 6f 52 10 04 03[ ]+pcomgeuq 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+24e0:[ ]+0f 25 6f 52 10 04 04[ ]+pcomequq 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+24e7:[ ]+0f 25 6f 52 10 04 05[ ]+pcomneuq 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+24ee:[ ]+0f 25 2e e5 b5 04[ ]+comness %xmm13,%xmm12,%xmm11 + [ ]+24f4:[ ]+0f 25 2e a7 b5 00 00 10 00 04[ ]+comness 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+24fe:[ ]+0f 25 2e e5 b5 00[ ]+comeqss %xmm13,%xmm12,%xmm11 + [ ]+2504:[ ]+0f 25 2e e5 b5 01[ ]+comltss %xmm13,%xmm12,%xmm11 + [ ]+250a:[ ]+0f 25 2e e5 b5 02[ ]+comless %xmm13,%xmm12,%xmm11 + [ ]+2510:[ ]+0f 25 2e e5 b5 03[ ]+comunordss %xmm13,%xmm12,%xmm11 + [ ]+2516:[ ]+0f 25 2e e5 b5 04[ ]+comness %xmm13,%xmm12,%xmm11 + [ ]+251c:[ ]+0f 25 2e e5 b5 05[ ]+comnltss %xmm13,%xmm12,%xmm11 + [ ]+2522:[ ]+0f 25 2e e5 b5 06[ ]+comnless %xmm13,%xmm12,%xmm11 + [ ]+2528:[ ]+0f 25 2e e5 b5 07[ ]+comordss %xmm13,%xmm12,%xmm11 + [ ]+252e:[ ]+0f 25 2e e5 b5 08[ ]+comueqss %xmm13,%xmm12,%xmm11 + [ ]+2534:[ ]+0f 25 2e e5 b5 09[ ]+comultss %xmm13,%xmm12,%xmm11 + [ ]+253a:[ ]+0f 25 2e e5 b5 0a[ ]+comuless %xmm13,%xmm12,%xmm11 + [ ]+2540:[ ]+0f 25 2e e5 b5 0b[ ]+comfalsess %xmm13,%xmm12,%xmm11 + [ ]+2546:[ ]+0f 25 2e e5 b5 0c[ ]+comuness %xmm13,%xmm12,%xmm11 + [ ]+254c:[ ]+0f 25 2e e5 b5 0d[ ]+comunltss %xmm13,%xmm12,%xmm11 + [ ]+2552:[ ]+0f 25 2e e5 b5 0e[ ]+comunless %xmm13,%xmm12,%xmm11 + [ ]+2558:[ ]+0f 25 2e e5 b5 0f[ ]+comtruess %xmm13,%xmm12,%xmm11 + [ ]+255e:[ ]+0f 25 2e a7 b5 00 00 10 00 00[ ]+comeqss 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2568:[ ]+0f 25 2e a7 b5 00 00 10 00 01[ ]+comltss 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2572:[ ]+0f 25 2e a7 b5 00 00 10 00 02[ ]+comless 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+257c:[ ]+0f 25 2e a7 b5 00 00 10 00 03[ ]+comunordss 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2586:[ ]+0f 25 2e a7 b5 00 00 10 00 04[ ]+comness 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2590:[ ]+0f 25 2e a7 b5 00 00 10 00 05[ ]+comnltss 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+259a:[ ]+0f 25 2e a7 b5 00 00 10 00 06[ ]+comnless 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+25a4:[ ]+0f 25 2e a7 b5 00 00 10 00 07[ ]+comordss 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+25ae:[ ]+0f 25 2e a7 b5 00 00 10 00 08[ ]+comueqss 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+25b8:[ ]+0f 25 2e a7 b5 00 00 10 00 09[ ]+comultss 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+25c2:[ ]+0f 25 2e a7 b5 00 00 10 00 0a[ ]+comuless 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+25cc:[ ]+0f 25 2e a7 b5 00 00 10 00 0b[ ]+comfalsess 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+25d6:[ ]+0f 25 2e a7 b5 00 00 10 00 0c[ ]+comuness 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+25e0:[ ]+0f 25 2e a7 b5 00 00 10 00 0d[ ]+comunltss 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+25ea:[ ]+0f 25 2e a7 b5 00 00 10 00 0e[ ]+comunless 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+25f4:[ ]+0f 25 2e a7 b5 00 00 10 00 0f[ ]+comtruess 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+25fe:[ ]+0f 25 2f e5 b5 04[ ]+comnesd %xmm13,%xmm12,%xmm11 + [ ]+2604:[ ]+0f 25 2f a7 b5 00 00 10 00 04[ ]+comnesd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+260e:[ ]+0f 25 2f e5 b5 00[ ]+comeqsd %xmm13,%xmm12,%xmm11 + [ ]+2614:[ ]+0f 25 2f e5 b5 01[ ]+comltsd %xmm13,%xmm12,%xmm11 + [ ]+261a:[ ]+0f 25 2f e5 b5 02[ ]+comlesd %xmm13,%xmm12,%xmm11 + [ ]+2620:[ ]+0f 25 2f e5 b5 03[ ]+comunordsd %xmm13,%xmm12,%xmm11 + [ ]+2626:[ ]+0f 25 2f e5 b5 04[ ]+comnesd %xmm13,%xmm12,%xmm11 + [ ]+262c:[ ]+0f 25 2f e5 b5 05[ ]+comnltsd %xmm13,%xmm12,%xmm11 + [ ]+2632:[ ]+0f 25 2f e5 b5 06[ ]+comnlesd %xmm13,%xmm12,%xmm11 + [ ]+2638:[ ]+0f 25 2f e5 b5 07[ ]+comordsd %xmm13,%xmm12,%xmm11 + [ ]+263e:[ ]+0f 25 2f e5 b5 08[ ]+comueqsd %xmm13,%xmm12,%xmm11 + [ ]+2644:[ ]+0f 25 2f e5 b5 09[ ]+comultsd %xmm13,%xmm12,%xmm11 + [ ]+264a:[ ]+0f 25 2f e5 b5 0a[ ]+comulesd %xmm13,%xmm12,%xmm11 + [ ]+2650:[ ]+0f 25 2f e5 b5 0b[ ]+comfalsesd %xmm13,%xmm12,%xmm11 + [ ]+2656:[ ]+0f 25 2f e5 b5 0c[ ]+comunesd %xmm13,%xmm12,%xmm11 + [ ]+265c:[ ]+0f 25 2f e5 b5 0d[ ]+comunltsd %xmm13,%xmm12,%xmm11 + [ ]+2662:[ ]+0f 25 2f e5 b5 0e[ ]+comunlesd %xmm13,%xmm12,%xmm11 + [ ]+2668:[ ]+0f 25 2f e5 b5 0f[ ]+comtruesd %xmm13,%xmm12,%xmm11 + [ ]+266e:[ ]+0f 25 2f a7 b5 00 00 10 00 00[ ]+comeqsd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2678:[ ]+0f 25 2f a7 b5 00 00 10 00 01[ ]+comltsd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2682:[ ]+0f 25 2f a7 b5 00 00 10 00 02[ ]+comlesd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+268c:[ ]+0f 25 2f a7 b5 00 00 10 00 03[ ]+comunordsd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2696:[ ]+0f 25 2f a7 b5 00 00 10 00 04[ ]+comnesd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+26a0:[ ]+0f 25 2f a7 b5 00 00 10 00 05[ ]+comnltsd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+26aa:[ ]+0f 25 2f a7 b5 00 00 10 00 06[ ]+comnlesd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+26b4:[ ]+0f 25 2f a7 b5 00 00 10 00 07[ ]+comordsd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+26be:[ ]+0f 25 2f a7 b5 00 00 10 00 08[ ]+comueqsd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+26c8:[ ]+0f 25 2f a7 b5 00 00 10 00 09[ ]+comultsd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+26d2:[ ]+0f 25 2f a7 b5 00 00 10 00 0a[ ]+comulesd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+26dc:[ ]+0f 25 2f a7 b5 00 00 10 00 0b[ ]+comfalsesd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+26e6:[ ]+0f 25 2f a7 b5 00 00 10 00 0c[ ]+comunesd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+26f0:[ ]+0f 25 2f a7 b5 00 00 10 00 0d[ ]+comunltsd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+26fa:[ ]+0f 25 2f a7 b5 00 00 10 00 0e[ ]+comunlesd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2704:[ ]+0f 25 2f a7 b5 00 00 10 00 0f[ ]+comtruesd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+270e:[ ]+0f 25 2c e5 b5 04[ ]+comneps %xmm13,%xmm12,%xmm11 + [ ]+2714:[ ]+0f 25 2c a7 b5 00 00 10 00 04[ ]+comneps 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+271e:[ ]+0f 25 2c e5 b5 00[ ]+comeqps %xmm13,%xmm12,%xmm11 + [ ]+2724:[ ]+0f 25 2c e5 b5 01[ ]+comltps %xmm13,%xmm12,%xmm11 + [ ]+272a:[ ]+0f 25 2c e5 b5 02[ ]+comleps %xmm13,%xmm12,%xmm11 + [ ]+2730:[ ]+0f 25 2c e5 b5 03[ ]+comunordps %xmm13,%xmm12,%xmm11 + [ ]+2736:[ ]+0f 25 2c e5 b5 04[ ]+comneps %xmm13,%xmm12,%xmm11 + [ ]+273c:[ ]+0f 25 2c e5 b5 05[ ]+comnltps %xmm13,%xmm12,%xmm11 + [ ]+2742:[ ]+0f 25 2c e5 b5 06[ ]+comnleps %xmm13,%xmm12,%xmm11 + [ ]+2748:[ ]+0f 25 2c e5 b5 07[ ]+comordps %xmm13,%xmm12,%xmm11 + [ ]+274e:[ ]+0f 25 2c e5 b5 08[ ]+comueqps %xmm13,%xmm12,%xmm11 + [ ]+2754:[ ]+0f 25 2c e5 b5 09[ ]+comultps %xmm13,%xmm12,%xmm11 + [ ]+275a:[ ]+0f 25 2c e5 b5 0a[ ]+comuleps %xmm13,%xmm12,%xmm11 + [ ]+2760:[ ]+0f 25 2c e5 b5 0b[ ]+comfalseps %xmm13,%xmm12,%xmm11 + [ ]+2766:[ ]+0f 25 2c e5 b5 0c[ ]+comuneps %xmm13,%xmm12,%xmm11 + [ ]+276c:[ ]+0f 25 2c e5 b5 0d[ ]+comunltps %xmm13,%xmm12,%xmm11 + [ ]+2772:[ ]+0f 25 2c e5 b5 0e[ ]+comunleps %xmm13,%xmm12,%xmm11 + [ ]+2778:[ ]+0f 25 2c e5 b5 0f[ ]+comtrueps %xmm13,%xmm12,%xmm11 + [ ]+277e:[ ]+0f 25 2c a7 b5 00 00 10 00 00[ ]+comeqps 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2788:[ ]+0f 25 2c a7 b5 00 00 10 00 01[ ]+comltps 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2792:[ ]+0f 25 2c a7 b5 00 00 10 00 02[ ]+comleps 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+279c:[ ]+0f 25 2c a7 b5 00 00 10 00 03[ ]+comunordps 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+27a6:[ ]+0f 25 2c a7 b5 00 00 10 00 04[ ]+comneps 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+27b0:[ ]+0f 25 2c a7 b5 00 00 10 00 05[ ]+comnltps 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+27ba:[ ]+0f 25 2c a7 b5 00 00 10 00 06[ ]+comnleps 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+27c4:[ ]+0f 25 2c a7 b5 00 00 10 00 07[ ]+comordps 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+27ce:[ ]+0f 25 2c a7 b5 00 00 10 00 08[ ]+comueqps 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+27d8:[ ]+0f 25 2c a7 b5 00 00 10 00 09[ ]+comultps 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+27e2:[ ]+0f 25 2c a7 b5 00 00 10 00 0a[ ]+comuleps 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+27ec:[ ]+0f 25 2c a7 b5 00 00 10 00 0b[ ]+comfalseps 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+27f6:[ ]+0f 25 2c a7 b5 00 00 10 00 0c[ ]+comuneps 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2800:[ ]+0f 25 2c a7 b5 00 00 10 00 0d[ ]+comunltps 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+280a:[ ]+0f 25 2c a7 b5 00 00 10 00 0e[ ]+comunleps 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2814:[ ]+0f 25 2c a7 b5 00 00 10 00 0f[ ]+comtrueps 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+281e:[ ]+0f 25 2d e5 b5 04[ ]+comnepd %xmm13,%xmm12,%xmm11 + [ ]+2824:[ ]+0f 25 2d a7 b5 00 00 10 00 04[ ]+comnepd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+282e:[ ]+0f 25 2d e5 b5 00[ ]+comeqpd %xmm13,%xmm12,%xmm11 + [ ]+2834:[ ]+0f 25 2d e5 b5 01[ ]+comltpd %xmm13,%xmm12,%xmm11 + [ ]+283a:[ ]+0f 25 2d e5 b5 02[ ]+comlepd %xmm13,%xmm12,%xmm11 + [ ]+2840:[ ]+0f 25 2d e5 b5 03[ ]+comunordpd %xmm13,%xmm12,%xmm11 + [ ]+2846:[ ]+0f 25 2d e5 b5 04[ ]+comnepd %xmm13,%xmm12,%xmm11 + [ ]+284c:[ ]+0f 25 2d e5 b5 05[ ]+comnltpd %xmm13,%xmm12,%xmm11 + [ ]+2852:[ ]+0f 25 2d e5 b5 06[ ]+comnlepd %xmm13,%xmm12,%xmm11 + [ ]+2858:[ ]+0f 25 2d e5 b5 07[ ]+comordpd %xmm13,%xmm12,%xmm11 + [ ]+285e:[ ]+0f 25 2d e5 b5 08[ ]+comueqpd %xmm13,%xmm12,%xmm11 + [ ]+2864:[ ]+0f 25 2d e5 b5 09[ ]+comultpd %xmm13,%xmm12,%xmm11 + [ ]+286a:[ ]+0f 25 2d e5 b5 0a[ ]+comulepd %xmm13,%xmm12,%xmm11 + [ ]+2870:[ ]+0f 25 2d e5 b5 0b[ ]+comfalsepd %xmm13,%xmm12,%xmm11 + [ ]+2876:[ ]+0f 25 2d e5 b5 0c[ ]+comunepd %xmm13,%xmm12,%xmm11 + [ ]+287c:[ ]+0f 25 2d e5 b5 0d[ ]+comunltpd %xmm13,%xmm12,%xmm11 + [ ]+2882:[ ]+0f 25 2d e5 b5 0e[ ]+comunlepd %xmm13,%xmm12,%xmm11 + [ ]+2888:[ ]+0f 25 2d e5 b5 0f[ ]+comtruepd %xmm13,%xmm12,%xmm11 + [ ]+288e:[ ]+0f 25 2d a7 b5 00 00 10 00 00[ ]+comeqpd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2898:[ ]+0f 25 2d a7 b5 00 00 10 00 01[ ]+comltpd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+28a2:[ ]+0f 25 2d a7 b5 00 00 10 00 02[ ]+comlepd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+28ac:[ ]+0f 25 2d a7 b5 00 00 10 00 03[ ]+comunordpd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+28b6:[ ]+0f 25 2d a7 b5 00 00 10 00 04[ ]+comnepd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+28c0:[ ]+0f 25 2d a7 b5 00 00 10 00 05[ ]+comnltpd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+28ca:[ ]+0f 25 2d a7 b5 00 00 10 00 06[ ]+comnlepd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+28d4:[ ]+0f 25 2d a7 b5 00 00 10 00 07[ ]+comordpd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+28de:[ ]+0f 25 2d a7 b5 00 00 10 00 08[ ]+comueqpd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+28e8:[ ]+0f 25 2d a7 b5 00 00 10 00 09[ ]+comultpd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+28f2:[ ]+0f 25 2d a7 b5 00 00 10 00 0a[ ]+comulepd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+28fc:[ ]+0f 25 2d a7 b5 00 00 10 00 0b[ ]+comfalsepd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2906:[ ]+0f 25 2d a7 b5 00 00 10 00 0c[ ]+comunepd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2910:[ ]+0f 25 2d a7 b5 00 00 10 00 0d[ ]+comunltpd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+291a:[ ]+0f 25 2d a7 b5 00 00 10 00 0e[ ]+comunlepd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2924:[ ]+0f 25 2d a7 b5 00 00 10 00 0f[ ]+comtruepd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+292e:[ ]+0f 25 4c e5 b5 04[ ]+pcomeqb %xmm13,%xmm12,%xmm11 + [ ]+2934:[ ]+0f 25 4c a7 b5 00 00 10 00 04[ ]+pcomeqb 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+293e:[ ]+0f 25 4c e5 b5 00[ ]+pcomltb %xmm13,%xmm12,%xmm11 + [ ]+2944:[ ]+0f 25 4c e5 b5 01[ ]+pcomleb %xmm13,%xmm12,%xmm11 + [ ]+294a:[ ]+0f 25 4c e5 b5 02[ ]+pcomgtb %xmm13,%xmm12,%xmm11 + [ ]+2950:[ ]+0f 25 4c e5 b5 03[ ]+pcomgeb %xmm13,%xmm12,%xmm11 + [ ]+2956:[ ]+0f 25 4c e5 b5 04[ ]+pcomeqb %xmm13,%xmm12,%xmm11 + [ ]+295c:[ ]+0f 25 4c e5 b5 05[ ]+pcomneb %xmm13,%xmm12,%xmm11 + [ ]+2962:[ ]+0f 25 4c a7 b5 00 00 10 00 00[ ]+pcomltb 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+296c:[ ]+0f 25 4c a7 b5 00 00 10 00 01[ ]+pcomleb 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2976:[ ]+0f 25 4c a7 b5 00 00 10 00 02[ ]+pcomgtb 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2980:[ ]+0f 25 4c a7 b5 00 00 10 00 03[ ]+pcomgeb 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+298a:[ ]+0f 25 4c a7 b5 00 00 10 00 04[ ]+pcomeqb 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2994:[ ]+0f 25 4c a7 b5 00 00 10 00 05[ ]+pcomneb 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+299e:[ ]+0f 25 4d e5 b5 04[ ]+pcomeqw %xmm13,%xmm12,%xmm11 + [ ]+29a4:[ ]+0f 25 4d a7 b5 00 00 10 00 04[ ]+pcomeqw 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+29ae:[ ]+0f 25 4d e5 b5 00[ ]+pcomltw %xmm13,%xmm12,%xmm11 + [ ]+29b4:[ ]+0f 25 4d e5 b5 01[ ]+pcomlew %xmm13,%xmm12,%xmm11 + [ ]+29ba:[ ]+0f 25 4d e5 b5 02[ ]+pcomgtw %xmm13,%xmm12,%xmm11 + [ ]+29c0:[ ]+0f 25 4d e5 b5 03[ ]+pcomgew %xmm13,%xmm12,%xmm11 + [ ]+29c6:[ ]+0f 25 4d e5 b5 04[ ]+pcomeqw %xmm13,%xmm12,%xmm11 + [ ]+29cc:[ ]+0f 25 4d e5 b5 05[ ]+pcomnew %xmm13,%xmm12,%xmm11 + [ ]+29d2:[ ]+0f 25 4d a7 b5 00 00 10 00 00[ ]+pcomltw 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+29dc:[ ]+0f 25 4d a7 b5 00 00 10 00 01[ ]+pcomlew 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+29e6:[ ]+0f 25 4d a7 b5 00 00 10 00 02[ ]+pcomgtw 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+29f0:[ ]+0f 25 4d a7 b5 00 00 10 00 03[ ]+pcomgew 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+29fa:[ ]+0f 25 4d a7 b5 00 00 10 00 04[ ]+pcomeqw 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2a04:[ ]+0f 25 4d a7 b5 00 00 10 00 05[ ]+pcomnew 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2a0e:[ ]+0f 25 4e e5 b5 04[ ]+pcomeqd %xmm13,%xmm12,%xmm11 + [ ]+2a14:[ ]+0f 25 4e a7 b5 00 00 10 00 04[ ]+pcomeqd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2a1e:[ ]+0f 25 4e e5 b5 00[ ]+pcomltd %xmm13,%xmm12,%xmm11 + [ ]+2a24:[ ]+0f 25 4e e5 b5 01[ ]+pcomled %xmm13,%xmm12,%xmm11 + [ ]+2a2a:[ ]+0f 25 4e e5 b5 02[ ]+pcomgtd %xmm13,%xmm12,%xmm11 + [ ]+2a30:[ ]+0f 25 4e e5 b5 03[ ]+pcomged %xmm13,%xmm12,%xmm11 + [ ]+2a36:[ ]+0f 25 4e e5 b5 04[ ]+pcomeqd %xmm13,%xmm12,%xmm11 + [ ]+2a3c:[ ]+0f 25 4e e5 b5 05[ ]+pcomned %xmm13,%xmm12,%xmm11 + [ ]+2a42:[ ]+0f 25 4e a7 b5 00 00 10 00 00[ ]+pcomltd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2a4c:[ ]+0f 25 4e a7 b5 00 00 10 00 01[ ]+pcomled 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2a56:[ ]+0f 25 4e a7 b5 00 00 10 00 02[ ]+pcomgtd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2a60:[ ]+0f 25 4e a7 b5 00 00 10 00 03[ ]+pcomged 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2a6a:[ ]+0f 25 4e a7 b5 00 00 10 00 04[ ]+pcomeqd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2a74:[ ]+0f 25 4e a7 b5 00 00 10 00 05[ ]+pcomned 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2a7e:[ ]+0f 25 4f e5 b5 04[ ]+pcomeqq %xmm13,%xmm12,%xmm11 + [ ]+2a84:[ ]+0f 25 4f a7 b5 00 00 10 00 04[ ]+pcomeqq 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2a8e:[ ]+0f 25 4f e5 b5 00[ ]+pcomltq %xmm13,%xmm12,%xmm11 + [ ]+2a94:[ ]+0f 25 4f e5 b5 01[ ]+pcomleq %xmm13,%xmm12,%xmm11 + [ ]+2a9a:[ ]+0f 25 4f e5 b5 02[ ]+pcomgtq %xmm13,%xmm12,%xmm11 + [ ]+2aa0:[ ]+0f 25 4f e5 b5 03[ ]+pcomgeq %xmm13,%xmm12,%xmm11 + [ ]+2aa6:[ ]+0f 25 4f e5 b5 04[ ]+pcomeqq %xmm13,%xmm12,%xmm11 + [ ]+2aac:[ ]+0f 25 4f e5 b5 05[ ]+pcomneq %xmm13,%xmm12,%xmm11 + [ ]+2ab2:[ ]+0f 25 4f a7 b5 00 00 10 00 00[ ]+pcomltq 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2abc:[ ]+0f 25 4f a7 b5 00 00 10 00 01[ ]+pcomleq 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2ac6:[ ]+0f 25 4f a7 b5 00 00 10 00 02[ ]+pcomgtq 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2ad0:[ ]+0f 25 4f a7 b5 00 00 10 00 03[ ]+pcomgeq 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2ada:[ ]+0f 25 4f a7 b5 00 00 10 00 04[ ]+pcomeqq 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2ae4:[ ]+0f 25 4f a7 b5 00 00 10 00 05[ ]+pcomneq 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2aee:[ ]+0f 25 6c e5 b5 04[ ]+pcomequb %xmm13,%xmm12,%xmm11 + [ ]+2af4:[ ]+0f 25 6c a7 b5 00 00 10 00 04[ ]+pcomequb 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2afe:[ ]+0f 25 6c e5 b5 00[ ]+pcomltub %xmm13,%xmm12,%xmm11 + [ ]+2b04:[ ]+0f 25 6c e5 b5 01[ ]+pcomleub %xmm13,%xmm12,%xmm11 + [ ]+2b0a:[ ]+0f 25 6c e5 b5 02[ ]+pcomgtub %xmm13,%xmm12,%xmm11 + [ ]+2b10:[ ]+0f 25 6c e5 b5 03[ ]+pcomgeub %xmm13,%xmm12,%xmm11 + [ ]+2b16:[ ]+0f 25 6c e5 b5 04[ ]+pcomequb %xmm13,%xmm12,%xmm11 + [ ]+2b1c:[ ]+0f 25 6c e5 b5 05[ ]+pcomneub %xmm13,%xmm12,%xmm11 + [ ]+2b22:[ ]+0f 25 6c a7 b5 00 00 10 00 00[ ]+pcomltub 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2b2c:[ ]+0f 25 6c a7 b5 00 00 10 00 01[ ]+pcomleub 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2b36:[ ]+0f 25 6c a7 b5 00 00 10 00 02[ ]+pcomgtub 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2b40:[ ]+0f 25 6c a7 b5 00 00 10 00 03[ ]+pcomgeub 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2b4a:[ ]+0f 25 6c a7 b5 00 00 10 00 04[ ]+pcomequb 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2b54:[ ]+0f 25 6c a7 b5 00 00 10 00 05[ ]+pcomneub 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2b5e:[ ]+0f 25 6d e5 b5 04[ ]+pcomequw %xmm13,%xmm12,%xmm11 + [ ]+2b64:[ ]+0f 25 6d a7 b5 00 00 10 00 04[ ]+pcomequw 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2b6e:[ ]+0f 25 6d e5 b5 00[ ]+pcomltuw %xmm13,%xmm12,%xmm11 + [ ]+2b74:[ ]+0f 25 6d e5 b5 01[ ]+pcomleuw %xmm13,%xmm12,%xmm11 + [ ]+2b7a:[ ]+0f 25 6d e5 b5 02[ ]+pcomgtuw %xmm13,%xmm12,%xmm11 + [ ]+2b80:[ ]+0f 25 6d e5 b5 03[ ]+pcomgeuw %xmm13,%xmm12,%xmm11 + [ ]+2b86:[ ]+0f 25 6d e5 b5 04[ ]+pcomequw %xmm13,%xmm12,%xmm11 + [ ]+2b8c:[ ]+0f 25 6d e5 b5 05[ ]+pcomneuw %xmm13,%xmm12,%xmm11 + [ ]+2b92:[ ]+0f 25 6d a7 b5 00 00 10 00 00[ ]+pcomltuw 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2b9c:[ ]+0f 25 6d a7 b5 00 00 10 00 01[ ]+pcomleuw 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2ba6:[ ]+0f 25 6d a7 b5 00 00 10 00 02[ ]+pcomgtuw 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2bb0:[ ]+0f 25 6d a7 b5 00 00 10 00 03[ ]+pcomgeuw 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2bba:[ ]+0f 25 6d a7 b5 00 00 10 00 04[ ]+pcomequw 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2bc4:[ ]+0f 25 6d a7 b5 00 00 10 00 05[ ]+pcomneuw 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2bce:[ ]+0f 25 6e e5 b5 04[ ]+pcomequd %xmm13,%xmm12,%xmm11 + [ ]+2bd4:[ ]+0f 25 6e a7 b5 00 00 10 00 04[ ]+pcomequd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2bde:[ ]+0f 25 6e e5 b5 00[ ]+pcomltud %xmm13,%xmm12,%xmm11 + [ ]+2be4:[ ]+0f 25 6e e5 b5 01[ ]+pcomleud %xmm13,%xmm12,%xmm11 + [ ]+2bea:[ ]+0f 25 6e e5 b5 02[ ]+pcomgtud %xmm13,%xmm12,%xmm11 + [ ]+2bf0:[ ]+0f 25 6e e5 b5 03[ ]+pcomgeud %xmm13,%xmm12,%xmm11 + [ ]+2bf6:[ ]+0f 25 6e e5 b5 04[ ]+pcomequd %xmm13,%xmm12,%xmm11 + [ ]+2bfc:[ ]+0f 25 6e e5 b5 05[ ]+pcomneud %xmm13,%xmm12,%xmm11 + [ ]+2c02:[ ]+0f 25 6e a7 b5 00 00 10 00 00[ ]+pcomltud 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2c0c:[ ]+0f 25 6e a7 b5 00 00 10 00 01[ ]+pcomleud 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2c16:[ ]+0f 25 6e a7 b5 00 00 10 00 02[ ]+pcomgtud 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2c20:[ ]+0f 25 6e a7 b5 00 00 10 00 03[ ]+pcomgeud 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2c2a:[ ]+0f 25 6e a7 b5 00 00 10 00 04[ ]+pcomequd 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2c34:[ ]+0f 25 6e a7 b5 00 00 10 00 05[ ]+pcomneud 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2c3e:[ ]+0f 25 6f e5 b5 04[ ]+pcomequq %xmm13,%xmm12,%xmm11 + [ ]+2c44:[ ]+0f 25 6f a7 b5 00 00 10 00 04[ ]+pcomequq 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2c4e:[ ]+0f 25 6f e5 b5 00[ ]+pcomltuq %xmm13,%xmm12,%xmm11 + [ ]+2c54:[ ]+0f 25 6f e5 b5 01[ ]+pcomleuq %xmm13,%xmm12,%xmm11 + [ ]+2c5a:[ ]+0f 25 6f e5 b5 02[ ]+pcomgtuq %xmm13,%xmm12,%xmm11 + [ ]+2c60:[ ]+0f 25 6f e5 b5 03[ ]+pcomgeuq %xmm13,%xmm12,%xmm11 + [ ]+2c66:[ ]+0f 25 6f e5 b5 04[ ]+pcomequq %xmm13,%xmm12,%xmm11 + [ ]+2c6c:[ ]+0f 25 6f e5 b5 05[ ]+pcomneuq %xmm13,%xmm12,%xmm11 + [ ]+2c72:[ ]+0f 25 6f a7 b5 00 00 10 00 00[ ]+pcomltuq 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2c7c:[ ]+0f 25 6f a7 b5 00 00 10 00 01[ ]+pcomleuq 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2c86:[ ]+0f 25 6f a7 b5 00 00 10 00 02[ ]+pcomgtuq 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2c90:[ ]+0f 25 6f a7 b5 00 00 10 00 03[ ]+pcomgeuq 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2c9a:[ ]+0f 25 6f a7 b5 00 00 10 00 04[ ]+pcomequq 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2ca4:[ ]+0f 25 6f a7 b5 00 00 10 00 05[ ]+pcomneuq 0x100000\(%r15\),%xmm12,%xmm11 + [ ]+2cae:[ ]+0f 25 2e e3 14 04[ ]+comness %xmm3,%xmm12,%xmm1 + [ ]+2cb4:[ ]+0f 25 2e 62 14 04 04[ ]+comness 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2cbb:[ ]+0f 25 2e e3 14 00[ ]+comeqss %xmm3,%xmm12,%xmm1 + [ ]+2cc1:[ ]+0f 25 2e e3 14 01[ ]+comltss %xmm3,%xmm12,%xmm1 + [ ]+2cc7:[ ]+0f 25 2e e3 14 02[ ]+comless %xmm3,%xmm12,%xmm1 + [ ]+2ccd:[ ]+0f 25 2e e3 14 03[ ]+comunordss %xmm3,%xmm12,%xmm1 + [ ]+2cd3:[ ]+0f 25 2e e3 14 04[ ]+comness %xmm3,%xmm12,%xmm1 + [ ]+2cd9:[ ]+0f 25 2e e3 14 05[ ]+comnltss %xmm3,%xmm12,%xmm1 + [ ]+2cdf:[ ]+0f 25 2e e3 14 06[ ]+comnless %xmm3,%xmm12,%xmm1 + [ ]+2ce5:[ ]+0f 25 2e e3 14 07[ ]+comordss %xmm3,%xmm12,%xmm1 + [ ]+2ceb:[ ]+0f 25 2e e3 14 08[ ]+comueqss %xmm3,%xmm12,%xmm1 + [ ]+2cf1:[ ]+0f 25 2e e3 14 09[ ]+comultss %xmm3,%xmm12,%xmm1 + [ ]+2cf7:[ ]+0f 25 2e e3 14 0a[ ]+comuless %xmm3,%xmm12,%xmm1 + [ ]+2cfd:[ ]+0f 25 2e e3 14 0b[ ]+comfalsess %xmm3,%xmm12,%xmm1 + [ ]+2d03:[ ]+0f 25 2e e3 14 0c[ ]+comuness %xmm3,%xmm12,%xmm1 + [ ]+2d09:[ ]+0f 25 2e e3 14 0d[ ]+comunltss %xmm3,%xmm12,%xmm1 + [ ]+2d0f:[ ]+0f 25 2e e3 14 0e[ ]+comunless %xmm3,%xmm12,%xmm1 + [ ]+2d15:[ ]+0f 25 2e e3 14 0f[ ]+comtruess %xmm3,%xmm12,%xmm1 + [ ]+2d1b:[ ]+0f 25 2e 62 14 04 00[ ]+comeqss 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2d22:[ ]+0f 25 2e 62 14 04 01[ ]+comltss 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2d29:[ ]+0f 25 2e 62 14 04 02[ ]+comless 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2d30:[ ]+0f 25 2e 62 14 04 03[ ]+comunordss 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2d37:[ ]+0f 25 2e 62 14 04 04[ ]+comness 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2d3e:[ ]+0f 25 2e 62 14 04 05[ ]+comnltss 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2d45:[ ]+0f 25 2e 62 14 04 06[ ]+comnless 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2d4c:[ ]+0f 25 2e 62 14 04 07[ ]+comordss 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2d53:[ ]+0f 25 2e 62 14 04 08[ ]+comueqss 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2d5a:[ ]+0f 25 2e 62 14 04 09[ ]+comultss 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2d61:[ ]+0f 25 2e 62 14 04 0a[ ]+comuless 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2d68:[ ]+0f 25 2e 62 14 04 0b[ ]+comfalsess 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2d6f:[ ]+0f 25 2e 62 14 04 0c[ ]+comuness 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2d76:[ ]+0f 25 2e 62 14 04 0d[ ]+comunltss 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2d7d:[ ]+0f 25 2e 62 14 04 0e[ ]+comunless 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2d84:[ ]+0f 25 2e 62 14 04 0f[ ]+comtruess 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2d8b:[ ]+0f 25 2f e3 14 04[ ]+comnesd %xmm3,%xmm12,%xmm1 + [ ]+2d91:[ ]+0f 25 2f 62 14 04 04[ ]+comnesd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2d98:[ ]+0f 25 2f e3 14 00[ ]+comeqsd %xmm3,%xmm12,%xmm1 + [ ]+2d9e:[ ]+0f 25 2f e3 14 01[ ]+comltsd %xmm3,%xmm12,%xmm1 + [ ]+2da4:[ ]+0f 25 2f e3 14 02[ ]+comlesd %xmm3,%xmm12,%xmm1 + [ ]+2daa:[ ]+0f 25 2f e3 14 03[ ]+comunordsd %xmm3,%xmm12,%xmm1 + [ ]+2db0:[ ]+0f 25 2f e3 14 04[ ]+comnesd %xmm3,%xmm12,%xmm1 + [ ]+2db6:[ ]+0f 25 2f e3 14 05[ ]+comnltsd %xmm3,%xmm12,%xmm1 + [ ]+2dbc:[ ]+0f 25 2f e3 14 06[ ]+comnlesd %xmm3,%xmm12,%xmm1 + [ ]+2dc2:[ ]+0f 25 2f e3 14 07[ ]+comordsd %xmm3,%xmm12,%xmm1 + [ ]+2dc8:[ ]+0f 25 2f e3 14 08[ ]+comueqsd %xmm3,%xmm12,%xmm1 + [ ]+2dce:[ ]+0f 25 2f e3 14 09[ ]+comultsd %xmm3,%xmm12,%xmm1 + [ ]+2dd4:[ ]+0f 25 2f e3 14 0a[ ]+comulesd %xmm3,%xmm12,%xmm1 + [ ]+2dda:[ ]+0f 25 2f e3 14 0b[ ]+comfalsesd %xmm3,%xmm12,%xmm1 + [ ]+2de0:[ ]+0f 25 2f e3 14 0c[ ]+comunesd %xmm3,%xmm12,%xmm1 + [ ]+2de6:[ ]+0f 25 2f e3 14 0d[ ]+comunltsd %xmm3,%xmm12,%xmm1 + [ ]+2dec:[ ]+0f 25 2f e3 14 0e[ ]+comunlesd %xmm3,%xmm12,%xmm1 + [ ]+2df2:[ ]+0f 25 2f e3 14 0f[ ]+comtruesd %xmm3,%xmm12,%xmm1 + [ ]+2df8:[ ]+0f 25 2f 62 14 04 00[ ]+comeqsd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2dff:[ ]+0f 25 2f 62 14 04 01[ ]+comltsd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2e06:[ ]+0f 25 2f 62 14 04 02[ ]+comlesd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2e0d:[ ]+0f 25 2f 62 14 04 03[ ]+comunordsd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2e14:[ ]+0f 25 2f 62 14 04 04[ ]+comnesd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2e1b:[ ]+0f 25 2f 62 14 04 05[ ]+comnltsd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2e22:[ ]+0f 25 2f 62 14 04 06[ ]+comnlesd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2e29:[ ]+0f 25 2f 62 14 04 07[ ]+comordsd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2e30:[ ]+0f 25 2f 62 14 04 08[ ]+comueqsd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2e37:[ ]+0f 25 2f 62 14 04 09[ ]+comultsd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2e3e:[ ]+0f 25 2f 62 14 04 0a[ ]+comulesd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2e45:[ ]+0f 25 2f 62 14 04 0b[ ]+comfalsesd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2e4c:[ ]+0f 25 2f 62 14 04 0c[ ]+comunesd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2e53:[ ]+0f 25 2f 62 14 04 0d[ ]+comunltsd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2e5a:[ ]+0f 25 2f 62 14 04 0e[ ]+comunlesd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2e61:[ ]+0f 25 2f 62 14 04 0f[ ]+comtruesd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2e68:[ ]+0f 25 2c e3 14 04[ ]+comneps %xmm3,%xmm12,%xmm1 + [ ]+2e6e:[ ]+0f 25 2c 62 14 04 04[ ]+comneps 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2e75:[ ]+0f 25 2c e3 14 00[ ]+comeqps %xmm3,%xmm12,%xmm1 + [ ]+2e7b:[ ]+0f 25 2c e3 14 01[ ]+comltps %xmm3,%xmm12,%xmm1 + [ ]+2e81:[ ]+0f 25 2c e3 14 02[ ]+comleps %xmm3,%xmm12,%xmm1 + [ ]+2e87:[ ]+0f 25 2c e3 14 03[ ]+comunordps %xmm3,%xmm12,%xmm1 + [ ]+2e8d:[ ]+0f 25 2c e3 14 04[ ]+comneps %xmm3,%xmm12,%xmm1 + [ ]+2e93:[ ]+0f 25 2c e3 14 05[ ]+comnltps %xmm3,%xmm12,%xmm1 + [ ]+2e99:[ ]+0f 25 2c e3 14 06[ ]+comnleps %xmm3,%xmm12,%xmm1 + [ ]+2e9f:[ ]+0f 25 2c e3 14 07[ ]+comordps %xmm3,%xmm12,%xmm1 + [ ]+2ea5:[ ]+0f 25 2c e3 14 08[ ]+comueqps %xmm3,%xmm12,%xmm1 + [ ]+2eab:[ ]+0f 25 2c e3 14 09[ ]+comultps %xmm3,%xmm12,%xmm1 + [ ]+2eb1:[ ]+0f 25 2c e3 14 0a[ ]+comuleps %xmm3,%xmm12,%xmm1 + [ ]+2eb7:[ ]+0f 25 2c e3 14 0b[ ]+comfalseps %xmm3,%xmm12,%xmm1 + [ ]+2ebd:[ ]+0f 25 2c e3 14 0c[ ]+comuneps %xmm3,%xmm12,%xmm1 + [ ]+2ec3:[ ]+0f 25 2c e3 14 0d[ ]+comunltps %xmm3,%xmm12,%xmm1 + [ ]+2ec9:[ ]+0f 25 2c e3 14 0e[ ]+comunleps %xmm3,%xmm12,%xmm1 + [ ]+2ecf:[ ]+0f 25 2c e3 14 0f[ ]+comtrueps %xmm3,%xmm12,%xmm1 + [ ]+2ed5:[ ]+0f 25 2c 62 14 04 00[ ]+comeqps 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2edc:[ ]+0f 25 2c 62 14 04 01[ ]+comltps 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2ee3:[ ]+0f 25 2c 62 14 04 02[ ]+comleps 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2eea:[ ]+0f 25 2c 62 14 04 03[ ]+comunordps 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2ef1:[ ]+0f 25 2c 62 14 04 04[ ]+comneps 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2ef8:[ ]+0f 25 2c 62 14 04 05[ ]+comnltps 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2eff:[ ]+0f 25 2c 62 14 04 06[ ]+comnleps 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2f06:[ ]+0f 25 2c 62 14 04 07[ ]+comordps 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2f0d:[ ]+0f 25 2c 62 14 04 08[ ]+comueqps 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2f14:[ ]+0f 25 2c 62 14 04 09[ ]+comultps 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2f1b:[ ]+0f 25 2c 62 14 04 0a[ ]+comuleps 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2f22:[ ]+0f 25 2c 62 14 04 0b[ ]+comfalseps 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2f29:[ ]+0f 25 2c 62 14 04 0c[ ]+comuneps 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2f30:[ ]+0f 25 2c 62 14 04 0d[ ]+comunltps 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2f37:[ ]+0f 25 2c 62 14 04 0e[ ]+comunleps 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2f3e:[ ]+0f 25 2c 62 14 04 0f[ ]+comtrueps 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2f45:[ ]+0f 25 2d e3 14 04[ ]+comnepd %xmm3,%xmm12,%xmm1 + [ ]+2f4b:[ ]+0f 25 2d 62 14 04 04[ ]+comnepd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2f52:[ ]+0f 25 2d e3 14 00[ ]+comeqpd %xmm3,%xmm12,%xmm1 + [ ]+2f58:[ ]+0f 25 2d e3 14 01[ ]+comltpd %xmm3,%xmm12,%xmm1 + [ ]+2f5e:[ ]+0f 25 2d e3 14 02[ ]+comlepd %xmm3,%xmm12,%xmm1 + [ ]+2f64:[ ]+0f 25 2d e3 14 03[ ]+comunordpd %xmm3,%xmm12,%xmm1 + [ ]+2f6a:[ ]+0f 25 2d e3 14 04[ ]+comnepd %xmm3,%xmm12,%xmm1 + [ ]+2f70:[ ]+0f 25 2d e3 14 05[ ]+comnltpd %xmm3,%xmm12,%xmm1 + [ ]+2f76:[ ]+0f 25 2d e3 14 06[ ]+comnlepd %xmm3,%xmm12,%xmm1 + [ ]+2f7c:[ ]+0f 25 2d e3 14 07[ ]+comordpd %xmm3,%xmm12,%xmm1 + [ ]+2f82:[ ]+0f 25 2d e3 14 08[ ]+comueqpd %xmm3,%xmm12,%xmm1 + [ ]+2f88:[ ]+0f 25 2d e3 14 09[ ]+comultpd %xmm3,%xmm12,%xmm1 + [ ]+2f8e:[ ]+0f 25 2d e3 14 0a[ ]+comulepd %xmm3,%xmm12,%xmm1 + [ ]+2f94:[ ]+0f 25 2d e3 14 0b[ ]+comfalsepd %xmm3,%xmm12,%xmm1 + [ ]+2f9a:[ ]+0f 25 2d e3 14 0c[ ]+comunepd %xmm3,%xmm12,%xmm1 + [ ]+2fa0:[ ]+0f 25 2d e3 14 0d[ ]+comunltpd %xmm3,%xmm12,%xmm1 + [ ]+2fa6:[ ]+0f 25 2d e3 14 0e[ ]+comunlepd %xmm3,%xmm12,%xmm1 + [ ]+2fac:[ ]+0f 25 2d e3 14 0f[ ]+comtruepd %xmm3,%xmm12,%xmm1 + [ ]+2fb2:[ ]+0f 25 2d 62 14 04 00[ ]+comeqpd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2fb9:[ ]+0f 25 2d 62 14 04 01[ ]+comltpd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2fc0:[ ]+0f 25 2d 62 14 04 02[ ]+comlepd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2fc7:[ ]+0f 25 2d 62 14 04 03[ ]+comunordpd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2fce:[ ]+0f 25 2d 62 14 04 04[ ]+comnepd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2fd5:[ ]+0f 25 2d 62 14 04 05[ ]+comnltpd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2fdc:[ ]+0f 25 2d 62 14 04 06[ ]+comnlepd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2fe3:[ ]+0f 25 2d 62 14 04 07[ ]+comordpd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2fea:[ ]+0f 25 2d 62 14 04 08[ ]+comueqpd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2ff1:[ ]+0f 25 2d 62 14 04 09[ ]+comultpd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2ff8:[ ]+0f 25 2d 62 14 04 0a[ ]+comulepd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+2fff:[ ]+0f 25 2d 62 14 04 0b[ ]+comfalsepd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+3006:[ ]+0f 25 2d 62 14 04 0c[ ]+comunepd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+300d:[ ]+0f 25 2d 62 14 04 0d[ ]+comunltpd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+3014:[ ]+0f 25 2d 62 14 04 0e[ ]+comunlepd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+301b:[ ]+0f 25 2d 62 14 04 0f[ ]+comtruepd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+3022:[ ]+0f 25 4c e3 14 04[ ]+pcomeqb %xmm3,%xmm12,%xmm1 + [ ]+3028:[ ]+0f 25 4c 62 14 04 04[ ]+pcomeqb 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+302f:[ ]+0f 25 4c e3 14 00[ ]+pcomltb %xmm3,%xmm12,%xmm1 + [ ]+3035:[ ]+0f 25 4c e3 14 01[ ]+pcomleb %xmm3,%xmm12,%xmm1 + [ ]+303b:[ ]+0f 25 4c e3 14 02[ ]+pcomgtb %xmm3,%xmm12,%xmm1 + [ ]+3041:[ ]+0f 25 4c e3 14 03[ ]+pcomgeb %xmm3,%xmm12,%xmm1 + [ ]+3047:[ ]+0f 25 4c e3 14 04[ ]+pcomeqb %xmm3,%xmm12,%xmm1 + [ ]+304d:[ ]+0f 25 4c e3 14 05[ ]+pcomneb %xmm3,%xmm12,%xmm1 + [ ]+3053:[ ]+0f 25 4c 62 14 04 00[ ]+pcomltb 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+305a:[ ]+0f 25 4c 62 14 04 01[ ]+pcomleb 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+3061:[ ]+0f 25 4c 62 14 04 02[ ]+pcomgtb 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+3068:[ ]+0f 25 4c 62 14 04 03[ ]+pcomgeb 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+306f:[ ]+0f 25 4c 62 14 04 04[ ]+pcomeqb 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+3076:[ ]+0f 25 4c 62 14 04 05[ ]+pcomneb 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+307d:[ ]+0f 25 4d e3 14 04[ ]+pcomeqw %xmm3,%xmm12,%xmm1 + [ ]+3083:[ ]+0f 25 4d 62 14 04 04[ ]+pcomeqw 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+308a:[ ]+0f 25 4d e3 14 00[ ]+pcomltw %xmm3,%xmm12,%xmm1 + [ ]+3090:[ ]+0f 25 4d e3 14 01[ ]+pcomlew %xmm3,%xmm12,%xmm1 + [ ]+3096:[ ]+0f 25 4d e3 14 02[ ]+pcomgtw %xmm3,%xmm12,%xmm1 + [ ]+309c:[ ]+0f 25 4d e3 14 03[ ]+pcomgew %xmm3,%xmm12,%xmm1 + [ ]+30a2:[ ]+0f 25 4d e3 14 04[ ]+pcomeqw %xmm3,%xmm12,%xmm1 + [ ]+30a8:[ ]+0f 25 4d e3 14 05[ ]+pcomnew %xmm3,%xmm12,%xmm1 + [ ]+30ae:[ ]+0f 25 4d 62 14 04 00[ ]+pcomltw 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+30b5:[ ]+0f 25 4d 62 14 04 01[ ]+pcomlew 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+30bc:[ ]+0f 25 4d 62 14 04 02[ ]+pcomgtw 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+30c3:[ ]+0f 25 4d 62 14 04 03[ ]+pcomgew 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+30ca:[ ]+0f 25 4d 62 14 04 04[ ]+pcomeqw 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+30d1:[ ]+0f 25 4d 62 14 04 05[ ]+pcomnew 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+30d8:[ ]+0f 25 4e e3 14 04[ ]+pcomeqd %xmm3,%xmm12,%xmm1 + [ ]+30de:[ ]+0f 25 4e 62 14 04 04[ ]+pcomeqd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+30e5:[ ]+0f 25 4e e3 14 00[ ]+pcomltd %xmm3,%xmm12,%xmm1 + [ ]+30eb:[ ]+0f 25 4e e3 14 01[ ]+pcomled %xmm3,%xmm12,%xmm1 + [ ]+30f1:[ ]+0f 25 4e e3 14 02[ ]+pcomgtd %xmm3,%xmm12,%xmm1 + [ ]+30f7:[ ]+0f 25 4e e3 14 03[ ]+pcomged %xmm3,%xmm12,%xmm1 + [ ]+30fd:[ ]+0f 25 4e e3 14 04[ ]+pcomeqd %xmm3,%xmm12,%xmm1 + [ ]+3103:[ ]+0f 25 4e e3 14 05[ ]+pcomned %xmm3,%xmm12,%xmm1 + [ ]+3109:[ ]+0f 25 4e 62 14 04 00[ ]+pcomltd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+3110:[ ]+0f 25 4e 62 14 04 01[ ]+pcomled 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+3117:[ ]+0f 25 4e 62 14 04 02[ ]+pcomgtd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+311e:[ ]+0f 25 4e 62 14 04 03[ ]+pcomged 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+3125:[ ]+0f 25 4e 62 14 04 04[ ]+pcomeqd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+312c:[ ]+0f 25 4e 62 14 04 05[ ]+pcomned 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+3133:[ ]+0f 25 4f e3 14 04[ ]+pcomeqq %xmm3,%xmm12,%xmm1 + [ ]+3139:[ ]+0f 25 4f 62 14 04 04[ ]+pcomeqq 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+3140:[ ]+0f 25 4f e3 14 00[ ]+pcomltq %xmm3,%xmm12,%xmm1 + [ ]+3146:[ ]+0f 25 4f e3 14 01[ ]+pcomleq %xmm3,%xmm12,%xmm1 + [ ]+314c:[ ]+0f 25 4f e3 14 02[ ]+pcomgtq %xmm3,%xmm12,%xmm1 + [ ]+3152:[ ]+0f 25 4f e3 14 03[ ]+pcomgeq %xmm3,%xmm12,%xmm1 + [ ]+3158:[ ]+0f 25 4f e3 14 04[ ]+pcomeqq %xmm3,%xmm12,%xmm1 + [ ]+315e:[ ]+0f 25 4f e3 14 05[ ]+pcomneq %xmm3,%xmm12,%xmm1 + [ ]+3164:[ ]+0f 25 4f 62 14 04 00[ ]+pcomltq 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+316b:[ ]+0f 25 4f 62 14 04 01[ ]+pcomleq 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+3172:[ ]+0f 25 4f 62 14 04 02[ ]+pcomgtq 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+3179:[ ]+0f 25 4f 62 14 04 03[ ]+pcomgeq 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+3180:[ ]+0f 25 4f 62 14 04 04[ ]+pcomeqq 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+3187:[ ]+0f 25 4f 62 14 04 05[ ]+pcomneq 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+318e:[ ]+0f 25 6c e3 14 04[ ]+pcomequb %xmm3,%xmm12,%xmm1 + [ ]+3194:[ ]+0f 25 6c 62 14 04 04[ ]+pcomequb 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+319b:[ ]+0f 25 6c e3 14 00[ ]+pcomltub %xmm3,%xmm12,%xmm1 + [ ]+31a1:[ ]+0f 25 6c e3 14 01[ ]+pcomleub %xmm3,%xmm12,%xmm1 + [ ]+31a7:[ ]+0f 25 6c e3 14 02[ ]+pcomgtub %xmm3,%xmm12,%xmm1 + [ ]+31ad:[ ]+0f 25 6c e3 14 03[ ]+pcomgeub %xmm3,%xmm12,%xmm1 + [ ]+31b3:[ ]+0f 25 6c e3 14 04[ ]+pcomequb %xmm3,%xmm12,%xmm1 + [ ]+31b9:[ ]+0f 25 6c e3 14 05[ ]+pcomneub %xmm3,%xmm12,%xmm1 + [ ]+31bf:[ ]+0f 25 6c 62 14 04 00[ ]+pcomltub 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+31c6:[ ]+0f 25 6c 62 14 04 01[ ]+pcomleub 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+31cd:[ ]+0f 25 6c 62 14 04 02[ ]+pcomgtub 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+31d4:[ ]+0f 25 6c 62 14 04 03[ ]+pcomgeub 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+31db:[ ]+0f 25 6c 62 14 04 04[ ]+pcomequb 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+31e2:[ ]+0f 25 6c 62 14 04 05[ ]+pcomneub 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+31e9:[ ]+0f 25 6d e3 14 04[ ]+pcomequw %xmm3,%xmm12,%xmm1 + [ ]+31ef:[ ]+0f 25 6d 62 14 04 04[ ]+pcomequw 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+31f6:[ ]+0f 25 6d e3 14 00[ ]+pcomltuw %xmm3,%xmm12,%xmm1 + [ ]+31fc:[ ]+0f 25 6d e3 14 01[ ]+pcomleuw %xmm3,%xmm12,%xmm1 + [ ]+3202:[ ]+0f 25 6d e3 14 02[ ]+pcomgtuw %xmm3,%xmm12,%xmm1 + [ ]+3208:[ ]+0f 25 6d e3 14 03[ ]+pcomgeuw %xmm3,%xmm12,%xmm1 + [ ]+320e:[ ]+0f 25 6d e3 14 04[ ]+pcomequw %xmm3,%xmm12,%xmm1 + [ ]+3214:[ ]+0f 25 6d e3 14 05[ ]+pcomneuw %xmm3,%xmm12,%xmm1 + [ ]+321a:[ ]+0f 25 6d 62 14 04 00[ ]+pcomltuw 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+3221:[ ]+0f 25 6d 62 14 04 01[ ]+pcomleuw 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+3228:[ ]+0f 25 6d 62 14 04 02[ ]+pcomgtuw 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+322f:[ ]+0f 25 6d 62 14 04 03[ ]+pcomgeuw 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+3236:[ ]+0f 25 6d 62 14 04 04[ ]+pcomequw 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+323d:[ ]+0f 25 6d 62 14 04 05[ ]+pcomneuw 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+3244:[ ]+0f 25 6e e3 14 04[ ]+pcomequd %xmm3,%xmm12,%xmm1 + [ ]+324a:[ ]+0f 25 6e 62 14 04 04[ ]+pcomequd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+3251:[ ]+0f 25 6e e3 14 00[ ]+pcomltud %xmm3,%xmm12,%xmm1 + [ ]+3257:[ ]+0f 25 6e e3 14 01[ ]+pcomleud %xmm3,%xmm12,%xmm1 + [ ]+325d:[ ]+0f 25 6e e3 14 02[ ]+pcomgtud %xmm3,%xmm12,%xmm1 + [ ]+3263:[ ]+0f 25 6e e3 14 03[ ]+pcomgeud %xmm3,%xmm12,%xmm1 + [ ]+3269:[ ]+0f 25 6e e3 14 04[ ]+pcomequd %xmm3,%xmm12,%xmm1 + [ ]+326f:[ ]+0f 25 6e e3 14 05[ ]+pcomneud %xmm3,%xmm12,%xmm1 + [ ]+3275:[ ]+0f 25 6e 62 14 04 00[ ]+pcomltud 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+327c:[ ]+0f 25 6e 62 14 04 01[ ]+pcomleud 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+3283:[ ]+0f 25 6e 62 14 04 02[ ]+pcomgtud 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+328a:[ ]+0f 25 6e 62 14 04 03[ ]+pcomgeud 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+3291:[ ]+0f 25 6e 62 14 04 04[ ]+pcomequd 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+3298:[ ]+0f 25 6e 62 14 04 05[ ]+pcomneud 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+329f:[ ]+0f 25 6f e3 14 04[ ]+pcomequq %xmm3,%xmm12,%xmm1 + [ ]+32a5:[ ]+0f 25 6f 62 14 04 04[ ]+pcomequq 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+32ac:[ ]+0f 25 6f e3 14 00[ ]+pcomltuq %xmm3,%xmm12,%xmm1 + [ ]+32b2:[ ]+0f 25 6f e3 14 01[ ]+pcomleuq %xmm3,%xmm12,%xmm1 + [ ]+32b8:[ ]+0f 25 6f e3 14 02[ ]+pcomgtuq %xmm3,%xmm12,%xmm1 + [ ]+32be:[ ]+0f 25 6f e3 14 03[ ]+pcomgeuq %xmm3,%xmm12,%xmm1 + [ ]+32c4:[ ]+0f 25 6f e3 14 04[ ]+pcomequq %xmm3,%xmm12,%xmm1 + [ ]+32ca:[ ]+0f 25 6f e3 14 05[ ]+pcomneuq %xmm3,%xmm12,%xmm1 + [ ]+32d0:[ ]+0f 25 6f 62 14 04 00[ ]+pcomltuq 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+32d7:[ ]+0f 25 6f 62 14 04 01[ ]+pcomleuq 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+32de:[ ]+0f 25 6f 62 14 04 02[ ]+pcomgtuq 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+32e5:[ ]+0f 25 6f 62 14 04 03[ ]+pcomgeuq 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+32ec:[ ]+0f 25 6f 62 14 04 04[ ]+pcomequq 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+32f3:[ ]+0f 25 6f 62 14 04 05[ ]+pcomneuq 0x4\(%rdx\),%xmm12,%xmm1 + [ ]+32fa:[ ]+0f 25 2e d3 b0 04[ ]+comness %xmm3,%xmm2,%xmm11 + [ ]+3300:[ ]+0f 25 2e 52 b0 04 04[ ]+comness 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3307:[ ]+0f 25 2e d3 b0 00[ ]+comeqss %xmm3,%xmm2,%xmm11 + [ ]+330d:[ ]+0f 25 2e d3 b0 01[ ]+comltss %xmm3,%xmm2,%xmm11 + [ ]+3313:[ ]+0f 25 2e d3 b0 02[ ]+comless %xmm3,%xmm2,%xmm11 + [ ]+3319:[ ]+0f 25 2e d3 b0 03[ ]+comunordss %xmm3,%xmm2,%xmm11 + [ ]+331f:[ ]+0f 25 2e d3 b0 04[ ]+comness %xmm3,%xmm2,%xmm11 + [ ]+3325:[ ]+0f 25 2e d3 b0 05[ ]+comnltss %xmm3,%xmm2,%xmm11 + [ ]+332b:[ ]+0f 25 2e d3 b0 06[ ]+comnless %xmm3,%xmm2,%xmm11 + [ ]+3331:[ ]+0f 25 2e d3 b0 07[ ]+comordss %xmm3,%xmm2,%xmm11 + [ ]+3337:[ ]+0f 25 2e d3 b0 08[ ]+comueqss %xmm3,%xmm2,%xmm11 + [ ]+333d:[ ]+0f 25 2e d3 b0 09[ ]+comultss %xmm3,%xmm2,%xmm11 + [ ]+3343:[ ]+0f 25 2e d3 b0 0a[ ]+comuless %xmm3,%xmm2,%xmm11 + [ ]+3349:[ ]+0f 25 2e d3 b0 0b[ ]+comfalsess %xmm3,%xmm2,%xmm11 + [ ]+334f:[ ]+0f 25 2e d3 b0 0c[ ]+comuness %xmm3,%xmm2,%xmm11 + [ ]+3355:[ ]+0f 25 2e d3 b0 0d[ ]+comunltss %xmm3,%xmm2,%xmm11 + [ ]+335b:[ ]+0f 25 2e d3 b0 0e[ ]+comunless %xmm3,%xmm2,%xmm11 + [ ]+3361:[ ]+0f 25 2e d3 b0 0f[ ]+comtruess %xmm3,%xmm2,%xmm11 + [ ]+3367:[ ]+0f 25 2e 52 b0 04 00[ ]+comeqss 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+336e:[ ]+0f 25 2e 52 b0 04 01[ ]+comltss 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3375:[ ]+0f 25 2e 52 b0 04 02[ ]+comless 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+337c:[ ]+0f 25 2e 52 b0 04 03[ ]+comunordss 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3383:[ ]+0f 25 2e 52 b0 04 04[ ]+comness 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+338a:[ ]+0f 25 2e 52 b0 04 05[ ]+comnltss 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3391:[ ]+0f 25 2e 52 b0 04 06[ ]+comnless 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3398:[ ]+0f 25 2e 52 b0 04 07[ ]+comordss 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+339f:[ ]+0f 25 2e 52 b0 04 08[ ]+comueqss 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+33a6:[ ]+0f 25 2e 52 b0 04 09[ ]+comultss 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+33ad:[ ]+0f 25 2e 52 b0 04 0a[ ]+comuless 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+33b4:[ ]+0f 25 2e 52 b0 04 0b[ ]+comfalsess 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+33bb:[ ]+0f 25 2e 52 b0 04 0c[ ]+comuness 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+33c2:[ ]+0f 25 2e 52 b0 04 0d[ ]+comunltss 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+33c9:[ ]+0f 25 2e 52 b0 04 0e[ ]+comunless 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+33d0:[ ]+0f 25 2e 52 b0 04 0f[ ]+comtruess 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+33d7:[ ]+0f 25 2f d3 b0 04[ ]+comnesd %xmm3,%xmm2,%xmm11 + [ ]+33dd:[ ]+0f 25 2f 52 b0 04 04[ ]+comnesd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+33e4:[ ]+0f 25 2f d3 b0 00[ ]+comeqsd %xmm3,%xmm2,%xmm11 + [ ]+33ea:[ ]+0f 25 2f d3 b0 01[ ]+comltsd %xmm3,%xmm2,%xmm11 + [ ]+33f0:[ ]+0f 25 2f d3 b0 02[ ]+comlesd %xmm3,%xmm2,%xmm11 + [ ]+33f6:[ ]+0f 25 2f d3 b0 03[ ]+comunordsd %xmm3,%xmm2,%xmm11 + [ ]+33fc:[ ]+0f 25 2f d3 b0 04[ ]+comnesd %xmm3,%xmm2,%xmm11 + [ ]+3402:[ ]+0f 25 2f d3 b0 05[ ]+comnltsd %xmm3,%xmm2,%xmm11 + [ ]+3408:[ ]+0f 25 2f d3 b0 06[ ]+comnlesd %xmm3,%xmm2,%xmm11 + [ ]+340e:[ ]+0f 25 2f d3 b0 07[ ]+comordsd %xmm3,%xmm2,%xmm11 + [ ]+3414:[ ]+0f 25 2f d3 b0 08[ ]+comueqsd %xmm3,%xmm2,%xmm11 + [ ]+341a:[ ]+0f 25 2f d3 b0 09[ ]+comultsd %xmm3,%xmm2,%xmm11 + [ ]+3420:[ ]+0f 25 2f d3 b0 0a[ ]+comulesd %xmm3,%xmm2,%xmm11 + [ ]+3426:[ ]+0f 25 2f d3 b0 0b[ ]+comfalsesd %xmm3,%xmm2,%xmm11 + [ ]+342c:[ ]+0f 25 2f d3 b0 0c[ ]+comunesd %xmm3,%xmm2,%xmm11 + [ ]+3432:[ ]+0f 25 2f d3 b0 0d[ ]+comunltsd %xmm3,%xmm2,%xmm11 + [ ]+3438:[ ]+0f 25 2f d3 b0 0e[ ]+comunlesd %xmm3,%xmm2,%xmm11 + [ ]+343e:[ ]+0f 25 2f d3 b0 0f[ ]+comtruesd %xmm3,%xmm2,%xmm11 + [ ]+3444:[ ]+0f 25 2f 52 b0 04 00[ ]+comeqsd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+344b:[ ]+0f 25 2f 52 b0 04 01[ ]+comltsd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3452:[ ]+0f 25 2f 52 b0 04 02[ ]+comlesd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3459:[ ]+0f 25 2f 52 b0 04 03[ ]+comunordsd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3460:[ ]+0f 25 2f 52 b0 04 04[ ]+comnesd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3467:[ ]+0f 25 2f 52 b0 04 05[ ]+comnltsd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+346e:[ ]+0f 25 2f 52 b0 04 06[ ]+comnlesd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3475:[ ]+0f 25 2f 52 b0 04 07[ ]+comordsd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+347c:[ ]+0f 25 2f 52 b0 04 08[ ]+comueqsd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3483:[ ]+0f 25 2f 52 b0 04 09[ ]+comultsd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+348a:[ ]+0f 25 2f 52 b0 04 0a[ ]+comulesd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3491:[ ]+0f 25 2f 52 b0 04 0b[ ]+comfalsesd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3498:[ ]+0f 25 2f 52 b0 04 0c[ ]+comunesd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+349f:[ ]+0f 25 2f 52 b0 04 0d[ ]+comunltsd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+34a6:[ ]+0f 25 2f 52 b0 04 0e[ ]+comunlesd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+34ad:[ ]+0f 25 2f 52 b0 04 0f[ ]+comtruesd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+34b4:[ ]+0f 25 2c d3 b0 04[ ]+comneps %xmm3,%xmm2,%xmm11 + [ ]+34ba:[ ]+0f 25 2c 52 b0 04 04[ ]+comneps 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+34c1:[ ]+0f 25 2c d3 b0 00[ ]+comeqps %xmm3,%xmm2,%xmm11 + [ ]+34c7:[ ]+0f 25 2c d3 b0 01[ ]+comltps %xmm3,%xmm2,%xmm11 + [ ]+34cd:[ ]+0f 25 2c d3 b0 02[ ]+comleps %xmm3,%xmm2,%xmm11 + [ ]+34d3:[ ]+0f 25 2c d3 b0 03[ ]+comunordps %xmm3,%xmm2,%xmm11 + [ ]+34d9:[ ]+0f 25 2c d3 b0 04[ ]+comneps %xmm3,%xmm2,%xmm11 + [ ]+34df:[ ]+0f 25 2c d3 b0 05[ ]+comnltps %xmm3,%xmm2,%xmm11 + [ ]+34e5:[ ]+0f 25 2c d3 b0 06[ ]+comnleps %xmm3,%xmm2,%xmm11 + [ ]+34eb:[ ]+0f 25 2c d3 b0 07[ ]+comordps %xmm3,%xmm2,%xmm11 + [ ]+34f1:[ ]+0f 25 2c d3 b0 08[ ]+comueqps %xmm3,%xmm2,%xmm11 + [ ]+34f7:[ ]+0f 25 2c d3 b0 09[ ]+comultps %xmm3,%xmm2,%xmm11 + [ ]+34fd:[ ]+0f 25 2c d3 b0 0a[ ]+comuleps %xmm3,%xmm2,%xmm11 + [ ]+3503:[ ]+0f 25 2c d3 b0 0b[ ]+comfalseps %xmm3,%xmm2,%xmm11 + [ ]+3509:[ ]+0f 25 2c d3 b0 0c[ ]+comuneps %xmm3,%xmm2,%xmm11 + [ ]+350f:[ ]+0f 25 2c d3 b0 0d[ ]+comunltps %xmm3,%xmm2,%xmm11 + [ ]+3515:[ ]+0f 25 2c d3 b0 0e[ ]+comunleps %xmm3,%xmm2,%xmm11 + [ ]+351b:[ ]+0f 25 2c d3 b0 0f[ ]+comtrueps %xmm3,%xmm2,%xmm11 + [ ]+3521:[ ]+0f 25 2c 52 b0 04 00[ ]+comeqps 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3528:[ ]+0f 25 2c 52 b0 04 01[ ]+comltps 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+352f:[ ]+0f 25 2c 52 b0 04 02[ ]+comleps 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3536:[ ]+0f 25 2c 52 b0 04 03[ ]+comunordps 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+353d:[ ]+0f 25 2c 52 b0 04 04[ ]+comneps 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3544:[ ]+0f 25 2c 52 b0 04 05[ ]+comnltps 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+354b:[ ]+0f 25 2c 52 b0 04 06[ ]+comnleps 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3552:[ ]+0f 25 2c 52 b0 04 07[ ]+comordps 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3559:[ ]+0f 25 2c 52 b0 04 08[ ]+comueqps 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3560:[ ]+0f 25 2c 52 b0 04 09[ ]+comultps 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3567:[ ]+0f 25 2c 52 b0 04 0a[ ]+comuleps 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+356e:[ ]+0f 25 2c 52 b0 04 0b[ ]+comfalseps 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3575:[ ]+0f 25 2c 52 b0 04 0c[ ]+comuneps 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+357c:[ ]+0f 25 2c 52 b0 04 0d[ ]+comunltps 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3583:[ ]+0f 25 2c 52 b0 04 0e[ ]+comunleps 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+358a:[ ]+0f 25 2c 52 b0 04 0f[ ]+comtrueps 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3591:[ ]+0f 25 2d d3 b0 04[ ]+comnepd %xmm3,%xmm2,%xmm11 + [ ]+3597:[ ]+0f 25 2d 52 b0 04 04[ ]+comnepd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+359e:[ ]+0f 25 2d d3 b0 00[ ]+comeqpd %xmm3,%xmm2,%xmm11 + [ ]+35a4:[ ]+0f 25 2d d3 b0 01[ ]+comltpd %xmm3,%xmm2,%xmm11 + [ ]+35aa:[ ]+0f 25 2d d3 b0 02[ ]+comlepd %xmm3,%xmm2,%xmm11 + [ ]+35b0:[ ]+0f 25 2d d3 b0 03[ ]+comunordpd %xmm3,%xmm2,%xmm11 + [ ]+35b6:[ ]+0f 25 2d d3 b0 04[ ]+comnepd %xmm3,%xmm2,%xmm11 + [ ]+35bc:[ ]+0f 25 2d d3 b0 05[ ]+comnltpd %xmm3,%xmm2,%xmm11 + [ ]+35c2:[ ]+0f 25 2d d3 b0 06[ ]+comnlepd %xmm3,%xmm2,%xmm11 + [ ]+35c8:[ ]+0f 25 2d d3 b0 07[ ]+comordpd %xmm3,%xmm2,%xmm11 + [ ]+35ce:[ ]+0f 25 2d d3 b0 08[ ]+comueqpd %xmm3,%xmm2,%xmm11 + [ ]+35d4:[ ]+0f 25 2d d3 b0 09[ ]+comultpd %xmm3,%xmm2,%xmm11 + [ ]+35da:[ ]+0f 25 2d d3 b0 0a[ ]+comulepd %xmm3,%xmm2,%xmm11 + [ ]+35e0:[ ]+0f 25 2d d3 b0 0b[ ]+comfalsepd %xmm3,%xmm2,%xmm11 + [ ]+35e6:[ ]+0f 25 2d d3 b0 0c[ ]+comunepd %xmm3,%xmm2,%xmm11 + [ ]+35ec:[ ]+0f 25 2d d3 b0 0d[ ]+comunltpd %xmm3,%xmm2,%xmm11 + [ ]+35f2:[ ]+0f 25 2d d3 b0 0e[ ]+comunlepd %xmm3,%xmm2,%xmm11 + [ ]+35f8:[ ]+0f 25 2d d3 b0 0f[ ]+comtruepd %xmm3,%xmm2,%xmm11 + [ ]+35fe:[ ]+0f 25 2d 52 b0 04 00[ ]+comeqpd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3605:[ ]+0f 25 2d 52 b0 04 01[ ]+comltpd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+360c:[ ]+0f 25 2d 52 b0 04 02[ ]+comlepd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3613:[ ]+0f 25 2d 52 b0 04 03[ ]+comunordpd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+361a:[ ]+0f 25 2d 52 b0 04 04[ ]+comnepd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3621:[ ]+0f 25 2d 52 b0 04 05[ ]+comnltpd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3628:[ ]+0f 25 2d 52 b0 04 06[ ]+comnlepd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+362f:[ ]+0f 25 2d 52 b0 04 07[ ]+comordpd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3636:[ ]+0f 25 2d 52 b0 04 08[ ]+comueqpd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+363d:[ ]+0f 25 2d 52 b0 04 09[ ]+comultpd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3644:[ ]+0f 25 2d 52 b0 04 0a[ ]+comulepd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+364b:[ ]+0f 25 2d 52 b0 04 0b[ ]+comfalsepd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3652:[ ]+0f 25 2d 52 b0 04 0c[ ]+comunepd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3659:[ ]+0f 25 2d 52 b0 04 0d[ ]+comunltpd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3660:[ ]+0f 25 2d 52 b0 04 0e[ ]+comunlepd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3667:[ ]+0f 25 2d 52 b0 04 0f[ ]+comtruepd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+366e:[ ]+0f 25 4c d3 b0 04[ ]+pcomeqb %xmm3,%xmm2,%xmm11 + [ ]+3674:[ ]+0f 25 4c 52 b0 04 04[ ]+pcomeqb 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+367b:[ ]+0f 25 4c d3 b0 00[ ]+pcomltb %xmm3,%xmm2,%xmm11 + [ ]+3681:[ ]+0f 25 4c d3 b0 01[ ]+pcomleb %xmm3,%xmm2,%xmm11 + [ ]+3687:[ ]+0f 25 4c d3 b0 02[ ]+pcomgtb %xmm3,%xmm2,%xmm11 + [ ]+368d:[ ]+0f 25 4c d3 b0 03[ ]+pcomgeb %xmm3,%xmm2,%xmm11 + [ ]+3693:[ ]+0f 25 4c d3 b0 04[ ]+pcomeqb %xmm3,%xmm2,%xmm11 + [ ]+3699:[ ]+0f 25 4c d3 b0 05[ ]+pcomneb %xmm3,%xmm2,%xmm11 + [ ]+369f:[ ]+0f 25 4c 52 b0 04 00[ ]+pcomltb 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+36a6:[ ]+0f 25 4c 52 b0 04 01[ ]+pcomleb 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+36ad:[ ]+0f 25 4c 52 b0 04 02[ ]+pcomgtb 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+36b4:[ ]+0f 25 4c 52 b0 04 03[ ]+pcomgeb 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+36bb:[ ]+0f 25 4c 52 b0 04 04[ ]+pcomeqb 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+36c2:[ ]+0f 25 4c 52 b0 04 05[ ]+pcomneb 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+36c9:[ ]+0f 25 4d d3 b0 04[ ]+pcomeqw %xmm3,%xmm2,%xmm11 + [ ]+36cf:[ ]+0f 25 4d 52 b0 04 04[ ]+pcomeqw 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+36d6:[ ]+0f 25 4d d3 b0 00[ ]+pcomltw %xmm3,%xmm2,%xmm11 + [ ]+36dc:[ ]+0f 25 4d d3 b0 01[ ]+pcomlew %xmm3,%xmm2,%xmm11 + [ ]+36e2:[ ]+0f 25 4d d3 b0 02[ ]+pcomgtw %xmm3,%xmm2,%xmm11 + [ ]+36e8:[ ]+0f 25 4d d3 b0 03[ ]+pcomgew %xmm3,%xmm2,%xmm11 + [ ]+36ee:[ ]+0f 25 4d d3 b0 04[ ]+pcomeqw %xmm3,%xmm2,%xmm11 + [ ]+36f4:[ ]+0f 25 4d d3 b0 05[ ]+pcomnew %xmm3,%xmm2,%xmm11 + [ ]+36fa:[ ]+0f 25 4d 52 b0 04 00[ ]+pcomltw 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3701:[ ]+0f 25 4d 52 b0 04 01[ ]+pcomlew 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3708:[ ]+0f 25 4d 52 b0 04 02[ ]+pcomgtw 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+370f:[ ]+0f 25 4d 52 b0 04 03[ ]+pcomgew 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3716:[ ]+0f 25 4d 52 b0 04 04[ ]+pcomeqw 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+371d:[ ]+0f 25 4d 52 b0 04 05[ ]+pcomnew 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3724:[ ]+0f 25 4e d3 b0 04[ ]+pcomeqd %xmm3,%xmm2,%xmm11 + [ ]+372a:[ ]+0f 25 4e 52 b0 04 04[ ]+pcomeqd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3731:[ ]+0f 25 4e d3 b0 00[ ]+pcomltd %xmm3,%xmm2,%xmm11 + [ ]+3737:[ ]+0f 25 4e d3 b0 01[ ]+pcomled %xmm3,%xmm2,%xmm11 + [ ]+373d:[ ]+0f 25 4e d3 b0 02[ ]+pcomgtd %xmm3,%xmm2,%xmm11 + [ ]+3743:[ ]+0f 25 4e d3 b0 03[ ]+pcomged %xmm3,%xmm2,%xmm11 + [ ]+3749:[ ]+0f 25 4e d3 b0 04[ ]+pcomeqd %xmm3,%xmm2,%xmm11 + [ ]+374f:[ ]+0f 25 4e d3 b0 05[ ]+pcomned %xmm3,%xmm2,%xmm11 + [ ]+3755:[ ]+0f 25 4e 52 b0 04 00[ ]+pcomltd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+375c:[ ]+0f 25 4e 52 b0 04 01[ ]+pcomled 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3763:[ ]+0f 25 4e 52 b0 04 02[ ]+pcomgtd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+376a:[ ]+0f 25 4e 52 b0 04 03[ ]+pcomged 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3771:[ ]+0f 25 4e 52 b0 04 04[ ]+pcomeqd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3778:[ ]+0f 25 4e 52 b0 04 05[ ]+pcomned 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+377f:[ ]+0f 25 4f d3 b0 04[ ]+pcomeqq %xmm3,%xmm2,%xmm11 + [ ]+3785:[ ]+0f 25 4f 52 b0 04 04[ ]+pcomeqq 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+378c:[ ]+0f 25 4f d3 b0 00[ ]+pcomltq %xmm3,%xmm2,%xmm11 + [ ]+3792:[ ]+0f 25 4f d3 b0 01[ ]+pcomleq %xmm3,%xmm2,%xmm11 + [ ]+3798:[ ]+0f 25 4f d3 b0 02[ ]+pcomgtq %xmm3,%xmm2,%xmm11 + [ ]+379e:[ ]+0f 25 4f d3 b0 03[ ]+pcomgeq %xmm3,%xmm2,%xmm11 + [ ]+37a4:[ ]+0f 25 4f d3 b0 04[ ]+pcomeqq %xmm3,%xmm2,%xmm11 + [ ]+37aa:[ ]+0f 25 4f d3 b0 05[ ]+pcomneq %xmm3,%xmm2,%xmm11 + [ ]+37b0:[ ]+0f 25 4f 52 b0 04 00[ ]+pcomltq 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+37b7:[ ]+0f 25 4f 52 b0 04 01[ ]+pcomleq 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+37be:[ ]+0f 25 4f 52 b0 04 02[ ]+pcomgtq 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+37c5:[ ]+0f 25 4f 52 b0 04 03[ ]+pcomgeq 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+37cc:[ ]+0f 25 4f 52 b0 04 04[ ]+pcomeqq 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+37d3:[ ]+0f 25 4f 52 b0 04 05[ ]+pcomneq 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+37da:[ ]+0f 25 6c d3 b0 04[ ]+pcomequb %xmm3,%xmm2,%xmm11 + [ ]+37e0:[ ]+0f 25 6c 52 b0 04 04[ ]+pcomequb 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+37e7:[ ]+0f 25 6c d3 b0 00[ ]+pcomltub %xmm3,%xmm2,%xmm11 + [ ]+37ed:[ ]+0f 25 6c d3 b0 01[ ]+pcomleub %xmm3,%xmm2,%xmm11 + [ ]+37f3:[ ]+0f 25 6c d3 b0 02[ ]+pcomgtub %xmm3,%xmm2,%xmm11 + [ ]+37f9:[ ]+0f 25 6c d3 b0 03[ ]+pcomgeub %xmm3,%xmm2,%xmm11 + [ ]+37ff:[ ]+0f 25 6c d3 b0 04[ ]+pcomequb %xmm3,%xmm2,%xmm11 + [ ]+3805:[ ]+0f 25 6c d3 b0 05[ ]+pcomneub %xmm3,%xmm2,%xmm11 + [ ]+380b:[ ]+0f 25 6c 52 b0 04 00[ ]+pcomltub 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3812:[ ]+0f 25 6c 52 b0 04 01[ ]+pcomleub 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3819:[ ]+0f 25 6c 52 b0 04 02[ ]+pcomgtub 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3820:[ ]+0f 25 6c 52 b0 04 03[ ]+pcomgeub 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3827:[ ]+0f 25 6c 52 b0 04 04[ ]+pcomequb 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+382e:[ ]+0f 25 6c 52 b0 04 05[ ]+pcomneub 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3835:[ ]+0f 25 6d d3 b0 04[ ]+pcomequw %xmm3,%xmm2,%xmm11 + [ ]+383b:[ ]+0f 25 6d 52 b0 04 04[ ]+pcomequw 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3842:[ ]+0f 25 6d d3 b0 00[ ]+pcomltuw %xmm3,%xmm2,%xmm11 + [ ]+3848:[ ]+0f 25 6d d3 b0 01[ ]+pcomleuw %xmm3,%xmm2,%xmm11 + [ ]+384e:[ ]+0f 25 6d d3 b0 02[ ]+pcomgtuw %xmm3,%xmm2,%xmm11 + [ ]+3854:[ ]+0f 25 6d d3 b0 03[ ]+pcomgeuw %xmm3,%xmm2,%xmm11 + [ ]+385a:[ ]+0f 25 6d d3 b0 04[ ]+pcomequw %xmm3,%xmm2,%xmm11 + [ ]+3860:[ ]+0f 25 6d d3 b0 05[ ]+pcomneuw %xmm3,%xmm2,%xmm11 + [ ]+3866:[ ]+0f 25 6d 52 b0 04 00[ ]+pcomltuw 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+386d:[ ]+0f 25 6d 52 b0 04 01[ ]+pcomleuw 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3874:[ ]+0f 25 6d 52 b0 04 02[ ]+pcomgtuw 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+387b:[ ]+0f 25 6d 52 b0 04 03[ ]+pcomgeuw 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3882:[ ]+0f 25 6d 52 b0 04 04[ ]+pcomequw 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3889:[ ]+0f 25 6d 52 b0 04 05[ ]+pcomneuw 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3890:[ ]+0f 25 6e d3 b0 04[ ]+pcomequd %xmm3,%xmm2,%xmm11 + [ ]+3896:[ ]+0f 25 6e 52 b0 04 04[ ]+pcomequd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+389d:[ ]+0f 25 6e d3 b0 00[ ]+pcomltud %xmm3,%xmm2,%xmm11 + [ ]+38a3:[ ]+0f 25 6e d3 b0 01[ ]+pcomleud %xmm3,%xmm2,%xmm11 + [ ]+38a9:[ ]+0f 25 6e d3 b0 02[ ]+pcomgtud %xmm3,%xmm2,%xmm11 + [ ]+38af:[ ]+0f 25 6e d3 b0 03[ ]+pcomgeud %xmm3,%xmm2,%xmm11 + [ ]+38b5:[ ]+0f 25 6e d3 b0 04[ ]+pcomequd %xmm3,%xmm2,%xmm11 + [ ]+38bb:[ ]+0f 25 6e d3 b0 05[ ]+pcomneud %xmm3,%xmm2,%xmm11 + [ ]+38c1:[ ]+0f 25 6e 52 b0 04 00[ ]+pcomltud 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+38c8:[ ]+0f 25 6e 52 b0 04 01[ ]+pcomleud 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+38cf:[ ]+0f 25 6e 52 b0 04 02[ ]+pcomgtud 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+38d6:[ ]+0f 25 6e 52 b0 04 03[ ]+pcomgeud 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+38dd:[ ]+0f 25 6e 52 b0 04 04[ ]+pcomequd 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+38e4:[ ]+0f 25 6e 52 b0 04 05[ ]+pcomneud 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+38eb:[ ]+0f 25 6f d3 b0 04[ ]+pcomequq %xmm3,%xmm2,%xmm11 + [ ]+38f1:[ ]+0f 25 6f 52 b0 04 04[ ]+pcomequq 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+38f8:[ ]+0f 25 6f d3 b0 00[ ]+pcomltuq %xmm3,%xmm2,%xmm11 + [ ]+38fe:[ ]+0f 25 6f d3 b0 01[ ]+pcomleuq %xmm3,%xmm2,%xmm11 + [ ]+3904:[ ]+0f 25 6f d3 b0 02[ ]+pcomgtuq %xmm3,%xmm2,%xmm11 + [ ]+390a:[ ]+0f 25 6f d3 b0 03[ ]+pcomgeuq %xmm3,%xmm2,%xmm11 + [ ]+3910:[ ]+0f 25 6f d3 b0 04[ ]+pcomequq %xmm3,%xmm2,%xmm11 + [ ]+3916:[ ]+0f 25 6f d3 b0 05[ ]+pcomneuq %xmm3,%xmm2,%xmm11 + [ ]+391c:[ ]+0f 25 6f 52 b0 04 00[ ]+pcomltuq 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3923:[ ]+0f 25 6f 52 b0 04 01[ ]+pcomleuq 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+392a:[ ]+0f 25 6f 52 b0 04 02[ ]+pcomgtuq 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3931:[ ]+0f 25 6f 52 b0 04 03[ ]+pcomgeuq 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3938:[ ]+0f 25 6f 52 b0 04 04[ ]+pcomequq 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+393f:[ ]+0f 25 6f 52 b0 04 05[ ]+pcomneuq 0x4\(%rdx\),%xmm2,%xmm11 + [ ]+3946:[ ]+0f 25 2e d5 11 04[ ]+comness %xmm13,%xmm2,%xmm1 + [ ]+394c:[ ]+0f 25 2e 52 10 04 04[ ]+comness 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3953:[ ]+0f 25 2e d5 11 00[ ]+comeqss %xmm13,%xmm2,%xmm1 + [ ]+3959:[ ]+0f 25 2e d5 11 01[ ]+comltss %xmm13,%xmm2,%xmm1 + [ ]+395f:[ ]+0f 25 2e d5 11 02[ ]+comless %xmm13,%xmm2,%xmm1 + [ ]+3965:[ ]+0f 25 2e d5 11 03[ ]+comunordss %xmm13,%xmm2,%xmm1 + [ ]+396b:[ ]+0f 25 2e d5 11 04[ ]+comness %xmm13,%xmm2,%xmm1 + [ ]+3971:[ ]+0f 25 2e d5 11 05[ ]+comnltss %xmm13,%xmm2,%xmm1 + [ ]+3977:[ ]+0f 25 2e d5 11 06[ ]+comnless %xmm13,%xmm2,%xmm1 + [ ]+397d:[ ]+0f 25 2e d5 11 07[ ]+comordss %xmm13,%xmm2,%xmm1 + [ ]+3983:[ ]+0f 25 2e d5 11 08[ ]+comueqss %xmm13,%xmm2,%xmm1 + [ ]+3989:[ ]+0f 25 2e d5 11 09[ ]+comultss %xmm13,%xmm2,%xmm1 + [ ]+398f:[ ]+0f 25 2e d5 11 0a[ ]+comuless %xmm13,%xmm2,%xmm1 + [ ]+3995:[ ]+0f 25 2e d5 11 0b[ ]+comfalsess %xmm13,%xmm2,%xmm1 + [ ]+399b:[ ]+0f 25 2e d5 11 0c[ ]+comuness %xmm13,%xmm2,%xmm1 + [ ]+39a1:[ ]+0f 25 2e d5 11 0d[ ]+comunltss %xmm13,%xmm2,%xmm1 + [ ]+39a7:[ ]+0f 25 2e d5 11 0e[ ]+comunless %xmm13,%xmm2,%xmm1 + [ ]+39ad:[ ]+0f 25 2e d5 11 0f[ ]+comtruess %xmm13,%xmm2,%xmm1 + [ ]+39b3:[ ]+0f 25 2e 52 10 04 00[ ]+comeqss 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+39ba:[ ]+0f 25 2e 52 10 04 01[ ]+comltss 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+39c1:[ ]+0f 25 2e 52 10 04 02[ ]+comless 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+39c8:[ ]+0f 25 2e 52 10 04 03[ ]+comunordss 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+39cf:[ ]+0f 25 2e 52 10 04 04[ ]+comness 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+39d6:[ ]+0f 25 2e 52 10 04 05[ ]+comnltss 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+39dd:[ ]+0f 25 2e 52 10 04 06[ ]+comnless 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+39e4:[ ]+0f 25 2e 52 10 04 07[ ]+comordss 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+39eb:[ ]+0f 25 2e 52 10 04 08[ ]+comueqss 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+39f2:[ ]+0f 25 2e 52 10 04 09[ ]+comultss 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+39f9:[ ]+0f 25 2e 52 10 04 0a[ ]+comuless 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3a00:[ ]+0f 25 2e 52 10 04 0b[ ]+comfalsess 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3a07:[ ]+0f 25 2e 52 10 04 0c[ ]+comuness 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3a0e:[ ]+0f 25 2e 52 10 04 0d[ ]+comunltss 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3a15:[ ]+0f 25 2e 52 10 04 0e[ ]+comunless 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3a1c:[ ]+0f 25 2e 52 10 04 0f[ ]+comtruess 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3a23:[ ]+0f 25 2f d5 11 04[ ]+comnesd %xmm13,%xmm2,%xmm1 + [ ]+3a29:[ ]+0f 25 2f 52 10 04 04[ ]+comnesd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3a30:[ ]+0f 25 2f d5 11 00[ ]+comeqsd %xmm13,%xmm2,%xmm1 + [ ]+3a36:[ ]+0f 25 2f d5 11 01[ ]+comltsd %xmm13,%xmm2,%xmm1 + [ ]+3a3c:[ ]+0f 25 2f d5 11 02[ ]+comlesd %xmm13,%xmm2,%xmm1 + [ ]+3a42:[ ]+0f 25 2f d5 11 03[ ]+comunordsd %xmm13,%xmm2,%xmm1 + [ ]+3a48:[ ]+0f 25 2f d5 11 04[ ]+comnesd %xmm13,%xmm2,%xmm1 + [ ]+3a4e:[ ]+0f 25 2f d5 11 05[ ]+comnltsd %xmm13,%xmm2,%xmm1 + [ ]+3a54:[ ]+0f 25 2f d5 11 06[ ]+comnlesd %xmm13,%xmm2,%xmm1 + [ ]+3a5a:[ ]+0f 25 2f d5 11 07[ ]+comordsd %xmm13,%xmm2,%xmm1 + [ ]+3a60:[ ]+0f 25 2f d5 11 08[ ]+comueqsd %xmm13,%xmm2,%xmm1 + [ ]+3a66:[ ]+0f 25 2f d5 11 09[ ]+comultsd %xmm13,%xmm2,%xmm1 + [ ]+3a6c:[ ]+0f 25 2f d5 11 0a[ ]+comulesd %xmm13,%xmm2,%xmm1 + [ ]+3a72:[ ]+0f 25 2f d5 11 0b[ ]+comfalsesd %xmm13,%xmm2,%xmm1 + [ ]+3a78:[ ]+0f 25 2f d5 11 0c[ ]+comunesd %xmm13,%xmm2,%xmm1 + [ ]+3a7e:[ ]+0f 25 2f d5 11 0d[ ]+comunltsd %xmm13,%xmm2,%xmm1 + [ ]+3a84:[ ]+0f 25 2f d5 11 0e[ ]+comunlesd %xmm13,%xmm2,%xmm1 + [ ]+3a8a:[ ]+0f 25 2f d5 11 0f[ ]+comtruesd %xmm13,%xmm2,%xmm1 + [ ]+3a90:[ ]+0f 25 2f 52 10 04 00[ ]+comeqsd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3a97:[ ]+0f 25 2f 52 10 04 01[ ]+comltsd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3a9e:[ ]+0f 25 2f 52 10 04 02[ ]+comlesd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3aa5:[ ]+0f 25 2f 52 10 04 03[ ]+comunordsd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3aac:[ ]+0f 25 2f 52 10 04 04[ ]+comnesd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3ab3:[ ]+0f 25 2f 52 10 04 05[ ]+comnltsd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3aba:[ ]+0f 25 2f 52 10 04 06[ ]+comnlesd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3ac1:[ ]+0f 25 2f 52 10 04 07[ ]+comordsd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3ac8:[ ]+0f 25 2f 52 10 04 08[ ]+comueqsd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3acf:[ ]+0f 25 2f 52 10 04 09[ ]+comultsd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3ad6:[ ]+0f 25 2f 52 10 04 0a[ ]+comulesd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3add:[ ]+0f 25 2f 52 10 04 0b[ ]+comfalsesd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3ae4:[ ]+0f 25 2f 52 10 04 0c[ ]+comunesd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3aeb:[ ]+0f 25 2f 52 10 04 0d[ ]+comunltsd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3af2:[ ]+0f 25 2f 52 10 04 0e[ ]+comunlesd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3af9:[ ]+0f 25 2f 52 10 04 0f[ ]+comtruesd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3b00:[ ]+0f 25 2c d5 11 04[ ]+comneps %xmm13,%xmm2,%xmm1 + [ ]+3b06:[ ]+0f 25 2c 52 10 04 04[ ]+comneps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3b0d:[ ]+0f 25 2c d5 11 00[ ]+comeqps %xmm13,%xmm2,%xmm1 + [ ]+3b13:[ ]+0f 25 2c d5 11 01[ ]+comltps %xmm13,%xmm2,%xmm1 + [ ]+3b19:[ ]+0f 25 2c d5 11 02[ ]+comleps %xmm13,%xmm2,%xmm1 + [ ]+3b1f:[ ]+0f 25 2c d5 11 03[ ]+comunordps %xmm13,%xmm2,%xmm1 + [ ]+3b25:[ ]+0f 25 2c d5 11 04[ ]+comneps %xmm13,%xmm2,%xmm1 + [ ]+3b2b:[ ]+0f 25 2c d5 11 05[ ]+comnltps %xmm13,%xmm2,%xmm1 + [ ]+3b31:[ ]+0f 25 2c d5 11 06[ ]+comnleps %xmm13,%xmm2,%xmm1 + [ ]+3b37:[ ]+0f 25 2c d5 11 07[ ]+comordps %xmm13,%xmm2,%xmm1 + [ ]+3b3d:[ ]+0f 25 2c d5 11 08[ ]+comueqps %xmm13,%xmm2,%xmm1 + [ ]+3b43:[ ]+0f 25 2c d5 11 09[ ]+comultps %xmm13,%xmm2,%xmm1 + [ ]+3b49:[ ]+0f 25 2c d5 11 0a[ ]+comuleps %xmm13,%xmm2,%xmm1 + [ ]+3b4f:[ ]+0f 25 2c d5 11 0b[ ]+comfalseps %xmm13,%xmm2,%xmm1 + [ ]+3b55:[ ]+0f 25 2c d5 11 0c[ ]+comuneps %xmm13,%xmm2,%xmm1 + [ ]+3b5b:[ ]+0f 25 2c d5 11 0d[ ]+comunltps %xmm13,%xmm2,%xmm1 + [ ]+3b61:[ ]+0f 25 2c d5 11 0e[ ]+comunleps %xmm13,%xmm2,%xmm1 + [ ]+3b67:[ ]+0f 25 2c d5 11 0f[ ]+comtrueps %xmm13,%xmm2,%xmm1 + [ ]+3b6d:[ ]+0f 25 2c 52 10 04 00[ ]+comeqps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3b74:[ ]+0f 25 2c 52 10 04 01[ ]+comltps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3b7b:[ ]+0f 25 2c 52 10 04 02[ ]+comleps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3b82:[ ]+0f 25 2c 52 10 04 03[ ]+comunordps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3b89:[ ]+0f 25 2c 52 10 04 04[ ]+comneps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3b90:[ ]+0f 25 2c 52 10 04 05[ ]+comnltps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3b97:[ ]+0f 25 2c 52 10 04 06[ ]+comnleps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3b9e:[ ]+0f 25 2c 52 10 04 07[ ]+comordps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3ba5:[ ]+0f 25 2c 52 10 04 08[ ]+comueqps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3bac:[ ]+0f 25 2c 52 10 04 09[ ]+comultps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3bb3:[ ]+0f 25 2c 52 10 04 0a[ ]+comuleps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3bba:[ ]+0f 25 2c 52 10 04 0b[ ]+comfalseps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3bc1:[ ]+0f 25 2c 52 10 04 0c[ ]+comuneps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3bc8:[ ]+0f 25 2c 52 10 04 0d[ ]+comunltps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3bcf:[ ]+0f 25 2c 52 10 04 0e[ ]+comunleps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3bd6:[ ]+0f 25 2c 52 10 04 0f[ ]+comtrueps 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3bdd:[ ]+0f 25 2d d5 11 04[ ]+comnepd %xmm13,%xmm2,%xmm1 + [ ]+3be3:[ ]+0f 25 2d 52 10 04 04[ ]+comnepd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3bea:[ ]+0f 25 2d d5 11 00[ ]+comeqpd %xmm13,%xmm2,%xmm1 + [ ]+3bf0:[ ]+0f 25 2d d5 11 01[ ]+comltpd %xmm13,%xmm2,%xmm1 + [ ]+3bf6:[ ]+0f 25 2d d5 11 02[ ]+comlepd %xmm13,%xmm2,%xmm1 + [ ]+3bfc:[ ]+0f 25 2d d5 11 03[ ]+comunordpd %xmm13,%xmm2,%xmm1 + [ ]+3c02:[ ]+0f 25 2d d5 11 04[ ]+comnepd %xmm13,%xmm2,%xmm1 + [ ]+3c08:[ ]+0f 25 2d d5 11 05[ ]+comnltpd %xmm13,%xmm2,%xmm1 + [ ]+3c0e:[ ]+0f 25 2d d5 11 06[ ]+comnlepd %xmm13,%xmm2,%xmm1 + [ ]+3c14:[ ]+0f 25 2d d5 11 07[ ]+comordpd %xmm13,%xmm2,%xmm1 + [ ]+3c1a:[ ]+0f 25 2d d5 11 08[ ]+comueqpd %xmm13,%xmm2,%xmm1 + [ ]+3c20:[ ]+0f 25 2d d5 11 09[ ]+comultpd %xmm13,%xmm2,%xmm1 + [ ]+3c26:[ ]+0f 25 2d d5 11 0a[ ]+comulepd %xmm13,%xmm2,%xmm1 + [ ]+3c2c:[ ]+0f 25 2d d5 11 0b[ ]+comfalsepd %xmm13,%xmm2,%xmm1 + [ ]+3c32:[ ]+0f 25 2d d5 11 0c[ ]+comunepd %xmm13,%xmm2,%xmm1 + [ ]+3c38:[ ]+0f 25 2d d5 11 0d[ ]+comunltpd %xmm13,%xmm2,%xmm1 + [ ]+3c3e:[ ]+0f 25 2d d5 11 0e[ ]+comunlepd %xmm13,%xmm2,%xmm1 + [ ]+3c44:[ ]+0f 25 2d d5 11 0f[ ]+comtruepd %xmm13,%xmm2,%xmm1 + [ ]+3c4a:[ ]+0f 25 2d 52 10 04 00[ ]+comeqpd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3c51:[ ]+0f 25 2d 52 10 04 01[ ]+comltpd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3c58:[ ]+0f 25 2d 52 10 04 02[ ]+comlepd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3c5f:[ ]+0f 25 2d 52 10 04 03[ ]+comunordpd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3c66:[ ]+0f 25 2d 52 10 04 04[ ]+comnepd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3c6d:[ ]+0f 25 2d 52 10 04 05[ ]+comnltpd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3c74:[ ]+0f 25 2d 52 10 04 06[ ]+comnlepd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3c7b:[ ]+0f 25 2d 52 10 04 07[ ]+comordpd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3c82:[ ]+0f 25 2d 52 10 04 08[ ]+comueqpd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3c89:[ ]+0f 25 2d 52 10 04 09[ ]+comultpd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3c90:[ ]+0f 25 2d 52 10 04 0a[ ]+comulepd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3c97:[ ]+0f 25 2d 52 10 04 0b[ ]+comfalsepd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3c9e:[ ]+0f 25 2d 52 10 04 0c[ ]+comunepd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3ca5:[ ]+0f 25 2d 52 10 04 0d[ ]+comunltpd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3cac:[ ]+0f 25 2d 52 10 04 0e[ ]+comunlepd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3cb3:[ ]+0f 25 2d 52 10 04 0f[ ]+comtruepd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3cba:[ ]+0f 25 4c d5 11 04[ ]+pcomeqb %xmm13,%xmm2,%xmm1 + [ ]+3cc0:[ ]+0f 25 4c 52 10 04 04[ ]+pcomeqb 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3cc7:[ ]+0f 25 4c d5 11 00[ ]+pcomltb %xmm13,%xmm2,%xmm1 + [ ]+3ccd:[ ]+0f 25 4c d5 11 01[ ]+pcomleb %xmm13,%xmm2,%xmm1 + [ ]+3cd3:[ ]+0f 25 4c d5 11 02[ ]+pcomgtb %xmm13,%xmm2,%xmm1 + [ ]+3cd9:[ ]+0f 25 4c d5 11 03[ ]+pcomgeb %xmm13,%xmm2,%xmm1 + [ ]+3cdf:[ ]+0f 25 4c d5 11 04[ ]+pcomeqb %xmm13,%xmm2,%xmm1 + [ ]+3ce5:[ ]+0f 25 4c d5 11 05[ ]+pcomneb %xmm13,%xmm2,%xmm1 + [ ]+3ceb:[ ]+0f 25 4c 52 10 04 00[ ]+pcomltb 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3cf2:[ ]+0f 25 4c 52 10 04 01[ ]+pcomleb 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3cf9:[ ]+0f 25 4c 52 10 04 02[ ]+pcomgtb 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3d00:[ ]+0f 25 4c 52 10 04 03[ ]+pcomgeb 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3d07:[ ]+0f 25 4c 52 10 04 04[ ]+pcomeqb 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3d0e:[ ]+0f 25 4c 52 10 04 05[ ]+pcomneb 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3d15:[ ]+0f 25 4d d5 11 04[ ]+pcomeqw %xmm13,%xmm2,%xmm1 + [ ]+3d1b:[ ]+0f 25 4d 52 10 04 04[ ]+pcomeqw 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3d22:[ ]+0f 25 4d d5 11 00[ ]+pcomltw %xmm13,%xmm2,%xmm1 + [ ]+3d28:[ ]+0f 25 4d d5 11 01[ ]+pcomlew %xmm13,%xmm2,%xmm1 + [ ]+3d2e:[ ]+0f 25 4d d5 11 02[ ]+pcomgtw %xmm13,%xmm2,%xmm1 + [ ]+3d34:[ ]+0f 25 4d d5 11 03[ ]+pcomgew %xmm13,%xmm2,%xmm1 + [ ]+3d3a:[ ]+0f 25 4d d5 11 04[ ]+pcomeqw %xmm13,%xmm2,%xmm1 + [ ]+3d40:[ ]+0f 25 4d d5 11 05[ ]+pcomnew %xmm13,%xmm2,%xmm1 + [ ]+3d46:[ ]+0f 25 4d 52 10 04 00[ ]+pcomltw 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3d4d:[ ]+0f 25 4d 52 10 04 01[ ]+pcomlew 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3d54:[ ]+0f 25 4d 52 10 04 02[ ]+pcomgtw 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3d5b:[ ]+0f 25 4d 52 10 04 03[ ]+pcomgew 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3d62:[ ]+0f 25 4d 52 10 04 04[ ]+pcomeqw 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3d69:[ ]+0f 25 4d 52 10 04 05[ ]+pcomnew 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3d70:[ ]+0f 25 4e d5 11 04[ ]+pcomeqd %xmm13,%xmm2,%xmm1 + [ ]+3d76:[ ]+0f 25 4e 52 10 04 04[ ]+pcomeqd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3d7d:[ ]+0f 25 4e d5 11 00[ ]+pcomltd %xmm13,%xmm2,%xmm1 + [ ]+3d83:[ ]+0f 25 4e d5 11 01[ ]+pcomled %xmm13,%xmm2,%xmm1 + [ ]+3d89:[ ]+0f 25 4e d5 11 02[ ]+pcomgtd %xmm13,%xmm2,%xmm1 + [ ]+3d8f:[ ]+0f 25 4e d5 11 03[ ]+pcomged %xmm13,%xmm2,%xmm1 + [ ]+3d95:[ ]+0f 25 4e d5 11 04[ ]+pcomeqd %xmm13,%xmm2,%xmm1 + [ ]+3d9b:[ ]+0f 25 4e d5 11 05[ ]+pcomned %xmm13,%xmm2,%xmm1 + [ ]+3da1:[ ]+0f 25 4e 52 10 04 00[ ]+pcomltd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3da8:[ ]+0f 25 4e 52 10 04 01[ ]+pcomled 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3daf:[ ]+0f 25 4e 52 10 04 02[ ]+pcomgtd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3db6:[ ]+0f 25 4e 52 10 04 03[ ]+pcomged 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3dbd:[ ]+0f 25 4e 52 10 04 04[ ]+pcomeqd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3dc4:[ ]+0f 25 4e 52 10 04 05[ ]+pcomned 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3dcb:[ ]+0f 25 4f d5 11 04[ ]+pcomeqq %xmm13,%xmm2,%xmm1 + [ ]+3dd1:[ ]+0f 25 4f 52 10 04 04[ ]+pcomeqq 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3dd8:[ ]+0f 25 4f d5 11 00[ ]+pcomltq %xmm13,%xmm2,%xmm1 + [ ]+3dde:[ ]+0f 25 4f d5 11 01[ ]+pcomleq %xmm13,%xmm2,%xmm1 + [ ]+3de4:[ ]+0f 25 4f d5 11 02[ ]+pcomgtq %xmm13,%xmm2,%xmm1 + [ ]+3dea:[ ]+0f 25 4f d5 11 03[ ]+pcomgeq %xmm13,%xmm2,%xmm1 + [ ]+3df0:[ ]+0f 25 4f d5 11 04[ ]+pcomeqq %xmm13,%xmm2,%xmm1 + [ ]+3df6:[ ]+0f 25 4f d5 11 05[ ]+pcomneq %xmm13,%xmm2,%xmm1 + [ ]+3dfc:[ ]+0f 25 4f 52 10 04 00[ ]+pcomltq 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3e03:[ ]+0f 25 4f 52 10 04 01[ ]+pcomleq 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3e0a:[ ]+0f 25 4f 52 10 04 02[ ]+pcomgtq 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3e11:[ ]+0f 25 4f 52 10 04 03[ ]+pcomgeq 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3e18:[ ]+0f 25 4f 52 10 04 04[ ]+pcomeqq 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3e1f:[ ]+0f 25 4f 52 10 04 05[ ]+pcomneq 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3e26:[ ]+0f 25 6c d5 11 04[ ]+pcomequb %xmm13,%xmm2,%xmm1 + [ ]+3e2c:[ ]+0f 25 6c 52 10 04 04[ ]+pcomequb 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3e33:[ ]+0f 25 6c d5 11 00[ ]+pcomltub %xmm13,%xmm2,%xmm1 + [ ]+3e39:[ ]+0f 25 6c d5 11 01[ ]+pcomleub %xmm13,%xmm2,%xmm1 + [ ]+3e3f:[ ]+0f 25 6c d5 11 02[ ]+pcomgtub %xmm13,%xmm2,%xmm1 + [ ]+3e45:[ ]+0f 25 6c d5 11 03[ ]+pcomgeub %xmm13,%xmm2,%xmm1 + [ ]+3e4b:[ ]+0f 25 6c d5 11 04[ ]+pcomequb %xmm13,%xmm2,%xmm1 + [ ]+3e51:[ ]+0f 25 6c d5 11 05[ ]+pcomneub %xmm13,%xmm2,%xmm1 + [ ]+3e57:[ ]+0f 25 6c 52 10 04 00[ ]+pcomltub 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3e5e:[ ]+0f 25 6c 52 10 04 01[ ]+pcomleub 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3e65:[ ]+0f 25 6c 52 10 04 02[ ]+pcomgtub 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3e6c:[ ]+0f 25 6c 52 10 04 03[ ]+pcomgeub 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3e73:[ ]+0f 25 6c 52 10 04 04[ ]+pcomequb 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3e7a:[ ]+0f 25 6c 52 10 04 05[ ]+pcomneub 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3e81:[ ]+0f 25 6d d5 11 04[ ]+pcomequw %xmm13,%xmm2,%xmm1 + [ ]+3e87:[ ]+0f 25 6d 52 10 04 04[ ]+pcomequw 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3e8e:[ ]+0f 25 6d d5 11 00[ ]+pcomltuw %xmm13,%xmm2,%xmm1 + [ ]+3e94:[ ]+0f 25 6d d5 11 01[ ]+pcomleuw %xmm13,%xmm2,%xmm1 + [ ]+3e9a:[ ]+0f 25 6d d5 11 02[ ]+pcomgtuw %xmm13,%xmm2,%xmm1 + [ ]+3ea0:[ ]+0f 25 6d d5 11 03[ ]+pcomgeuw %xmm13,%xmm2,%xmm1 + [ ]+3ea6:[ ]+0f 25 6d d5 11 04[ ]+pcomequw %xmm13,%xmm2,%xmm1 + [ ]+3eac:[ ]+0f 25 6d d5 11 05[ ]+pcomneuw %xmm13,%xmm2,%xmm1 + [ ]+3eb2:[ ]+0f 25 6d 52 10 04 00[ ]+pcomltuw 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3eb9:[ ]+0f 25 6d 52 10 04 01[ ]+pcomleuw 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3ec0:[ ]+0f 25 6d 52 10 04 02[ ]+pcomgtuw 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3ec7:[ ]+0f 25 6d 52 10 04 03[ ]+pcomgeuw 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3ece:[ ]+0f 25 6d 52 10 04 04[ ]+pcomequw 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3ed5:[ ]+0f 25 6d 52 10 04 05[ ]+pcomneuw 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3edc:[ ]+0f 25 6e d5 11 04[ ]+pcomequd %xmm13,%xmm2,%xmm1 + [ ]+3ee2:[ ]+0f 25 6e 52 10 04 04[ ]+pcomequd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3ee9:[ ]+0f 25 6e d5 11 00[ ]+pcomltud %xmm13,%xmm2,%xmm1 + [ ]+3eef:[ ]+0f 25 6e d5 11 01[ ]+pcomleud %xmm13,%xmm2,%xmm1 + [ ]+3ef5:[ ]+0f 25 6e d5 11 02[ ]+pcomgtud %xmm13,%xmm2,%xmm1 + [ ]+3efb:[ ]+0f 25 6e d5 11 03[ ]+pcomgeud %xmm13,%xmm2,%xmm1 + [ ]+3f01:[ ]+0f 25 6e d5 11 04[ ]+pcomequd %xmm13,%xmm2,%xmm1 + [ ]+3f07:[ ]+0f 25 6e d5 11 05[ ]+pcomneud %xmm13,%xmm2,%xmm1 + [ ]+3f0d:[ ]+0f 25 6e 52 10 04 00[ ]+pcomltud 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3f14:[ ]+0f 25 6e 52 10 04 01[ ]+pcomleud 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3f1b:[ ]+0f 25 6e 52 10 04 02[ ]+pcomgtud 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3f22:[ ]+0f 25 6e 52 10 04 03[ ]+pcomgeud 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3f29:[ ]+0f 25 6e 52 10 04 04[ ]+pcomequd 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3f30:[ ]+0f 25 6e 52 10 04 05[ ]+pcomneud 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3f37:[ ]+0f 25 6f d5 11 04[ ]+pcomequq %xmm13,%xmm2,%xmm1 + [ ]+3f3d:[ ]+0f 25 6f 52 10 04 04[ ]+pcomequq 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3f44:[ ]+0f 25 6f d5 11 00[ ]+pcomltuq %xmm13,%xmm2,%xmm1 + [ ]+3f4a:[ ]+0f 25 6f d5 11 01[ ]+pcomleuq %xmm13,%xmm2,%xmm1 + [ ]+3f50:[ ]+0f 25 6f d5 11 02[ ]+pcomgtuq %xmm13,%xmm2,%xmm1 + [ ]+3f56:[ ]+0f 25 6f d5 11 03[ ]+pcomgeuq %xmm13,%xmm2,%xmm1 + [ ]+3f5c:[ ]+0f 25 6f d5 11 04[ ]+pcomequq %xmm13,%xmm2,%xmm1 + [ ]+3f62:[ ]+0f 25 6f d5 11 05[ ]+pcomneuq %xmm13,%xmm2,%xmm1 + [ ]+3f68:[ ]+0f 25 6f 52 10 04 00[ ]+pcomltuq 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3f6f:[ ]+0f 25 6f 52 10 04 01[ ]+pcomleuq 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3f76:[ ]+0f 25 6f 52 10 04 02[ ]+pcomgtuq 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3f7d:[ ]+0f 25 6f 52 10 04 03[ ]+pcomgeuq 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3f84:[ ]+0f 25 6f 52 10 04 04[ ]+pcomequq 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3f8b:[ ]+0f 25 6f 52 10 04 05[ ]+pcomneuq 0x4\(%rdx\),%xmm2,%xmm1 + [ ]+3f92:[ ]+0f 25 2e d3 10 04[ ]+comness %xmm3,%xmm2,%xmm1 + [ ]+3f98:[ ]+0f 25 2e 97 11 00 00 10 00 04[ ]+comness 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+3fa2:[ ]+0f 25 2e d3 10 00[ ]+comeqss %xmm3,%xmm2,%xmm1 + [ ]+3fa8:[ ]+0f 25 2e d3 10 01[ ]+comltss %xmm3,%xmm2,%xmm1 + [ ]+3fae:[ ]+0f 25 2e d3 10 02[ ]+comless %xmm3,%xmm2,%xmm1 + [ ]+3fb4:[ ]+0f 25 2e d3 10 03[ ]+comunordss %xmm3,%xmm2,%xmm1 + [ ]+3fba:[ ]+0f 25 2e d3 10 04[ ]+comness %xmm3,%xmm2,%xmm1 + [ ]+3fc0:[ ]+0f 25 2e d3 10 05[ ]+comnltss %xmm3,%xmm2,%xmm1 + [ ]+3fc6:[ ]+0f 25 2e d3 10 06[ ]+comnless %xmm3,%xmm2,%xmm1 + [ ]+3fcc:[ ]+0f 25 2e d3 10 07[ ]+comordss %xmm3,%xmm2,%xmm1 + [ ]+3fd2:[ ]+0f 25 2e d3 10 08[ ]+comueqss %xmm3,%xmm2,%xmm1 + [ ]+3fd8:[ ]+0f 25 2e d3 10 09[ ]+comultss %xmm3,%xmm2,%xmm1 + [ ]+3fde:[ ]+0f 25 2e d3 10 0a[ ]+comuless %xmm3,%xmm2,%xmm1 + [ ]+3fe4:[ ]+0f 25 2e d3 10 0b[ ]+comfalsess %xmm3,%xmm2,%xmm1 + [ ]+3fea:[ ]+0f 25 2e d3 10 0c[ ]+comuness %xmm3,%xmm2,%xmm1 + [ ]+3ff0:[ ]+0f 25 2e d3 10 0d[ ]+comunltss %xmm3,%xmm2,%xmm1 + [ ]+3ff6:[ ]+0f 25 2e d3 10 0e[ ]+comunless %xmm3,%xmm2,%xmm1 + [ ]+3ffc:[ ]+0f 25 2e d3 10 0f[ ]+comtruess %xmm3,%xmm2,%xmm1 + [ ]+4002:[ ]+0f 25 2e 97 11 00 00 10 00 00[ ]+comeqss 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+400c:[ ]+0f 25 2e 97 11 00 00 10 00 01[ ]+comltss 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4016:[ ]+0f 25 2e 97 11 00 00 10 00 02[ ]+comless 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4020:[ ]+0f 25 2e 97 11 00 00 10 00 03[ ]+comunordss 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+402a:[ ]+0f 25 2e 97 11 00 00 10 00 04[ ]+comness 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4034:[ ]+0f 25 2e 97 11 00 00 10 00 05[ ]+comnltss 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+403e:[ ]+0f 25 2e 97 11 00 00 10 00 06[ ]+comnless 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4048:[ ]+0f 25 2e 97 11 00 00 10 00 07[ ]+comordss 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4052:[ ]+0f 25 2e 97 11 00 00 10 00 08[ ]+comueqss 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+405c:[ ]+0f 25 2e 97 11 00 00 10 00 09[ ]+comultss 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4066:[ ]+0f 25 2e 97 11 00 00 10 00 0a[ ]+comuless 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4070:[ ]+0f 25 2e 97 11 00 00 10 00 0b[ ]+comfalsess 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+407a:[ ]+0f 25 2e 97 11 00 00 10 00 0c[ ]+comuness 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4084:[ ]+0f 25 2e 97 11 00 00 10 00 0d[ ]+comunltss 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+408e:[ ]+0f 25 2e 97 11 00 00 10 00 0e[ ]+comunless 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4098:[ ]+0f 25 2e 97 11 00 00 10 00 0f[ ]+comtruess 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+40a2:[ ]+0f 25 2f d3 10 04[ ]+comnesd %xmm3,%xmm2,%xmm1 + [ ]+40a8:[ ]+0f 25 2f 97 11 00 00 10 00 04[ ]+comnesd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+40b2:[ ]+0f 25 2f d3 10 00[ ]+comeqsd %xmm3,%xmm2,%xmm1 + [ ]+40b8:[ ]+0f 25 2f d3 10 01[ ]+comltsd %xmm3,%xmm2,%xmm1 + [ ]+40be:[ ]+0f 25 2f d3 10 02[ ]+comlesd %xmm3,%xmm2,%xmm1 + [ ]+40c4:[ ]+0f 25 2f d3 10 03[ ]+comunordsd %xmm3,%xmm2,%xmm1 + [ ]+40ca:[ ]+0f 25 2f d3 10 04[ ]+comnesd %xmm3,%xmm2,%xmm1 + [ ]+40d0:[ ]+0f 25 2f d3 10 05[ ]+comnltsd %xmm3,%xmm2,%xmm1 + [ ]+40d6:[ ]+0f 25 2f d3 10 06[ ]+comnlesd %xmm3,%xmm2,%xmm1 + [ ]+40dc:[ ]+0f 25 2f d3 10 07[ ]+comordsd %xmm3,%xmm2,%xmm1 + [ ]+40e2:[ ]+0f 25 2f d3 10 08[ ]+comueqsd %xmm3,%xmm2,%xmm1 + [ ]+40e8:[ ]+0f 25 2f d3 10 09[ ]+comultsd %xmm3,%xmm2,%xmm1 + [ ]+40ee:[ ]+0f 25 2f d3 10 0a[ ]+comulesd %xmm3,%xmm2,%xmm1 + [ ]+40f4:[ ]+0f 25 2f d3 10 0b[ ]+comfalsesd %xmm3,%xmm2,%xmm1 + [ ]+40fa:[ ]+0f 25 2f d3 10 0c[ ]+comunesd %xmm3,%xmm2,%xmm1 + [ ]+4100:[ ]+0f 25 2f d3 10 0d[ ]+comunltsd %xmm3,%xmm2,%xmm1 + [ ]+4106:[ ]+0f 25 2f d3 10 0e[ ]+comunlesd %xmm3,%xmm2,%xmm1 + [ ]+410c:[ ]+0f 25 2f d3 10 0f[ ]+comtruesd %xmm3,%xmm2,%xmm1 + [ ]+4112:[ ]+0f 25 2f 97 11 00 00 10 00 00[ ]+comeqsd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+411c:[ ]+0f 25 2f 97 11 00 00 10 00 01[ ]+comltsd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4126:[ ]+0f 25 2f 97 11 00 00 10 00 02[ ]+comlesd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4130:[ ]+0f 25 2f 97 11 00 00 10 00 03[ ]+comunordsd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+413a:[ ]+0f 25 2f 97 11 00 00 10 00 04[ ]+comnesd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4144:[ ]+0f 25 2f 97 11 00 00 10 00 05[ ]+comnltsd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+414e:[ ]+0f 25 2f 97 11 00 00 10 00 06[ ]+comnlesd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4158:[ ]+0f 25 2f 97 11 00 00 10 00 07[ ]+comordsd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4162:[ ]+0f 25 2f 97 11 00 00 10 00 08[ ]+comueqsd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+416c:[ ]+0f 25 2f 97 11 00 00 10 00 09[ ]+comultsd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4176:[ ]+0f 25 2f 97 11 00 00 10 00 0a[ ]+comulesd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4180:[ ]+0f 25 2f 97 11 00 00 10 00 0b[ ]+comfalsesd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+418a:[ ]+0f 25 2f 97 11 00 00 10 00 0c[ ]+comunesd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4194:[ ]+0f 25 2f 97 11 00 00 10 00 0d[ ]+comunltsd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+419e:[ ]+0f 25 2f 97 11 00 00 10 00 0e[ ]+comunlesd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+41a8:[ ]+0f 25 2f 97 11 00 00 10 00 0f[ ]+comtruesd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+41b2:[ ]+0f 25 2c d3 10 04[ ]+comneps %xmm3,%xmm2,%xmm1 + [ ]+41b8:[ ]+0f 25 2c 97 11 00 00 10 00 04[ ]+comneps 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+41c2:[ ]+0f 25 2c d3 10 00[ ]+comeqps %xmm3,%xmm2,%xmm1 + [ ]+41c8:[ ]+0f 25 2c d3 10 01[ ]+comltps %xmm3,%xmm2,%xmm1 + [ ]+41ce:[ ]+0f 25 2c d3 10 02[ ]+comleps %xmm3,%xmm2,%xmm1 + [ ]+41d4:[ ]+0f 25 2c d3 10 03[ ]+comunordps %xmm3,%xmm2,%xmm1 + [ ]+41da:[ ]+0f 25 2c d3 10 04[ ]+comneps %xmm3,%xmm2,%xmm1 + [ ]+41e0:[ ]+0f 25 2c d3 10 05[ ]+comnltps %xmm3,%xmm2,%xmm1 + [ ]+41e6:[ ]+0f 25 2c d3 10 06[ ]+comnleps %xmm3,%xmm2,%xmm1 + [ ]+41ec:[ ]+0f 25 2c d3 10 07[ ]+comordps %xmm3,%xmm2,%xmm1 + [ ]+41f2:[ ]+0f 25 2c d3 10 08[ ]+comueqps %xmm3,%xmm2,%xmm1 + [ ]+41f8:[ ]+0f 25 2c d3 10 09[ ]+comultps %xmm3,%xmm2,%xmm1 + [ ]+41fe:[ ]+0f 25 2c d3 10 0a[ ]+comuleps %xmm3,%xmm2,%xmm1 + [ ]+4204:[ ]+0f 25 2c d3 10 0b[ ]+comfalseps %xmm3,%xmm2,%xmm1 + [ ]+420a:[ ]+0f 25 2c d3 10 0c[ ]+comuneps %xmm3,%xmm2,%xmm1 + [ ]+4210:[ ]+0f 25 2c d3 10 0d[ ]+comunltps %xmm3,%xmm2,%xmm1 + [ ]+4216:[ ]+0f 25 2c d3 10 0e[ ]+comunleps %xmm3,%xmm2,%xmm1 + [ ]+421c:[ ]+0f 25 2c d3 10 0f[ ]+comtrueps %xmm3,%xmm2,%xmm1 + [ ]+4222:[ ]+0f 25 2c 97 11 00 00 10 00 00[ ]+comeqps 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+422c:[ ]+0f 25 2c 97 11 00 00 10 00 01[ ]+comltps 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4236:[ ]+0f 25 2c 97 11 00 00 10 00 02[ ]+comleps 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4240:[ ]+0f 25 2c 97 11 00 00 10 00 03[ ]+comunordps 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+424a:[ ]+0f 25 2c 97 11 00 00 10 00 04[ ]+comneps 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4254:[ ]+0f 25 2c 97 11 00 00 10 00 05[ ]+comnltps 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+425e:[ ]+0f 25 2c 97 11 00 00 10 00 06[ ]+comnleps 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4268:[ ]+0f 25 2c 97 11 00 00 10 00 07[ ]+comordps 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4272:[ ]+0f 25 2c 97 11 00 00 10 00 08[ ]+comueqps 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+427c:[ ]+0f 25 2c 97 11 00 00 10 00 09[ ]+comultps 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4286:[ ]+0f 25 2c 97 11 00 00 10 00 0a[ ]+comuleps 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4290:[ ]+0f 25 2c 97 11 00 00 10 00 0b[ ]+comfalseps 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+429a:[ ]+0f 25 2c 97 11 00 00 10 00 0c[ ]+comuneps 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+42a4:[ ]+0f 25 2c 97 11 00 00 10 00 0d[ ]+comunltps 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+42ae:[ ]+0f 25 2c 97 11 00 00 10 00 0e[ ]+comunleps 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+42b8:[ ]+0f 25 2c 97 11 00 00 10 00 0f[ ]+comtrueps 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+42c2:[ ]+0f 25 2d d3 10 04[ ]+comnepd %xmm3,%xmm2,%xmm1 + [ ]+42c8:[ ]+0f 25 2d 97 11 00 00 10 00 04[ ]+comnepd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+42d2:[ ]+0f 25 2d d3 10 00[ ]+comeqpd %xmm3,%xmm2,%xmm1 + [ ]+42d8:[ ]+0f 25 2d d3 10 01[ ]+comltpd %xmm3,%xmm2,%xmm1 + [ ]+42de:[ ]+0f 25 2d d3 10 02[ ]+comlepd %xmm3,%xmm2,%xmm1 + [ ]+42e4:[ ]+0f 25 2d d3 10 03[ ]+comunordpd %xmm3,%xmm2,%xmm1 + [ ]+42ea:[ ]+0f 25 2d d3 10 04[ ]+comnepd %xmm3,%xmm2,%xmm1 + [ ]+42f0:[ ]+0f 25 2d d3 10 05[ ]+comnltpd %xmm3,%xmm2,%xmm1 + [ ]+42f6:[ ]+0f 25 2d d3 10 06[ ]+comnlepd %xmm3,%xmm2,%xmm1 + [ ]+42fc:[ ]+0f 25 2d d3 10 07[ ]+comordpd %xmm3,%xmm2,%xmm1 + [ ]+4302:[ ]+0f 25 2d d3 10 08[ ]+comueqpd %xmm3,%xmm2,%xmm1 + [ ]+4308:[ ]+0f 25 2d d3 10 09[ ]+comultpd %xmm3,%xmm2,%xmm1 + [ ]+430e:[ ]+0f 25 2d d3 10 0a[ ]+comulepd %xmm3,%xmm2,%xmm1 + [ ]+4314:[ ]+0f 25 2d d3 10 0b[ ]+comfalsepd %xmm3,%xmm2,%xmm1 + [ ]+431a:[ ]+0f 25 2d d3 10 0c[ ]+comunepd %xmm3,%xmm2,%xmm1 + [ ]+4320:[ ]+0f 25 2d d3 10 0d[ ]+comunltpd %xmm3,%xmm2,%xmm1 + [ ]+4326:[ ]+0f 25 2d d3 10 0e[ ]+comunlepd %xmm3,%xmm2,%xmm1 + [ ]+432c:[ ]+0f 25 2d d3 10 0f[ ]+comtruepd %xmm3,%xmm2,%xmm1 + [ ]+4332:[ ]+0f 25 2d 97 11 00 00 10 00 00[ ]+comeqpd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+433c:[ ]+0f 25 2d 97 11 00 00 10 00 01[ ]+comltpd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4346:[ ]+0f 25 2d 97 11 00 00 10 00 02[ ]+comlepd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4350:[ ]+0f 25 2d 97 11 00 00 10 00 03[ ]+comunordpd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+435a:[ ]+0f 25 2d 97 11 00 00 10 00 04[ ]+comnepd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4364:[ ]+0f 25 2d 97 11 00 00 10 00 05[ ]+comnltpd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+436e:[ ]+0f 25 2d 97 11 00 00 10 00 06[ ]+comnlepd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4378:[ ]+0f 25 2d 97 11 00 00 10 00 07[ ]+comordpd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4382:[ ]+0f 25 2d 97 11 00 00 10 00 08[ ]+comueqpd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+438c:[ ]+0f 25 2d 97 11 00 00 10 00 09[ ]+comultpd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4396:[ ]+0f 25 2d 97 11 00 00 10 00 0a[ ]+comulepd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+43a0:[ ]+0f 25 2d 97 11 00 00 10 00 0b[ ]+comfalsepd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+43aa:[ ]+0f 25 2d 97 11 00 00 10 00 0c[ ]+comunepd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+43b4:[ ]+0f 25 2d 97 11 00 00 10 00 0d[ ]+comunltpd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+43be:[ ]+0f 25 2d 97 11 00 00 10 00 0e[ ]+comunlepd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+43c8:[ ]+0f 25 2d 97 11 00 00 10 00 0f[ ]+comtruepd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+43d2:[ ]+0f 25 4c d3 10 04[ ]+pcomeqb %xmm3,%xmm2,%xmm1 + [ ]+43d8:[ ]+0f 25 4c 97 11 00 00 10 00 04[ ]+pcomeqb 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+43e2:[ ]+0f 25 4c d3 10 00[ ]+pcomltb %xmm3,%xmm2,%xmm1 + [ ]+43e8:[ ]+0f 25 4c d3 10 01[ ]+pcomleb %xmm3,%xmm2,%xmm1 + [ ]+43ee:[ ]+0f 25 4c d3 10 02[ ]+pcomgtb %xmm3,%xmm2,%xmm1 + [ ]+43f4:[ ]+0f 25 4c d3 10 03[ ]+pcomgeb %xmm3,%xmm2,%xmm1 + [ ]+43fa:[ ]+0f 25 4c d3 10 04[ ]+pcomeqb %xmm3,%xmm2,%xmm1 + [ ]+4400:[ ]+0f 25 4c d3 10 05[ ]+pcomneb %xmm3,%xmm2,%xmm1 + [ ]+4406:[ ]+0f 25 4c 97 11 00 00 10 00 00[ ]+pcomltb 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4410:[ ]+0f 25 4c 97 11 00 00 10 00 01[ ]+pcomleb 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+441a:[ ]+0f 25 4c 97 11 00 00 10 00 02[ ]+pcomgtb 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4424:[ ]+0f 25 4c 97 11 00 00 10 00 03[ ]+pcomgeb 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+442e:[ ]+0f 25 4c 97 11 00 00 10 00 04[ ]+pcomeqb 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4438:[ ]+0f 25 4c 97 11 00 00 10 00 05[ ]+pcomneb 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4442:[ ]+0f 25 4d d3 10 04[ ]+pcomeqw %xmm3,%xmm2,%xmm1 + [ ]+4448:[ ]+0f 25 4d 97 11 00 00 10 00 04[ ]+pcomeqw 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4452:[ ]+0f 25 4d d3 10 00[ ]+pcomltw %xmm3,%xmm2,%xmm1 + [ ]+4458:[ ]+0f 25 4d d3 10 01[ ]+pcomlew %xmm3,%xmm2,%xmm1 + [ ]+445e:[ ]+0f 25 4d d3 10 02[ ]+pcomgtw %xmm3,%xmm2,%xmm1 + [ ]+4464:[ ]+0f 25 4d d3 10 03[ ]+pcomgew %xmm3,%xmm2,%xmm1 + [ ]+446a:[ ]+0f 25 4d d3 10 04[ ]+pcomeqw %xmm3,%xmm2,%xmm1 + [ ]+4470:[ ]+0f 25 4d d3 10 05[ ]+pcomnew %xmm3,%xmm2,%xmm1 + [ ]+4476:[ ]+0f 25 4d 97 11 00 00 10 00 00[ ]+pcomltw 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4480:[ ]+0f 25 4d 97 11 00 00 10 00 01[ ]+pcomlew 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+448a:[ ]+0f 25 4d 97 11 00 00 10 00 02[ ]+pcomgtw 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4494:[ ]+0f 25 4d 97 11 00 00 10 00 03[ ]+pcomgew 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+449e:[ ]+0f 25 4d 97 11 00 00 10 00 04[ ]+pcomeqw 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+44a8:[ ]+0f 25 4d 97 11 00 00 10 00 05[ ]+pcomnew 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+44b2:[ ]+0f 25 4e d3 10 04[ ]+pcomeqd %xmm3,%xmm2,%xmm1 + [ ]+44b8:[ ]+0f 25 4e 97 11 00 00 10 00 04[ ]+pcomeqd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+44c2:[ ]+0f 25 4e d3 10 00[ ]+pcomltd %xmm3,%xmm2,%xmm1 + [ ]+44c8:[ ]+0f 25 4e d3 10 01[ ]+pcomled %xmm3,%xmm2,%xmm1 + [ ]+44ce:[ ]+0f 25 4e d3 10 02[ ]+pcomgtd %xmm3,%xmm2,%xmm1 + [ ]+44d4:[ ]+0f 25 4e d3 10 03[ ]+pcomged %xmm3,%xmm2,%xmm1 + [ ]+44da:[ ]+0f 25 4e d3 10 04[ ]+pcomeqd %xmm3,%xmm2,%xmm1 + [ ]+44e0:[ ]+0f 25 4e d3 10 05[ ]+pcomned %xmm3,%xmm2,%xmm1 + [ ]+44e6:[ ]+0f 25 4e 97 11 00 00 10 00 00[ ]+pcomltd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+44f0:[ ]+0f 25 4e 97 11 00 00 10 00 01[ ]+pcomled 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+44fa:[ ]+0f 25 4e 97 11 00 00 10 00 02[ ]+pcomgtd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4504:[ ]+0f 25 4e 97 11 00 00 10 00 03[ ]+pcomged 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+450e:[ ]+0f 25 4e 97 11 00 00 10 00 04[ ]+pcomeqd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4518:[ ]+0f 25 4e 97 11 00 00 10 00 05[ ]+pcomned 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4522:[ ]+0f 25 4f d3 10 04[ ]+pcomeqq %xmm3,%xmm2,%xmm1 + [ ]+4528:[ ]+0f 25 4f 97 11 00 00 10 00 04[ ]+pcomeqq 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4532:[ ]+0f 25 4f d3 10 00[ ]+pcomltq %xmm3,%xmm2,%xmm1 + [ ]+4538:[ ]+0f 25 4f d3 10 01[ ]+pcomleq %xmm3,%xmm2,%xmm1 + [ ]+453e:[ ]+0f 25 4f d3 10 02[ ]+pcomgtq %xmm3,%xmm2,%xmm1 + [ ]+4544:[ ]+0f 25 4f d3 10 03[ ]+pcomgeq %xmm3,%xmm2,%xmm1 + [ ]+454a:[ ]+0f 25 4f d3 10 04[ ]+pcomeqq %xmm3,%xmm2,%xmm1 + [ ]+4550:[ ]+0f 25 4f d3 10 05[ ]+pcomneq %xmm3,%xmm2,%xmm1 + [ ]+4556:[ ]+0f 25 4f 97 11 00 00 10 00 00[ ]+pcomltq 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4560:[ ]+0f 25 4f 97 11 00 00 10 00 01[ ]+pcomleq 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+456a:[ ]+0f 25 4f 97 11 00 00 10 00 02[ ]+pcomgtq 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4574:[ ]+0f 25 4f 97 11 00 00 10 00 03[ ]+pcomgeq 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+457e:[ ]+0f 25 4f 97 11 00 00 10 00 04[ ]+pcomeqq 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4588:[ ]+0f 25 4f 97 11 00 00 10 00 05[ ]+pcomneq 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4592:[ ]+0f 25 6c d3 10 04[ ]+pcomequb %xmm3,%xmm2,%xmm1 + [ ]+4598:[ ]+0f 25 6c 97 11 00 00 10 00 04[ ]+pcomequb 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+45a2:[ ]+0f 25 6c d3 10 00[ ]+pcomltub %xmm3,%xmm2,%xmm1 + [ ]+45a8:[ ]+0f 25 6c d3 10 01[ ]+pcomleub %xmm3,%xmm2,%xmm1 + [ ]+45ae:[ ]+0f 25 6c d3 10 02[ ]+pcomgtub %xmm3,%xmm2,%xmm1 + [ ]+45b4:[ ]+0f 25 6c d3 10 03[ ]+pcomgeub %xmm3,%xmm2,%xmm1 + [ ]+45ba:[ ]+0f 25 6c d3 10 04[ ]+pcomequb %xmm3,%xmm2,%xmm1 + [ ]+45c0:[ ]+0f 25 6c d3 10 05[ ]+pcomneub %xmm3,%xmm2,%xmm1 + [ ]+45c6:[ ]+0f 25 6c 97 11 00 00 10 00 00[ ]+pcomltub 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+45d0:[ ]+0f 25 6c 97 11 00 00 10 00 01[ ]+pcomleub 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+45da:[ ]+0f 25 6c 97 11 00 00 10 00 02[ ]+pcomgtub 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+45e4:[ ]+0f 25 6c 97 11 00 00 10 00 03[ ]+pcomgeub 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+45ee:[ ]+0f 25 6c 97 11 00 00 10 00 04[ ]+pcomequb 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+45f8:[ ]+0f 25 6c 97 11 00 00 10 00 05[ ]+pcomneub 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4602:[ ]+0f 25 6d d3 10 04[ ]+pcomequw %xmm3,%xmm2,%xmm1 + [ ]+4608:[ ]+0f 25 6d 97 11 00 00 10 00 04[ ]+pcomequw 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4612:[ ]+0f 25 6d d3 10 00[ ]+pcomltuw %xmm3,%xmm2,%xmm1 + [ ]+4618:[ ]+0f 25 6d d3 10 01[ ]+pcomleuw %xmm3,%xmm2,%xmm1 + [ ]+461e:[ ]+0f 25 6d d3 10 02[ ]+pcomgtuw %xmm3,%xmm2,%xmm1 + [ ]+4624:[ ]+0f 25 6d d3 10 03[ ]+pcomgeuw %xmm3,%xmm2,%xmm1 + [ ]+462a:[ ]+0f 25 6d d3 10 04[ ]+pcomequw %xmm3,%xmm2,%xmm1 + [ ]+4630:[ ]+0f 25 6d d3 10 05[ ]+pcomneuw %xmm3,%xmm2,%xmm1 + [ ]+4636:[ ]+0f 25 6d 97 11 00 00 10 00 00[ ]+pcomltuw 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4640:[ ]+0f 25 6d 97 11 00 00 10 00 01[ ]+pcomleuw 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+464a:[ ]+0f 25 6d 97 11 00 00 10 00 02[ ]+pcomgtuw 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4654:[ ]+0f 25 6d 97 11 00 00 10 00 03[ ]+pcomgeuw 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+465e:[ ]+0f 25 6d 97 11 00 00 10 00 04[ ]+pcomequw 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4668:[ ]+0f 25 6d 97 11 00 00 10 00 05[ ]+pcomneuw 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4672:[ ]+0f 25 6e d3 10 04[ ]+pcomequd %xmm3,%xmm2,%xmm1 + [ ]+4678:[ ]+0f 25 6e 97 11 00 00 10 00 04[ ]+pcomequd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4682:[ ]+0f 25 6e d3 10 00[ ]+pcomltud %xmm3,%xmm2,%xmm1 + [ ]+4688:[ ]+0f 25 6e d3 10 01[ ]+pcomleud %xmm3,%xmm2,%xmm1 + [ ]+468e:[ ]+0f 25 6e d3 10 02[ ]+pcomgtud %xmm3,%xmm2,%xmm1 + [ ]+4694:[ ]+0f 25 6e d3 10 03[ ]+pcomgeud %xmm3,%xmm2,%xmm1 + [ ]+469a:[ ]+0f 25 6e d3 10 04[ ]+pcomequd %xmm3,%xmm2,%xmm1 + [ ]+46a0:[ ]+0f 25 6e d3 10 05[ ]+pcomneud %xmm3,%xmm2,%xmm1 + [ ]+46a6:[ ]+0f 25 6e 97 11 00 00 10 00 00[ ]+pcomltud 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+46b0:[ ]+0f 25 6e 97 11 00 00 10 00 01[ ]+pcomleud 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+46ba:[ ]+0f 25 6e 97 11 00 00 10 00 02[ ]+pcomgtud 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+46c4:[ ]+0f 25 6e 97 11 00 00 10 00 03[ ]+pcomgeud 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+46ce:[ ]+0f 25 6e 97 11 00 00 10 00 04[ ]+pcomequd 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+46d8:[ ]+0f 25 6e 97 11 00 00 10 00 05[ ]+pcomneud 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+46e2:[ ]+0f 25 6f d3 10 04[ ]+pcomequq %xmm3,%xmm2,%xmm1 + [ ]+46e8:[ ]+0f 25 6f 97 11 00 00 10 00 04[ ]+pcomequq 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+46f2:[ ]+0f 25 6f d3 10 00[ ]+pcomltuq %xmm3,%xmm2,%xmm1 + [ ]+46f8:[ ]+0f 25 6f d3 10 01[ ]+pcomleuq %xmm3,%xmm2,%xmm1 + [ ]+46fe:[ ]+0f 25 6f d3 10 02[ ]+pcomgtuq %xmm3,%xmm2,%xmm1 + [ ]+4704:[ ]+0f 25 6f d3 10 03[ ]+pcomgeuq %xmm3,%xmm2,%xmm1 + [ ]+470a:[ ]+0f 25 6f d3 10 04[ ]+pcomequq %xmm3,%xmm2,%xmm1 + [ ]+4710:[ ]+0f 25 6f d3 10 05[ ]+pcomneuq %xmm3,%xmm2,%xmm1 + [ ]+4716:[ ]+0f 25 6f 97 11 00 00 10 00 00[ ]+pcomltuq 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4720:[ ]+0f 25 6f 97 11 00 00 10 00 01[ ]+pcomleuq 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+472a:[ ]+0f 25 6f 97 11 00 00 10 00 02[ ]+pcomgtuq 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4734:[ ]+0f 25 6f 97 11 00 00 10 00 03[ ]+pcomgeuq 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+473e:[ ]+0f 25 6f 97 11 00 00 10 00 04[ ]+pcomequq 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4748:[ ]+0f 25 6f 97 11 00 00 10 00 05[ ]+pcomneuq 0x100000\(%r15\),%xmm2,%xmm1 + [ ]+4752:[ ]+0f 7a 12 ca[ ]+frczss %xmm2,%xmm1 + [ ]+4756:[ ]+0f 7a 12 4a 04[ ]+frczss 0x4\(%rdx\),%xmm1 + [ ]+475b:[ ]+0f 7a 13 ca[ ]+frczsd %xmm2,%xmm1 + [ ]+475f:[ ]+0f 7a 13 4a 04[ ]+frczsd 0x4\(%rdx\),%xmm1 + [ ]+4764:[ ]+0f 7a 10 ca[ ]+frczps %xmm2,%xmm1 + [ ]+4768:[ ]+0f 7a 10 4a 04[ ]+frczps 0x4\(%rdx\),%xmm1 + [ ]+476d:[ ]+0f 7a 11 ca[ ]+frczpd %xmm2,%xmm1 + [ ]+4771:[ ]+0f 7a 11 4a 04[ ]+frczpd 0x4\(%rdx\),%xmm1 + [ ]+4776:[ ]+45 0f 7a 12 dc[ ]+frczss %xmm12,%xmm11 + [ ]+477b:[ ]+45 0f 7a 12 9f 00 00 10 00[ ]+frczss 0x100000\(%r15\),%xmm11 + [ ]+4784:[ ]+45 0f 7a 13 dc[ ]+frczsd %xmm12,%xmm11 + [ ]+4789:[ ]+45 0f 7a 13 9f 00 00 10 00[ ]+frczsd 0x100000\(%r15\),%xmm11 + [ ]+4792:[ ]+45 0f 7a 10 dc[ ]+frczps %xmm12,%xmm11 + [ ]+4797:[ ]+45 0f 7a 10 9f 00 00 10 00[ ]+frczps 0x100000\(%r15\),%xmm11 + [ ]+47a0:[ ]+45 0f 7a 11 dc[ ]+frczpd %xmm12,%xmm11 + [ ]+47a5:[ ]+45 0f 7a 11 9f 00 00 10 00[ ]+frczpd 0x100000\(%r15\),%xmm11 + [ ]+47ae:[ ]+41 0f 7a 12 cc[ ]+frczss %xmm12,%xmm1 + [ ]+47b3:[ ]+0f 7a 12 4a 04[ ]+frczss 0x4\(%rdx\),%xmm1 + [ ]+47b8:[ ]+41 0f 7a 13 cc[ ]+frczsd %xmm12,%xmm1 + [ ]+47bd:[ ]+0f 7a 13 4a 04[ ]+frczsd 0x4\(%rdx\),%xmm1 + [ ]+47c2:[ ]+41 0f 7a 10 cc[ ]+frczps %xmm12,%xmm1 + [ ]+47c7:[ ]+0f 7a 10 4a 04[ ]+frczps 0x4\(%rdx\),%xmm1 + [ ]+47cc:[ ]+41 0f 7a 11 cc[ ]+frczpd %xmm12,%xmm1 + [ ]+47d1:[ ]+0f 7a 11 4a 04[ ]+frczpd 0x4\(%rdx\),%xmm1 + [ ]+47d6:[ ]+44 0f 7a 12 da[ ]+frczss %xmm2,%xmm11 + [ ]+47db:[ ]+44 0f 7a 12 5a 04[ ]+frczss 0x4\(%rdx\),%xmm11 + [ ]+47e1:[ ]+44 0f 7a 13 da[ ]+frczsd %xmm2,%xmm11 + [ ]+47e6:[ ]+44 0f 7a 13 5a 04[ ]+frczsd 0x4\(%rdx\),%xmm11 + [ ]+47ec:[ ]+44 0f 7a 10 da[ ]+frczps %xmm2,%xmm11 + [ ]+47f1:[ ]+44 0f 7a 10 5a 04[ ]+frczps 0x4\(%rdx\),%xmm11 + [ ]+47f7:[ ]+44 0f 7a 11 da[ ]+frczpd %xmm2,%xmm11 + [ ]+47fc:[ ]+44 0f 7a 11 5a 04[ ]+frczpd 0x4\(%rdx\),%xmm11 + [ ]+4802:[ ]+0f 7a 12 ca[ ]+frczss %xmm2,%xmm1 + [ ]+4806:[ ]+0f 7a 12 4a 04[ ]+frczss 0x4\(%rdx\),%xmm1 + [ ]+480b:[ ]+0f 7a 13 ca[ ]+frczsd %xmm2,%xmm1 + [ ]+480f:[ ]+0f 7a 13 4a 04[ ]+frczsd 0x4\(%rdx\),%xmm1 + [ ]+4814:[ ]+0f 7a 10 ca[ ]+frczps %xmm2,%xmm1 + [ ]+4818:[ ]+0f 7a 10 4a 04[ ]+frczps 0x4\(%rdx\),%xmm1 + [ ]+481d:[ ]+0f 7a 11 ca[ ]+frczpd %xmm2,%xmm1 + [ ]+4821:[ ]+0f 7a 11 4a 04[ ]+frczpd 0x4\(%rdx\),%xmm1 + [ ]+4826:[ ]+0f 7a 12 ca[ ]+frczss %xmm2,%xmm1 + [ ]+482a:[ ]+41 0f 7a 12 8f 00 00 10 00[ ]+frczss 0x100000\(%r15\),%xmm1 + [ ]+4833:[ ]+0f 7a 13 ca[ ]+frczsd %xmm2,%xmm1 + [ ]+4837:[ ]+41 0f 7a 13 8f 00 00 10 00[ ]+frczsd 0x100000\(%r15\),%xmm1 + [ ]+4840:[ ]+0f 7a 10 ca[ ]+frczps %xmm2,%xmm1 + [ ]+4844:[ ]+41 0f 7a 10 8f 00 00 10 00[ ]+frczps 0x100000\(%r15\),%xmm1 + [ ]+484d:[ ]+0f 7a 11 ca[ ]+frczpd %xmm2,%xmm1 + [ ]+4851:[ ]+41 0f 7a 11 8f 00 00 10 00[ ]+frczpd 0x100000\(%r15\),%xmm1 + [ ]+485a:[ ]+0f 7a 30 ca[ ]+cvtph2ps %xmm2,%xmm1 + [ ]+485e:[ ]+0f 7a 30 4a 04[ ]+cvtph2ps 0x4\(%rdx\),%xmm1 + [ ]+4863:[ ]+0f 7a 31 d1[ ]+cvtps2ph %xmm2,%xmm1 + [ ]+4867:[ ]+0f 7a 31 4a 04[ ]+cvtps2ph %xmm1,0x4\(%rdx\) + [ ]+486c:[ ]+45 0f 7a 30 dc[ ]+cvtph2ps %xmm12,%xmm11 + [ ]+4871:[ ]+45 0f 7a 30 9f 00 00 10 00[ ]+cvtph2ps 0x100000\(%r15\),%xmm11 + [ ]+487a:[ ]+45 0f 7a 31 e3[ ]+cvtps2ph %xmm12,%xmm11 + [ ]+487f:[ ]+45 0f 7a 31 9f 00 00 10 00[ ]+cvtps2ph %xmm11,0x100000\(%r15\) + [ ]+4888:[ ]+41 0f 7a 30 cc[ ]+cvtph2ps %xmm12,%xmm1 + [ ]+488d:[ ]+0f 7a 30 4a 04[ ]+cvtph2ps 0x4\(%rdx\),%xmm1 + [ ]+4892:[ ]+44 0f 7a 31 e1[ ]+cvtps2ph %xmm12,%xmm1 + [ ]+4897:[ ]+0f 7a 31 4a 04[ ]+cvtps2ph %xmm1,0x4\(%rdx\) + [ ]+489c:[ ]+44 0f 7a 30 da[ ]+cvtph2ps %xmm2,%xmm11 + [ ]+48a1:[ ]+44 0f 7a 30 5a 04[ ]+cvtph2ps 0x4\(%rdx\),%xmm11 + [ ]+48a7:[ ]+41 0f 7a 31 d3[ ]+cvtps2ph %xmm2,%xmm11 + [ ]+48ac:[ ]+44 0f 7a 31 5a 04[ ]+cvtps2ph %xmm11,0x4\(%rdx\) + [ ]+48b2:[ ]+0f 7a 30 ca[ ]+cvtph2ps %xmm2,%xmm1 + [ ]+48b6:[ ]+0f 7a 30 4a 04[ ]+cvtph2ps 0x4\(%rdx\),%xmm1 + [ ]+48bb:[ ]+0f 7a 31 d1[ ]+cvtps2ph %xmm2,%xmm1 + [ ]+48bf:[ ]+0f 7a 31 4a 04[ ]+cvtps2ph %xmm1,0x4\(%rdx\) + [ ]+48c4:[ ]+0f 7a 30 ca[ ]+cvtph2ps %xmm2,%xmm1 + [ ]+48c8:[ ]+41 0f 7a 30 8f 00 00 10 00[ ]+cvtph2ps 0x100000\(%r15\),%xmm1 + [ ]+48d1:[ ]+0f 7a 31 d1[ ]+cvtps2ph %xmm2,%xmm1 + [ ]+48d5:[ ]+41 0f 7a 31 8f 00 00 10 00[ ]+cvtps2ph %xmm1,0x100000\(%r15\) + [ ]+48de:[ ]+c3[ ]+retq[ ]* *** opcodes/i386-opc.h.~1~ 2007-08-31 11:40:01.120710000 -0400 --- opcodes/i386-opc.h 2007-08-29 12:55:16.255337000 -0400 *************** typedef struct template *** 41,47 **** /* extension_opcode is the 3 bit extension for group insns. This field is also used to store the 8-bit opcode suffix for the AMD 3DNow! instructions. ! If this template has no extension opcode (the usual case) use None */ unsigned int extension_opcode; #define None 0xffff /* If no extension_opcode is possible. */ --- 41,48 ---- /* extension_opcode is the 3 bit extension for group insns. This field is also used to store the 8-bit opcode suffix for the AMD 3DNow! instructions. ! If this template has no extension opcode (the usual case) use None ! Instructions with Drex use this to specify 2 bits for OC. */ unsigned int extension_opcode; #define None 0xffff /* If no extension_opcode is possible. */ *************** typedef struct template *** 71,95 **** #define CpuABM 0x200000 /* ABM New Instructions required */ #define CpuSSE4_1 0x400000 /* SSE4.1 Instructions required */ #define CpuSSE4_2 0x800000 /* SSE4.2 Instructions required */ /* SSE4.1/4.2 Instructions required */ #define CpuSSE4 (CpuSSE4_1|CpuSSE4_2) /* These flags are set by gas depending on the flag_code. */ ! #define Cpu64 0x4000000 /* 64bit support required */ ! #define CpuNo64 0x8000000 /* Not supported in the 64bit mode */ /* The default value for unknown CPUs - enable all features to avoid problems. */ #define CpuUnknownFlags (Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \ |CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuVMX \ |Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuSSSE3|CpuSSE4_1 \ ! |CpuSSE4_2|CpuABM|CpuSSE4a) /* the bits in opcode_modifier are used to generate the final opcode from the base_opcode. These bits also are used to detect alternate forms of the same instruction */ unsigned int opcode_modifier; /* opcode_modifier bits: */ #define D 0x1 /* has direction bit. */ #define W 0x2 /* set if operands can be words or dwords --- 72,101 ---- #define CpuABM 0x200000 /* ABM New Instructions required */ #define CpuSSE4_1 0x400000 /* SSE4.1 Instructions required */ #define CpuSSE4_2 0x800000 /* SSE4.2 Instructions required */ + #define CpuSSE5 0x1000000 /* SSE5 Instructions required */ /* SSE4.1/4.2 Instructions required */ #define CpuSSE4 (CpuSSE4_1|CpuSSE4_2) /* These flags are set by gas depending on the flag_code. */ ! #define Cpu64 0x4000000 /* 64bit support required */ ! #define CpuNo64 0x8000000 /* Not supported in the 64bit mode */ /* The default value for unknown CPUs - enable all features to avoid problems. */ #define CpuUnknownFlags (Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \ |CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuVMX \ |Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuSSSE3|CpuSSE4_1 \ ! |CpuSSE4_2|CpuABM|CpuSSE4a|CpuSSE5) /* the bits in opcode_modifier are used to generate the final opcode from the base_opcode. These bits also are used to detect alternate forms of the same instruction */ unsigned int opcode_modifier; + /* More opcode modifier bits that are used to detect alternate forms of the + same instruction. */ + unsigned int opcode_modifier2; + /* opcode_modifier bits: */ #define D 0x1 /* has direction bit. */ #define W 0x2 /* set if operands can be words or dwords *************** typedef struct template *** 125,130 **** --- 131,146 ---- #define Rex64 0x10000000 /* instruction require Rex64 prefix. */ #define Ugh 0x20000000 /* deprecated fp insn, gets a warning */ + /* Combine common options for SSE5 to reduce the number of columns the + table takes. */ + #define Sse5Common1 No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|IgnoreSize|Modrm + #define Sse5Common2 IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|Modrm + + /* Opcode modifier2 bits */ + #define Drex 0x1 /* instruction needs DREX (aka SSE5) */ + #define Drexv 0x2 /* multiple encodings for memory ops */ + #define Drexc 0x4 /* special drex for comparisons */ + /* operand_types[i] describes the type of operand i. This is made by OR'ing together all of the possible type masks. (e.g. 'operand_types[i] = Reg|Imm' specifies that operand i can be *** opcodes/i386-gen.c.~1~ 2007-08-31 11:40:01.608526000 -0400 --- opcodes/i386-gen.c 2007-08-29 12:37:00.354013000 -0400 *************** process_i386_opcodes (void) *** 104,109 **** --- 104,110 ---- char *str, *p, *last; char *name, *operands, *base_opcode, *extension_opcode; char *cpu_flags, *opcode_modifier, *operand_types [MAX_OPERANDS]; + char *opcode_modifier2; if (fp == NULL) fail (_("can't find i386-opc.tbl for reading\n")); *************** process_i386_opcodes (void) *** 175,182 **** if (str >= last) abort (); ! /* Remove the first {. */ str = remove_leading_whitespaces (str); if (*str != '{') abort (); str = remove_leading_whitespaces (str + 1); --- 176,193 ---- if (str >= last) abort (); ! /* If the next character is not '{', then we have the second set of ! opcode_modifier bits specified. */ str = remove_leading_whitespaces (str); + if (*str == '{') + opcode_modifier2 = "0"; + + else + { + opcode_modifier2 = next_field (str, &str); + str = remove_leading_whitespaces (str); + } + if (*str != '{') abort (); str = remove_leading_whitespaces (str + 1); *************** process_i386_opcodes (void) *** 223,228 **** --- 234,240 ---- cpu_flags); printf (" %s,\n", opcode_modifier); + printf (" %s,\n", opcode_modifier2); printf (" { "); *************** process_i386_opcodes (void) *** 244,250 **** printf (" } },\n"); } ! printf (" { NULL, 0, 0, 0, 0, 0, { 0 } }\n"); printf ("};\n"); } --- 256,262 ---- printf (" } },\n"); } ! printf (" { NULL, 0, 0, 0, 0, 0, 0, { 0 } }\n"); printf ("};\n"); } *** opcodes/i386-opc.tbl.~1~ 2007-08-31 11:40:01.655734000 -0400 --- opcodes/i386-opc.tbl 2007-08-29 13:01:35.032803000 -0400 *************** pmovzxwq, 2, 0x660f3834, None, CpuSSE4_1 *** 1401,1411 **** pmovzxdq, 2, 0x660f3835, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmuldq, 2, 0x660f3828, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmulld, 2, 0x660f3840, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } ! ptest, 2, 0x660f3817, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } ! roundpd, 3, 0x660f3a09, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } ! roundps, 3, 0x660f3a08, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } ! roundsd, 3, 0x660f3a0b, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } ! roundss, 3, 0x660f3a0a, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } // Streaming SIMD extensions 4.2 Instructions. --- 1401,1411 ---- pmovzxdq, 2, 0x660f3835, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmuldq, 2, 0x660f3828, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmulld, 2, 0x660f3840, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } ! ptest, 2, 0x660f3817, None, CpuSSE4_1|CpuSSE5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } ! roundpd, 3, 0x660f3a09, None, CpuSSE4_1|CpuSSE5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } ! roundps, 3, 0x660f3a08, None, CpuSSE4_1|CpuSSE5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } ! roundsd, 3, 0x660f3a0b, None, CpuSSE4_1|CpuSSE5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } ! roundss, 3, 0x660f3a0a, None, CpuSSE4_1|CpuSSE5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } // Streaming SIMD extensions 4.2 Instructions. *************** insertq, 4, 0xf20f78, None, CpuSSE4a, Mo *** 1486,1491 **** --- 1486,1749 ---- popcnt, 2, 0xf30fb8, None, CpuABM|CpuSSE4_2, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } lzcnt, 2, 0xf30fbd, None, CpuABM, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } + // SSE5 instructions + fmaddps, 4, 0x0f2400, None, CpuSSE5, Sse5Common1, Drex|Drexv, { RegXMM|LLongMem, RegXMM|LLongMem, RegXMM|LLongMem, RegXMM } + fmaddpd, 4, 0x0f2401, None, CpuSSE5, Sse5Common1, Drex|Drexv, { RegXMM|LLongMem, RegXMM|LLongMem, RegXMM|LLongMem, RegXMM } + fmaddss, 4, 0x0f2402, None, CpuSSE5, Sse5Common1, Drex|Drexv, { RegXMM|LongMem, RegXMM|LongMem, RegXMM|LongMem, RegXMM } + fmaddsd, 4, 0x0f2403, None, CpuSSE5, Sse5Common1, Drex|Drexv, { RegXMM|LLongMem, RegXMM|LLongMem, RegXMM|LLongMem, RegXMM } + fmsubps, 4, 0x0f2408, None, CpuSSE5, Sse5Common1, Drex|Drexv, { RegXMM|LLongMem, RegXMM|LLongMem, RegXMM|LLongMem, RegXMM } + fmsubpd, 4, 0x0f2409, None, CpuSSE5, Sse5Common1, Drex|Drexv, { RegXMM|LLongMem, RegXMM|LLongMem, RegXMM|LLongMem, RegXMM } + fmsubss, 4, 0x0f240a, None, CpuSSE5, Sse5Common1, Drex|Drexv, { RegXMM|LongMem, RegXMM|LongMem, RegXMM|LongMem, RegXMM } + fmsubsd, 4, 0x0f240b, None, CpuSSE5, Sse5Common1, Drex|Drexv, { RegXMM|LLongMem, RegXMM|LLongMem, RegXMM|LLongMem, RegXMM } + fnmaddps, 4, 0x0f2410, None, CpuSSE5, Sse5Common1, Drex|Drexv, { RegXMM|LLongMem, RegXMM|LLongMem, RegXMM|LLongMem, RegXMM } + fnmaddpd, 4, 0x0f2411, None, CpuSSE5, Sse5Common1, Drex|Drexv, { RegXMM|LLongMem, RegXMM|LLongMem, RegXMM|LLongMem, RegXMM } + fnmaddss, 4, 0x0f2412, None, CpuSSE5, Sse5Common1, Drex|Drexv, { RegXMM|LongMem, RegXMM|LongMem, RegXMM|LongMem, RegXMM } + fnmaddsd, 4, 0x0f2413, None, CpuSSE5, Sse5Common1, Drex|Drexv, { RegXMM|LLongMem, RegXMM|LLongMem, RegXMM|LLongMem, RegXMM } + fnmsubps, 4, 0x0f2418, None, CpuSSE5, Sse5Common1, Drex|Drexv, { RegXMM|LLongMem, RegXMM|LLongMem, RegXMM|LLongMem, RegXMM } + fnmsubpd, 4, 0x0f2419, None, CpuSSE5, Sse5Common1, Drex|Drexv, { RegXMM|LLongMem, RegXMM|LLongMem, RegXMM|LLongMem, RegXMM } + fnmsubss, 4, 0x0f241a, None, CpuSSE5, Sse5Common1, Drex|Drexv, { RegXMM|LongMem, RegXMM|LongMem, RegXMM|LongMem, RegXMM } + fnmsubsd, 4, 0x0f241b, None, CpuSSE5, Sse5Common1, Drex|Drexv, { RegXMM|LLongMem, RegXMM|LLongMem, RegXMM|LLongMem, RegXMM } + pmacssww, 4, 0x0f2485, 0x0, CpuSSE5, Sse5Common1, Drex, { RegXMM, RegXMM|LLongMem, RegXMM, RegXMM } + pmacsww, 4, 0x0f2495, 0x0, CpuSSE5, Sse5Common1, Drex, { RegXMM, RegXMM|LLongMem, RegXMM, RegXMM } + pmacsswd, 4, 0x0f2486, 0x0, CpuSSE5, Sse5Common1, Drex, { RegXMM, RegXMM|LLongMem, RegXMM, RegXMM } + pmacswd, 4, 0x0f2496, 0x0, CpuSSE5, Sse5Common1, Drex, { RegXMM, RegXMM|LLongMem, RegXMM, RegXMM } + pmacssdd, 4, 0x0f248e, 0x0, CpuSSE5, Sse5Common1, Drex, { RegXMM, RegXMM|LLongMem, RegXMM, RegXMM } + pmacsdd, 4, 0x0f249e, 0x0, CpuSSE5, Sse5Common1, Drex, { RegXMM, RegXMM|LLongMem, RegXMM, RegXMM } + pmacssdql, 4, 0x0f2487, 0x0, CpuSSE5, Sse5Common1, Drex, { RegXMM, RegXMM|LLongMem, RegXMM, RegXMM } + pmacssdqh, 4, 0x0f248f, 0x0, CpuSSE5, Sse5Common1, Drex, { RegXMM, RegXMM|LLongMem, RegXMM, RegXMM } + pmacsdql, 4, 0x0f2497, 0x0, CpuSSE5, Sse5Common1, Drex, { RegXMM, RegXMM|LLongMem, RegXMM, RegXMM } + pmacsdqh, 4, 0x0f249f, 0x0, CpuSSE5, Sse5Common1, Drex, { RegXMM, RegXMM|LLongMem, RegXMM, RegXMM } + pmadcsswd, 4, 0x0f24a6, 0x0, CpuSSE5, Sse5Common1, Drex, { RegXMM, RegXMM|LLongMem, RegXMM, RegXMM } + pmadcswd, 4, 0x0f24b6, 0x0, CpuSSE5, Sse5Common1, Drex, { RegXMM, RegXMM|LLongMem, RegXMM, RegXMM } + phaddbw, 2, 0x0f7a41, None, CpuSSE5, Sse5Common1, 0, { RegXMM|LLongMem, RegXMM } + phaddbd, 2, 0x0f7a42, None, CpuSSE5, Sse5Common1, 0, { RegXMM|LLongMem, RegXMM } + phaddbq, 2, 0x0f7a43, None, CpuSSE5, Sse5Common1, 0, { RegXMM|LLongMem, RegXMM } + phaddwd, 2, 0x0f7a46, None, CpuSSE5, Sse5Common1, 0, { RegXMM|LLongMem, RegXMM } + phaddwq, 2, 0x0f7a47, None, CpuSSE5, Sse5Common1, 0, { RegXMM|LLongMem, RegXMM } + phadddq, 2, 0x0f7a4b, None, CpuSSE5, Sse5Common1, 0, { RegXMM|LLongMem, RegXMM } + phaddubw, 2, 0x0f7a51, None, CpuSSE5, Sse5Common1, 0, { RegXMM|LLongMem, RegXMM } + phaddubd, 2, 0x0f7a52, None, CpuSSE5, Sse5Common1, 0, { RegXMM|LLongMem, RegXMM } + phaddubq, 2, 0x0f7a53, None, CpuSSE5, Sse5Common1, 0, { RegXMM|LLongMem, RegXMM } + phadduwd, 2, 0x0f7a56, None, CpuSSE5, Sse5Common1, 0, { RegXMM|LLongMem, RegXMM } + phadduwq, 2, 0x0f7a57, None, CpuSSE5, Sse5Common1, 0, { RegXMM|LLongMem, RegXMM } + phaddudq, 2, 0x0f7a5b, None, CpuSSE5, Sse5Common1, 0, { RegXMM|LLongMem, RegXMM } + phsubbw, 2, 0x0f7a61, None, CpuSSE5, Sse5Common1, 0, { RegXMM|LLongMem, RegXMM } + phsubwd, 2, 0x0f7a62, None, CpuSSE5, Sse5Common1, 0, { RegXMM|LLongMem, RegXMM } + phsubdq, 2, 0x0f7a63, None, CpuSSE5, Sse5Common1, 0, { RegXMM|LLongMem, RegXMM } + pcmov, 4, 0x0f2422, None, CpuSSE5, Sse5Common1, Drex|Drexv, { RegXMM|LLongMem, RegXMM|LLongMem, RegXMM|LLongMem, RegXMM } + pperm, 4, 0x0f2423, None, CpuSSE5, Sse5Common1, Drex|Drexv, { RegXMM|LLongMem, RegXMM|LLongMem, RegXMM|LLongMem, RegXMM } + permps, 4, 0x0f2420, None, CpuSSE5, Sse5Common1, Drex|Drexv, { RegXMM|LLongMem, RegXMM|LLongMem, RegXMM|LLongMem, RegXMM } + permpd, 4, 0x0f2421, None, CpuSSE5, Sse5Common1, Drex|Drexv, { RegXMM|LLongMem, RegXMM|LLongMem, RegXMM|LLongMem, RegXMM } + protb, 3, 0x0f2440, None, CpuSSE5, Sse5Common1, Drex|Drexv, { RegXMM|LLongMem, RegXMM|LLongMem, RegXMM } + protb, 3, 0x0f7b40, 0x0, CpuSSE5, Sse5Common1, 0, { Imm8, RegXMM, RegXMM } + protw, 3, 0x0f2441, None, CpuSSE5, Sse5Common1, Drex|Drexv, { RegXMM|LLongMem, RegXMM|LLongMem, RegXMM } + protw, 3, 0x0f7b41, 0x0, CpuSSE5, Sse5Common1, 0, { Imm8, RegXMM, RegXMM } + protd, 3, 0x0f2442, None, CpuSSE5, Sse5Common1, Drex|Drexv, { RegXMM|LLongMem, RegXMM|LLongMem, RegXMM } + protd, 3, 0x0f7b42, 0x0, CpuSSE5, Sse5Common1, 0, { Imm8, RegXMM, RegXMM } + protq, 3, 0x0f2443, None, CpuSSE5, Sse5Common1, Drex|Drexv, { RegXMM|LLongMem, RegXMM|LLongMem, RegXMM } + protq, 3, 0x0f7b43, 0x0, CpuSSE5, Sse5Common1, 0, { Imm8, RegXMM, RegXMM } + pshlb, 3, 0x0f2444, None, CpuSSE5, Sse5Common1, Drex|Drexv, { RegXMM|LLongMem, RegXMM|LLongMem, RegXMM } + pshlw, 3, 0x0f2445, None, CpuSSE5, Sse5Common1, Drex|Drexv, { RegXMM|LLongMem, RegXMM|LLongMem, RegXMM } + pshld, 3, 0x0f2446, None, CpuSSE5, Sse5Common1, Drex|Drexv, { RegXMM|LLongMem, RegXMM|LLongMem, RegXMM } + pshlq, 3, 0x0f2447, None, CpuSSE5, Sse5Common1, Drex|Drexv, { RegXMM|LLongMem, RegXMM|LLongMem, RegXMM } + pshab, 3, 0x0f2448, 0x0, CpuSSE5, Sse5Common1, Drex|Drexv, { RegXMM|LLongMem, RegXMM|LLongMem, RegXMM } + pshaw, 3, 0x0f2449, 0x0, CpuSSE5, Sse5Common1, Drex|Drexv, { RegXMM|LLongMem, RegXMM|LLongMem, RegXMM } + pshad, 3, 0x0f244a, 0x0, CpuSSE5, Sse5Common1, Drex|Drexv, { RegXMM|LLongMem, RegXMM|LLongMem, RegXMM } + pshaq, 3, 0x0f244b, 0x0, CpuSSE5, Sse5Common1, Drex|Drexv, { RegXMM|LLongMem, RegXMM|LLongMem, RegXMM } + comps, 4, 0x0f252c, 0x0, CpuSSE5, Sse5Common2, Drexc, { Imm8, RegXMM|LLongMem, RegXMM, RegXMM } + comeqps, 3, 0x0f252c, 0x0, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comltps, 3, 0x0f252c, 0x1, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comungeps, 3, 0x0f252c, 0x1, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comleps, 3, 0x0f252c, 0x2, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comungtps, 3, 0x0f252c, 0x2, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comunordps, 3, 0x0f252c, 0x3, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comneps, 3, 0x0f252c, 0x4, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comneqps, 3, 0x0f252c, 0x4, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comnltps, 3, 0x0f252c, 0x5, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comugeps, 3, 0x0f252c, 0x5, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comnleps, 3, 0x0f252c, 0x6, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comugtps, 3, 0x0f252c, 0x6, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comordps, 3, 0x0f252c, 0x7, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comueqps, 3, 0x0f252c, 0x8, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comultps, 3, 0x0f252c, 0x9, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comngeps, 3, 0x0f252c, 0x9, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comuleps, 3, 0x0f252c, 0xa, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comngtps, 3, 0x0f252c, 0xa, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comfalseps, 3, 0x0f252c, 0xb, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comuneps, 3, 0x0f252c, 0xc, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comuneqps, 3, 0x0f252c, 0xc, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comunltps, 3, 0x0f252c, 0xd, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comgeps, 3, 0x0f252c, 0xd, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comunleps, 3, 0x0f252c, 0xe, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comgtps, 3, 0x0f252c, 0xe, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comtrueps, 3, 0x0f252c, 0xf, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + compd, 4, 0x0f252d, 0x0, CpuSSE5, Sse5Common2, Drexc, { Imm8, RegXMM|LLongMem, RegXMM, RegXMM } + comeqpd, 3, 0x0f252d, 0x0, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comltpd, 3, 0x0f252d, 0x1, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comungepd, 3, 0x0f252d, 0x1, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comlepd, 3, 0x0f252d, 0x2, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comungtpd, 3, 0x0f252d, 0x2, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comunordpd, 3, 0x0f252d, 0x3, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comnepd, 3, 0x0f252d, 0x4, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comneqpd, 3, 0x0f252d, 0x4, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comnltpd, 3, 0x0f252d, 0x5, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comugepd, 3, 0x0f252d, 0x5, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comnlepd, 3, 0x0f252d, 0x6, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comugtpd, 3, 0x0f252d, 0x6, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comordpd, 3, 0x0f252d, 0x7, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comueqpd, 3, 0x0f252d, 0x8, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comultpd, 3, 0x0f252d, 0x9, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comngepd, 3, 0x0f252d, 0x9, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comulepd, 3, 0x0f252d, 0xa, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comngtpd, 3, 0x0f252d, 0xa, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comfalsepd, 3, 0x0f252d, 0xb, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comunepd, 3, 0x0f252d, 0xc, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comuneqpd, 3, 0x0f252d, 0xc, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comunltpd, 3, 0x0f252d, 0xd, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comgepd, 3, 0x0f252d, 0xd, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comunlepd, 3, 0x0f252d, 0xe, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comgtpd, 3, 0x0f252d, 0xe, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comtruepd, 3, 0x0f252d, 0xf, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comss, 4, 0x0f252e, 0x0, CpuSSE5, Sse5Common2, Drexc, { Imm8, RegXMM|LLongMem, RegXMM, RegXMM } + comeqss, 3, 0x0f252e, 0x0, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comltss, 3, 0x0f252e, 0x1, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comungess, 3, 0x0f252e, 0x1, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comless, 3, 0x0f252e, 0x2, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comungtss, 3, 0x0f252e, 0x2, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comunordss, 3, 0x0f252e, 0x3, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comness, 3, 0x0f252e, 0x4, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comneqss, 3, 0x0f252e, 0x4, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comnltss, 3, 0x0f252e, 0x5, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comugess, 3, 0x0f252e, 0x5, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comnless, 3, 0x0f252e, 0x6, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comugtss, 3, 0x0f252e, 0x6, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comordss, 3, 0x0f252e, 0x7, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comueqss, 3, 0x0f252e, 0x8, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comultss, 3, 0x0f252e, 0x9, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comngess, 3, 0x0f252e, 0x9, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comuless, 3, 0x0f252e, 0xa, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comngtss, 3, 0x0f252e, 0xa, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comfalsess, 3, 0x0f252e, 0xb, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comuness, 3, 0x0f252e, 0xc, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comuneqss, 3, 0x0f252e, 0xc, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comunltss, 3, 0x0f252e, 0xd, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comgess, 3, 0x0f252e, 0xd, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comunless, 3, 0x0f252e, 0xe, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comgtss, 3, 0x0f252e, 0xe, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comtruess, 3, 0x0f252e, 0xf, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comsd, 4, 0x0f252f, 0x0, CpuSSE5, Sse5Common2, Drexc, { Imm8, RegXMM|LLongMem, RegXMM, RegXMM } + comeqsd, 3, 0x0f252f, 0x0, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comltsd, 3, 0x0f252f, 0x1, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comungesd, 3, 0x0f252f, 0x1, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comlesd, 3, 0x0f252f, 0x2, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comungtsd, 3, 0x0f252f, 0x2, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comunordsd, 3, 0x0f252f, 0x3, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comnesd, 3, 0x0f252f, 0x4, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comneqsd, 3, 0x0f252f, 0x4, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comnltsd, 3, 0x0f252f, 0x5, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comugesd, 3, 0x0f252f, 0x5, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comnlesd, 3, 0x0f252f, 0x6, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comugtsd, 3, 0x0f252f, 0x6, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comordsd, 3, 0x0f252f, 0x7, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comueqsd, 3, 0x0f252f, 0x8, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comultsd, 3, 0x0f252f, 0x9, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comngesd, 3, 0x0f252f, 0x9, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comulesd, 3, 0x0f252f, 0xa, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comngtsd, 3, 0x0f252f, 0xa, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comfalsesd, 3, 0x0f252f, 0xb, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comunesd, 3, 0x0f252f, 0xc, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comuneqsd, 3, 0x0f252f, 0xc, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comunltsd, 3, 0x0f252f, 0xd, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comgesd, 3, 0x0f252f, 0xd, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comunlesd, 3, 0x0f252f, 0xe, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comgtsd, 3, 0x0f252f, 0xe, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + comtruesd, 3, 0x0f252f, 0xf, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomub, 4, 0x0f256c, 0x0, CpuSSE5, Sse5Common2, Drexc, { Imm8, RegXMM|LLongMem, RegXMM, RegXMM } + pcomltub, 3, 0x0f256c, 0x0, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomleub, 3, 0x0f256c, 0x1, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomgtub, 3, 0x0f256c, 0x2, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomgeub, 3, 0x0f256c, 0x3, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomequb, 3, 0x0f256c, 0x4, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomnequb, 3, 0x0f256c, 0x5, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomneub, 3, 0x0f256c, 0x5, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomfalseub,3, 0x0f256c, 0x6, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomtrueub, 3, 0x0f256c, 0x7, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomuw, 4, 0x0f256d, 0x0, CpuSSE5, Sse5Common2, Drexc, { Imm8, RegXMM|LLongMem, RegXMM, RegXMM } + pcomltuw, 3, 0x0f256d, 0x0, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomleuw, 3, 0x0f256d, 0x1, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomgtuw, 3, 0x0f256d, 0x2, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomgeuw, 3, 0x0f256d, 0x3, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomequw, 3, 0x0f256d, 0x4, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomnequw, 3, 0x0f256d, 0x5, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomneuw, 3, 0x0f256d, 0x5, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomfalseuw,3, 0x0f256d, 0x6, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomtrueuw, 3, 0x0f256d, 0x7, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomud, 4, 0x0f256e, 0x0, CpuSSE5, Sse5Common2, Drexc, { Imm8, RegXMM|LLongMem, RegXMM, RegXMM } + pcomltud, 3, 0x0f256e, 0x0, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomleud, 3, 0x0f256e, 0x1, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomgtud, 3, 0x0f256e, 0x2, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomgeud, 3, 0x0f256e, 0x3, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomequd, 3, 0x0f256e, 0x4, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomnequd, 3, 0x0f256e, 0x5, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomneud, 3, 0x0f256e, 0x5, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomfalseud,3, 0x0f256e, 0x6, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomtrueud, 3, 0x0f256e, 0x7, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomuq, 4, 0x0f256f, 0x0, CpuSSE5, Sse5Common2, Drexc, { Imm8, RegXMM|LLongMem, RegXMM, RegXMM } + pcomltuq, 3, 0x0f256f, 0x0, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomleuq, 3, 0x0f256f, 0x1, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomgtuq, 3, 0x0f256f, 0x2, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomgeuq, 3, 0x0f256f, 0x3, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomequq, 3, 0x0f256f, 0x4, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomnequq, 3, 0x0f256f, 0x5, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomneuq, 3, 0x0f256f, 0x5, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomfalseuq,3, 0x0f256f, 0x6, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomtrueuq, 3, 0x0f256f, 0x7, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomb, 4, 0x0f254c, 0x0, CpuSSE5, Sse5Common2, Drexc, { Imm8, RegXMM|LLongMem, RegXMM, RegXMM } + pcomltb, 3, 0x0f254c, 0x0, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomleb, 3, 0x0f254c, 0x1, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomgtb, 3, 0x0f254c, 0x2, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomgeb, 3, 0x0f254c, 0x3, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomeqb, 3, 0x0f254c, 0x4, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomneqb, 3, 0x0f254c, 0x5, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomneb, 3, 0x0f254c, 0x5, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomfalseb, 3, 0x0f254c, 0x6, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomtrueb, 3, 0x0f254c, 0x7, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomw, 4, 0x0f254d, 0x0, CpuSSE5, Sse5Common2, Drexc, { Imm8, RegXMM|LLongMem, RegXMM, RegXMM } + pcomltw, 3, 0x0f254d, 0x0, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomlew, 3, 0x0f254d, 0x1, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomgtw, 3, 0x0f254d, 0x2, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomgew, 3, 0x0f254d, 0x3, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomeqw, 3, 0x0f254d, 0x4, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomneqw, 3, 0x0f254d, 0x5, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomnew, 3, 0x0f254d, 0x5, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomfalsew, 3, 0x0f254d, 0x6, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomtruew, 3, 0x0f254d, 0x7, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomd, 4, 0x0f254e, 0x0, CpuSSE5, Sse5Common2, Drexc, { Imm8, RegXMM|LLongMem, RegXMM, RegXMM } + pcomltd, 3, 0x0f254e, 0x0, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomled, 3, 0x0f254e, 0x1, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomgtd, 3, 0x0f254e, 0x2, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomged, 3, 0x0f254e, 0x3, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomeqd, 3, 0x0f254e, 0x4, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomneqd, 3, 0x0f254e, 0x5, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomned, 3, 0x0f254e, 0x5, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomfalsed, 3, 0x0f254e, 0x6, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomtrued, 3, 0x0f254e, 0x7, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomq, 4, 0x0f254f, 0x0, CpuSSE5, Sse5Common2, Drexc, { Imm8, RegXMM|LLongMem, RegXMM, RegXMM } + pcomltq, 3, 0x0f254f, 0x0, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomleq, 3, 0x0f254f, 0x1, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomgtq, 3, 0x0f254f, 0x2, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomgeq, 3, 0x0f254f, 0x3, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomeqq, 3, 0x0f254f, 0x4, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomneqq, 3, 0x0f254f, 0x5, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomneq, 3, 0x0f254f, 0x5, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomfalseq, 3, 0x0f254f, 0x6, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + pcomtrueq, 3, 0x0f254f, 0x7, CpuSSE5, Sse5Common2|ImmExt, Drexc, { RegXMM|LLongMem, RegXMM, RegXMM } + frczps, 2, 0x0f7a10, None, CpuSSE5, Sse5Common2, 0, { RegXMM|LLongMem, RegXMM } + frczpd, 2, 0x0f7a11, None, CpuSSE5, Sse5Common2, 0, { RegXMM|LLongMem, RegXMM } + frczss, 2, 0x0f7a12, None, CpuSSE5, Sse5Common2, 0, { RegXMM|LongMem, RegXMM } + frczsd, 2, 0x0f7a13, None, CpuSSE5, Sse5Common2, 0, { RegXMM|LLongMem, RegXMM } + cvtph2ps, 2, 0x0f7a30, None, CpuSSE5, Sse5Common1, 0, { RegXMM|LongMem, RegXMM } + cvtps2ph, 2, 0x0f7a31, None, CpuSSE5, Sse5Common1, 0, { RegXMM, RegXMM|LongMem } // VIA PadLock extensions. xstore-rng, 0, 0xfa7, 0xc0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } *** opcodes/i386-tbl.h.~1~ 2007-08-31 11:40:01.719802000 -0400 --- opcodes/i386-tbl.h 2007-08-31 11:05:21.588891000 -0400 *************** const template i386_optab[] = *** 24,4312 **** { { "mov", 2, 0xa0, None, Cpu64, D|W|No_sSuf|No_xSuf, { Disp64, Acc } }, { "mov", 2, 0xa0, None, CpuNo64, D|W|No_sSuf|No_qSuf|No_xSuf, { Disp16|Disp32, Acc } }, { "mov", 2, 0x88, None, 0, D|W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "mov", 2, 0xb0, None, 0, W|ShortForm|No_sSuf|No_qSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32 } }, { "mov", 2, 0xc6, 0x0, 0, W|Modrm|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "mov", 2, 0xb0, None, Cpu64, W|ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, { Imm64, Reg64 } }, { "mov", 2, 0x8c, None, 0, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { SReg2, Reg16|Reg32|Reg64|RegMem } }, { "mov", 2, 0x8c, None, 0, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { SReg2, BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "mov", 2, 0x8c, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { SReg3, Reg16|Reg32|Reg64|RegMem } }, { "mov", 2, 0x8c, None, Cpu386, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { SReg3, BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "mov", 2, 0x8e, None, 0, Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64, SReg2 } }, { "mov", 2, 0x8e, None, 0, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, SReg2 } }, { "mov", 2, 0x8e, None, Cpu386, Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64, SReg3 } }, { "mov", 2, 0x8e, None, Cpu386, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, SReg3 } }, { "mov", 2, 0xf20, None, Cpu386|CpuNo64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf, { Control, Reg32|RegMem } }, { "mov", 2, 0xf20, None, Cpu64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Control, Reg64|RegMem } }, { "mov", 2, 0xf21, None, Cpu386|CpuNo64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf, { Debug, Reg32|RegMem } }, { "mov", 2, 0xf21, None, Cpu64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Debug, Reg64|RegMem } }, { "mov", 2, 0xf24, None, Cpu386|CpuNo64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf, { Test, Reg32|RegMem } }, { "movabs", 2, 0xa0, None, Cpu64, D|W|No_sSuf|No_xSuf, { Disp64, Acc } }, { "movabs", 2, 0xb0, None, Cpu64, W|ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, { Imm64, Reg64 } }, { "movsbl", 2, 0xfbe, None, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } }, { "movsbw", 2, 0xfbe, None, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16 } }, { "movswl", 2, 0xfbf, None, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } }, { "movsbq", 2, 0xfbe, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } }, { "movswq", 2, 0xfbf, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } }, { "movslq", 2, 0x63, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, { Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } }, { "movsx", 2, 0xfbe, None, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "movsx", 2, 0xfbf, None, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 } }, { "movsx", 2, 0x63, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, { Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } }, { "movzb", 2, 0xfb6, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "movzbl", 2, 0xfb6, None, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } }, { "movzbw", 2, 0xfb6, None, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16 } }, { "movzwl", 2, 0xfb7, None, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } }, { "movzbq", 2, 0xfb6, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } }, { "movzwq", 2, 0xfb7, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } }, { "movzx", 2, 0xfb6, None, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "movzx", 2, 0xfb7, None, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 } }, { "push", 1, 0x50, None, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64 } }, { "push", 1, 0xff, 0x6, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "push", 1, 0x6a, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8S } }, { "push", 1, 0x68, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Imm16|Imm32 } }, { "push", 1, 0x6, None, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { SReg2 } }, { "push", 1, 0xfa0, None, Cpu386|CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { SReg3 } }, { "push", 1, 0x50, None, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Reg16|Reg64 } }, { "push", 1, 0xff, 0x6, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "push", 1, 0x6a, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Imm8S } }, { "push", 1, 0x68, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Imm16|Imm32S } }, { "push", 1, 0xfa0, None, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { SReg3 } }, { "pusha", 0, 0x60, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "pop", 1, 0x58, None, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64 } }, { "pop", 1, 0x8f, 0x0, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "pop", 1, 0x7, None, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { SReg2 } }, { "pop", 1, 0xfa1, None, Cpu386|CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { SReg3 } }, { "pop", 1, 0x58, None, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Reg16|Reg64 } }, { "pop", 1, 0x8f, 0x0, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "pop", 1, 0xfa1, None, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { SReg3 } }, { "popa", 0, 0x61, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "xchg", 2, 0x90, None, 0, ShortForm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64, Acc } }, { "xchg", 2, 0x90, None, 0, ShortForm|No_bSuf|No_sSuf|No_xSuf, { Acc, Reg16|Reg32|Reg64 } }, { "xchg", 2, 0x86, None, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "xchg", 2, 0x86, None, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg8|Reg16|Reg32|Reg64 } }, { "in", 2, 0xe4, None, 0, W|No_sSuf|No_qSuf|No_xSuf, { Imm8, Acc } }, { "in", 2, 0xec, None, 0, W|No_sSuf|No_qSuf|No_xSuf, { InOutPortReg, Acc } }, { "in", 1, 0xe4, None, 0, W|No_sSuf|No_qSuf|No_xSuf, { Imm8 } }, { "in", 1, 0xec, None, 0, W|No_sSuf|No_qSuf|No_xSuf, { InOutPortReg } }, { "out", 2, 0xe6, None, 0, W|No_sSuf|No_qSuf|No_xSuf, { Acc, Imm8 } }, { "out", 2, 0xee, None, 0, W|No_sSuf|No_qSuf|No_xSuf, { Acc, InOutPortReg } }, { "out", 1, 0xe6, None, 0, W|No_sSuf|No_qSuf|No_xSuf, { Imm8 } }, { "out", 1, 0xee, None, 0, W|No_sSuf|No_qSuf|No_xSuf, { InOutPortReg } }, { "lea", 2, 0x8d, None, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "lds", 2, 0xc5, None, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "les", 2, 0xc4, None, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "lfs", 2, 0xfb4, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "lgs", 2, 0xfb5, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "lss", 2, 0xfb2, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "clc", 0, 0xf8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "cld", 0, 0xfc, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "cli", 0, 0xfa, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "clts", 0, 0xf06, None, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "cmc", 0, 0xf5, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "lahf", 0, 0x9f, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "sahf", 0, 0x9e, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "pushf", 0, 0x9c, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "pushf", 0, 0x9c, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { 0 } }, { "popf", 0, 0x9d, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "popf", 0, 0x9d, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { 0 } }, { "stc", 0, 0xf9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "std", 0, 0xfd, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "sti", 0, 0xfb, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "add", 2, 0x0, None, 0, D|W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "add", 2, 0x83, 0x0, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "add", 2, 0x4, None, 0, W|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Acc } }, { "add", 2, 0x80, 0x0, 0, W|Modrm|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "inc", 1, 0x40, None, CpuNo64, ShortForm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64 } }, { "inc", 1, 0xfe, 0x0, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sub", 2, 0x28, None, 0, D|W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sub", 2, 0x83, 0x5, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sub", 2, 0x2c, None, 0, W|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Acc } }, { "sub", 2, 0x80, 0x5, 0, W|Modrm|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "dec", 1, 0x48, None, CpuNo64, ShortForm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64 } }, { "dec", 1, 0xfe, 0x1, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sbb", 2, 0x18, None, 0, D|W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sbb", 2, 0x83, 0x3, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sbb", 2, 0x1c, None, 0, W|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Acc } }, { "sbb", 2, 0x80, 0x3, 0, W|Modrm|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "cmp", 2, 0x38, None, 0, D|W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "cmp", 2, 0x83, 0x7, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "cmp", 2, 0x3c, None, 0, W|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Acc } }, { "cmp", 2, 0x80, 0x7, 0, W|Modrm|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "test", 2, 0x84, None, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "test", 2, 0x84, None, 0, W|Modrm|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg8|Reg16|Reg32|Reg64 } }, { "test", 2, 0xa8, None, 0, W|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Acc } }, { "test", 2, 0xf6, 0x0, 0, W|Modrm|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "and", 2, 0x20, None, 0, D|W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "and", 2, 0x83, 0x4, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "and", 2, 0x24, None, 0, W|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Acc } }, { "and", 2, 0x80, 0x4, 0, W|Modrm|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "or", 2, 0x8, None, 0, D|W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "or", 2, 0x83, 0x1, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "or", 2, 0xc, None, 0, W|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Acc } }, { "or", 2, 0x80, 0x1, 0, W|Modrm|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "xor", 2, 0x30, None, 0, D|W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "xor", 2, 0x83, 0x6, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "xor", 2, 0x34, None, 0, W|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Acc } }, { "xor", 2, 0x80, 0x6, 0, W|Modrm|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "clr", 1, 0x30, None, 0, W|Modrm|No_sSuf|No_xSuf|RegKludge, { Reg8|Reg16|Reg32|Reg64 } }, { "adc", 2, 0x10, None, 0, D|W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "adc", 2, 0x83, 0x2, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "adc", 2, 0x14, None, 0, W|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Acc } }, { "adc", 2, 0x80, 0x2, 0, W|Modrm|No_sSuf|No_xSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "neg", 1, 0xf6, 0x3, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "not", 1, 0xf6, 0x2, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "aaa", 0, 0x37, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "aas", 0, 0x3f, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "daa", 0, 0x27, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "das", 0, 0x2f, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "aad", 0, 0xd50a, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "aad", 1, 0xd5, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8 } }, { "aam", 0, 0xd40a, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "aam", 1, 0xd4, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8 } }, { "cbw", 0, 0x98, None, 0, Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "cdqe", 0, 0x98, None, Cpu64, Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "cwde", 0, 0x98, None, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "cwd", 0, 0x99, None, 0, Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "cdq", 0, 0x99, None, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "cqo", 0, 0x99, None, Cpu64, Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "cbtw", 0, 0x98, None, 0, Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "cltq", 0, 0x98, None, Cpu64, Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "cwtl", 0, 0x98, None, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "cwtd", 0, 0x99, None, 0, Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "cltd", 0, 0x99, None, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "cqto", 0, 0x99, None, Cpu64, Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "mul", 1, 0xf6, 0x4, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "imul", 1, 0xf6, 0x5, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "imul", 2, 0xfaf, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "imul", 3, 0x6b, None, Cpu186, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "imul", 3, 0x69, None, Cpu186, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "imul", 2, 0x6b, None, Cpu186, Modrm|No_bSuf|No_sSuf|No_xSuf|RegKludge, { Imm8S, Reg16|Reg32|Reg64 } }, { "imul", 2, 0x69, None, Cpu186, Modrm|No_bSuf|No_sSuf|No_xSuf|RegKludge, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64 } }, { "div", 1, 0xf6, 0x6, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "div", 2, 0xf6, 0x6, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Acc } }, { "idiv", 1, 0xf6, 0x7, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "idiv", 2, 0xf6, 0x7, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Acc } }, { "rol", 2, 0xd0, 0x0, 0, W|Modrm|No_sSuf|No_xSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "rol", 2, 0xc0, 0x0, Cpu186, W|Modrm|No_sSuf|No_xSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "rol", 2, 0xd2, 0x0, 0, W|Modrm|No_sSuf|No_xSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "rol", 1, 0xd0, 0x0, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "ror", 2, 0xd0, 0x1, 0, W|Modrm|No_sSuf|No_xSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "ror", 2, 0xc0, 0x1, Cpu186, W|Modrm|No_sSuf|No_xSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "ror", 2, 0xd2, 0x1, 0, W|Modrm|No_sSuf|No_xSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "ror", 1, 0xd0, 0x1, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "rcl", 2, 0xd0, 0x2, 0, W|Modrm|No_sSuf|No_xSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "rcl", 2, 0xc0, 0x2, Cpu186, W|Modrm|No_sSuf|No_xSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "rcl", 2, 0xd2, 0x2, 0, W|Modrm|No_sSuf|No_xSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "rcl", 1, 0xd0, 0x2, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "rcr", 2, 0xd0, 0x3, 0, W|Modrm|No_sSuf|No_xSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "rcr", 2, 0xc0, 0x3, Cpu186, W|Modrm|No_sSuf|No_xSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "rcr", 2, 0xd2, 0x3, 0, W|Modrm|No_sSuf|No_xSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "rcr", 1, 0xd0, 0x3, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sal", 2, 0xd0, 0x4, 0, W|Modrm|No_sSuf|No_xSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sal", 2, 0xc0, 0x4, Cpu186, W|Modrm|No_sSuf|No_xSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sal", 2, 0xd2, 0x4, 0, W|Modrm|No_sSuf|No_xSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sal", 1, 0xd0, 0x4, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "shl", 2, 0xd0, 0x4, 0, W|Modrm|No_sSuf|No_xSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "shl", 2, 0xc0, 0x4, Cpu186, W|Modrm|No_sSuf|No_xSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "shl", 2, 0xd2, 0x4, 0, W|Modrm|No_sSuf|No_xSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "shl", 1, 0xd0, 0x4, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "shr", 2, 0xd0, 0x5, 0, W|Modrm|No_sSuf|No_xSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "shr", 2, 0xc0, 0x5, Cpu186, W|Modrm|No_sSuf|No_xSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "shr", 2, 0xd2, 0x5, 0, W|Modrm|No_sSuf|No_xSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "shr", 1, 0xd0, 0x5, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sar", 2, 0xd0, 0x7, 0, W|Modrm|No_sSuf|No_xSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sar", 2, 0xc0, 0x7, Cpu186, W|Modrm|No_sSuf|No_xSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sar", 2, 0xd2, 0x7, 0, W|Modrm|No_sSuf|No_xSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sar", 1, 0xd0, 0x7, 0, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "shld", 3, 0xfa4, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "shld", 3, 0xfa5, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "shld", 2, 0xfa5, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "shrd", 3, 0xfac, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "shrd", 3, 0xfad, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "shrd", 2, 0xfad, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "call", 1, 0xe8, None, CpuNo64, JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Disp16|Disp32 } }, { "call", 1, 0xe8, None, Cpu64, JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Disp16|Disp32 } }, { "call", 1, 0xff, 0x2, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } }, { "call", 1, 0xff, 0x2, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } }, { "call", 2, 0x9a, None, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Imm16, Imm16|Imm32 } }, { "call", 1, 0xff, 0x3, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } }, { "lcall", 2, 0x9a, None, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Imm16, Imm16|Imm32 } }, { "lcall", 1, 0xff, 0x3, 0, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } }, { "jmp", 1, 0xeb, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jmp", 1, 0xff, 0x4, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } }, { "jmp", 1, 0xff, 0x4, Cpu64, Modrm|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } }, { "jmp", 2, 0xea, None, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Imm16, Imm16|Imm32 } }, { "jmp", 1, 0xff, 0x5, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } }, { "ljmp", 2, 0xea, None, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Imm16, Imm16|Imm32 } }, { "ljmp", 1, 0xff, 0x5, 0, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } }, { "ret", 0, 0xc3, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "ret", 1, 0xc2, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Imm16 } }, { "ret", 0, 0xc3, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { 0 } }, { "ret", 1, 0xc2, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Imm16 } }, { "lret", 0, 0xcb, None, 0, DefaultSize|No_bSuf|No_sSuf|No_xSuf, { 0 } }, { "lret", 1, 0xca, None, 0, DefaultSize|No_bSuf|No_sSuf|No_xSuf, { Imm16 } }, { "enter", 2, 0xc8, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Imm16, Imm8 } }, { "enter", 2, 0xc8, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Imm16, Imm8 } }, { "leave", 0, 0xc9, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "leave", 0, 0xc9, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { 0 } }, { "jo", 1, 0x70, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jno", 1, 0x71, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jb", 1, 0x72, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jc", 1, 0x72, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jnae", 1, 0x72, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jnb", 1, 0x73, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jnc", 1, 0x73, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jae", 1, 0x73, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "je", 1, 0x74, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jz", 1, 0x74, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jne", 1, 0x75, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jnz", 1, 0x75, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jbe", 1, 0x76, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jna", 1, 0x76, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jnbe", 1, 0x77, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "ja", 1, 0x77, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "js", 1, 0x78, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jns", 1, 0x79, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jp", 1, 0x7a, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jpe", 1, 0x7a, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jnp", 1, 0x7b, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jpo", 1, 0x7b, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jl", 1, 0x7c, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jnge", 1, 0x7c, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jnl", 1, 0x7d, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jge", 1, 0x7d, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jle", 1, 0x7e, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jng", 1, 0x7e, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jnle", 1, 0x7f, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jg", 1, 0x7f, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jcxz", 1, 0xe3, None, CpuNo64, JumpByte|Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jecxz", 1, 0xe3, None, CpuNo64, JumpByte|Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jecxz", 1, 0x67e3, None, Cpu64, JumpByte|Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jrcxz", 1, 0xe3, None, Cpu64, JumpByte|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "loop", 1, 0xe2, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "loop", 1, 0xe2, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "loopz", 1, 0xe1, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "loopz", 1, 0xe1, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "loope", 1, 0xe1, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "loope", 1, 0xe1, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "loopnz", 1, 0xe0, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "loopnz", 1, 0xe0, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "loopne", 1, 0xe0, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "loopne", 1, 0xe0, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "seto", 1, 0xf90, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setno", 1, 0xf91, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setb", 1, 0xf92, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setc", 1, 0xf92, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setnae", 1, 0xf92, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setnb", 1, 0xf93, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setnc", 1, 0xf93, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setae", 1, 0xf93, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sete", 1, 0xf94, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setz", 1, 0xf94, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setne", 1, 0xf95, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setnz", 1, 0xf95, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setbe", 1, 0xf96, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setna", 1, 0xf96, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setnbe", 1, 0xf97, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "seta", 1, 0xf97, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sets", 1, 0xf98, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setns", 1, 0xf99, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setp", 1, 0xf9a, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setpe", 1, 0xf9a, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setnp", 1, 0xf9b, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setpo", 1, 0xf9b, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setl", 1, 0xf9c, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setnge", 1, 0xf9c, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setnl", 1, 0xf9d, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setge", 1, 0xf9d, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setle", 1, 0xf9e, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setng", 1, 0xf9e, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setnle", 1, 0xf9f, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setg", 1, 0xf9f, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "cmps", 0, 0xa6, None, 0, W|No_sSuf|No_xSuf|IsString, { 0 } }, { "cmps", 2, 0xa6, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg, BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "scmp", 0, 0xa6, None, 0, W|No_sSuf|No_xSuf|IsString, { 0 } }, { "scmp", 2, 0xa6, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg, BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "ins", 0, 0x6c, None, Cpu186, W|No_sSuf|No_qSuf|No_xSuf|IsString, { 0 } }, { "ins", 2, 0x6c, None, Cpu186, W|No_sSuf|No_qSuf|No_xSuf|IsString, { InOutPortReg, BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, { "outs", 0, 0x6e, None, Cpu186, W|No_sSuf|No_qSuf|No_xSuf|IsString, { 0 } }, { "outs", 2, 0x6e, None, Cpu186, W|No_sSuf|No_qSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, InOutPortReg } }, { "lods", 0, 0xac, None, 0, W|No_sSuf|No_xSuf|IsString, { 0 } }, { "lods", 1, 0xac, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "lods", 2, 0xac, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Acc } }, { "slod", 0, 0xac, None, 0, W|No_sSuf|No_xSuf|IsString, { 0 } }, { "slod", 1, 0xac, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "slod", 2, 0xac, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Acc } }, { "movs", 0, 0xa4, None, 0, W|No_sSuf|No_xSuf|IsString, { 0 } }, { "movs", 2, 0xa4, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, { "smov", 0, 0xa4, None, 0, W|No_sSuf|No_xSuf|IsString, { 0 } }, { "smov", 2, 0xa4, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, { "scas", 0, 0xae, None, 0, W|No_sSuf|No_xSuf|IsString, { 0 } }, { "scas", 1, 0xae, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, { "scas", 2, 0xae, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg, Acc } }, { "ssca", 0, 0xae, None, 0, W|No_sSuf|No_xSuf|IsString, { 0 } }, { "ssca", 1, 0xae, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, { "ssca", 2, 0xae, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg, Acc } }, { "stos", 0, 0xaa, None, 0, W|No_sSuf|No_xSuf|IsString, { 0 } }, { "stos", 1, 0xaa, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, { "stos", 2, 0xaa, None, 0, W|No_sSuf|No_xSuf|IsString, { Acc, BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, { "ssto", 0, 0xaa, None, 0, W|No_sSuf|No_xSuf|IsString, { 0 } }, { "ssto", 1, 0xaa, None, 0, W|No_sSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, { "ssto", 2, 0xaa, None, 0, W|No_sSuf|No_xSuf|IsString, { Acc, BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, { "xlat", 0, 0xd7, None, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString, { 0 } }, { "xlat", 1, 0xd7, None, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "bsf", 2, 0xfbc, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "bsr", 2, 0xfbd, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "bt", 2, 0xfa3, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "bt", 2, 0xfba, 0x4, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "btc", 2, 0xfbb, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "btc", 2, 0xfba, 0x7, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "btr", 2, 0xfb3, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "btr", 2, 0xfba, 0x6, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "bts", 2, 0xfab, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "bts", 2, 0xfba, 0x5, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, { Imm8, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "int", 1, 0xcd, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8 } }, { "int3", 0, 0xcc, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "into", 0, 0xce, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "iret", 0, 0xcf, None, 0, DefaultSize|No_bSuf|No_sSuf|No_xSuf, { 0 } }, { "rsm", 0, 0xfaa, None, Cpu386, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "bound", 2, 0x62, None, Cpu186|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64, BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "hlt", 0, 0xf4, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "nop", 1, 0xf1f, 0x0, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "nop", 0, 0x90, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "arpl", 2, 0x63, None, Cpu286|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16, Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "lar", 2, 0xf02, None, Cpu286, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "lgdt", 1, 0xf01, 0x2, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "lgdt", 1, 0xf01, 0x2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "lidt", 1, 0xf01, 0x3, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "lidt", 1, 0xf01, 0x3, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "lldt", 1, 0xf00, 0x2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "lmsw", 1, 0xf01, 0x6, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "lsl", 2, 0xf03, None, Cpu286, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "ltr", 1, 0xf00, 0x3, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sgdt", 1, 0xf01, 0x0, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sgdt", 1, 0xf01, 0x0, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sidt", 1, 0xf01, 0x1, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sidt", 1, 0xf01, 0x1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sldt", 1, 0xf00, 0x0, Cpu286, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64 } }, { "sldt", 1, 0xf00, 0x0, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "smsw", 1, 0xf01, 0x4, Cpu286, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64 } }, { "smsw", 1, 0xf01, 0x4, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "str", 1, 0xf00, 0x1, Cpu286, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64 } }, { "str", 1, 0xf00, 0x1, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "verr", 1, 0xf00, 0x4, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "verw", 1, 0xf00, 0x5, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fld", 1, 0xd9c0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } }, { "fld", 1, 0xd9, 0x0, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fld", 1, 0xd9c0, None, 0, ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg } }, { "fld", 1, 0xdb, 0x5, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fild", 1, 0xdf, 0x0, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fild", 1, 0xdf, 0x5, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fildll", 1, 0xdf, 0x5, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fldt", 1, 0xdb, 0x5, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fbld", 1, 0xdf, 0x4, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fst", 1, 0xddd0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } }, { "fst", 1, 0xd9, 0x2, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fst", 1, 0xddd0, None, 0, ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg } }, { "fist", 1, 0xdf, 0x2, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fstp", 1, 0xddd8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } }, { "fstp", 1, 0xd9, 0x3, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fstp", 1, 0xddd8, None, 0, ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg } }, { "fstp", 1, 0xdb, 0x7, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fistp", 1, 0xdf, 0x3, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fistp", 1, 0xdf, 0x7, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fistpll", 1, 0xdf, 0x7, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fstpt", 1, 0xdb, 0x7, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fbstp", 1, 0xdf, 0x6, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fxch", 1, 0xd9c8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } }, { "fxch", 0, 0xd9c9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fcom", 1, 0xd8d0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } }, { "fcom", 0, 0xd8d1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fcom", 1, 0xd8, 0x2, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fcom", 1, 0xd8d0, None, 0, ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg } }, { "ficom", 1, 0xde, 0x2, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fcomp", 1, 0xd8d8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } }, { "fcomp", 0, 0xd8d9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fcomp", 1, 0xd8, 0x3, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fcomp", 1, 0xd8d8, None, 0, ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg } }, { "ficomp", 1, 0xde, 0x3, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fcompp", 0, 0xded9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fucom", 1, 0xdde0, None, Cpu286, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } }, { "fucom", 0, 0xdde1, None, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fucomp", 1, 0xdde8, None, Cpu286, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } }, { "fucomp", 0, 0xdde9, None, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fucompp", 0, 0xdae9, None, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "ftst", 0, 0xd9e4, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fxam", 0, 0xd9e5, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fld1", 0, 0xd9e8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fldl2t", 0, 0xd9e9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fldl2e", 0, 0xd9ea, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fldpi", 0, 0xd9eb, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fldlg2", 0, 0xd9ec, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fldln2", 0, 0xd9ed, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fldz", 0, 0xd9ee, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fadd", 2, 0xd8c0, None, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } }, { "fadd", 1, 0xd8c0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } }, #if SYSV386_COMPAT { "fadd", 0, 0xdec1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { 0 } }, #endif { "fadd", 1, 0xd8, 0x0, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fiadd", 1, 0xde, 0x0, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "faddp", 2, 0xdec0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatAcc, FloatReg } }, { "faddp", 1, 0xdec0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } }, { "faddp", 0, 0xdec1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "faddp", 2, 0xdec0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg, FloatAcc } }, { "fsub", 1, 0xd8e0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } }, #if SYSV386_COMPAT { "fsub", 2, 0xd8e0, None, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } }, { "fsub", 0, 0xdee1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { 0 } }, #else { "fsub", 2, 0xd8e0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc } }, #endif { "fsub", 1, 0xd8, 0x4, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fisub", 1, 0xde, 0x4, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, #if SYSV386_COMPAT { "fsubp", 2, 0xdee0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatAcc, FloatReg } }, { "fsubp", 1, 0xdee0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } }, { "fsubp", 0, 0xdee1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, #if OLDGCC_COMPAT { "fsubp", 2, 0xdee0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg, FloatAcc } }, #endif #else { "fsubp", 2, 0xdee8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, { FloatAcc, FloatReg } }, { "fsubp", 1, 0xdee8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, { FloatReg } }, { "fsubp", 0, 0xdee9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf, { 0 } }, #endif { "fsubr", 1, 0xd8e8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } }, #if SYSV386_COMPAT { "fsubr", 2, 0xd8e8, None, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } }, { "fsubr", 0, 0xdee9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { 0 } }, #else { "fsubr", 2, 0xd8e8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc } }, #endif { "fsubr", 1, 0xd8, 0x5, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fisubr", 1, 0xde, 0x5, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, #if SYSV386_COMPAT { "fsubrp", 2, 0xdee8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatAcc, FloatReg } }, { "fsubrp", 1, 0xdee8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } }, { "fsubrp", 0, 0xdee9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, #if OLDGCC_COMPAT { "fsubrp", 2, 0xdee8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg, FloatAcc } }, #endif #else { "fsubrp", 2, 0xdee0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, { FloatAcc, FloatReg } }, { "fsubrp", 1, 0xdee0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, { FloatReg } }, { "fsubrp", 0, 0xdee1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf, { 0 } }, #endif { "fmul", 2, 0xd8c8, None, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } }, { "fmul", 1, 0xd8c8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } }, #if SYSV386_COMPAT { "fmul", 0, 0xdec9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { 0 } }, #endif { "fmul", 1, 0xd8, 0x1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fimul", 1, 0xde, 0x1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fmulp", 2, 0xdec8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatAcc, FloatReg } }, { "fmulp", 1, 0xdec8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } }, { "fmulp", 0, 0xdec9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fmulp", 2, 0xdec8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg, FloatAcc } }, { "fdiv", 1, 0xd8f0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } }, #if SYSV386_COMPAT { "fdiv", 2, 0xd8f0, None, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } }, { "fdiv", 0, 0xdef1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { 0 } }, #else { "fdiv", 2, 0xd8f0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc } }, #endif { "fdiv", 1, 0xd8, 0x6, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fidiv", 1, 0xde, 0x6, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, #if SYSV386_COMPAT { "fdivp", 2, 0xdef0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatAcc, FloatReg } }, { "fdivp", 1, 0xdef0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } }, { "fdivp", 0, 0xdef1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, #if OLDGCC_COMPAT { "fdivp", 2, 0xdef0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg, FloatAcc } }, #endif #else { "fdivp", 2, 0xdef8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, { FloatAcc, FloatReg } }, { "fdivp", 1, 0xdef8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, { FloatReg } }, { "fdivp", 0, 0xdef9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf, { 0 } }, #endif { "fdivr", 1, 0xd8f8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } }, #if SYSV386_COMPAT { "fdivr", 2, 0xd8f8, None, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } }, { "fdivr", 0, 0xdef9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { 0 } }, #else { "fdivr", 2, 0xd8f8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc } }, #endif { "fdivr", 1, 0xd8, 0x7, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fidivr", 1, 0xde, 0x7, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, #if SYSV386_COMPAT { "fdivrp", 2, 0xdef8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatAcc, FloatReg } }, { "fdivrp", 1, 0xdef8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } }, { "fdivrp", 0, 0xdef9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, #if OLDGCC_COMPAT { "fdivrp", 2, 0xdef8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, { FloatReg, FloatAcc } }, #endif #else { "fdivrp", 2, 0xdef0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, { FloatAcc, FloatReg } }, { "fdivrp", 1, 0xdef0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, { FloatReg } }, { "fdivrp", 0, 0xdef1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf, { 0 } }, #endif { "f2xm1", 0, 0xd9f0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fyl2x", 0, 0xd9f1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fptan", 0, 0xd9f2, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fpatan", 0, 0xd9f3, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fxtract", 0, 0xd9f4, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fprem1", 0, 0xd9f5, None, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fdecstp", 0, 0xd9f6, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fincstp", 0, 0xd9f7, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fprem", 0, 0xd9f8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fyl2xp1", 0, 0xd9f9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fsqrt", 0, 0xd9fa, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fsincos", 0, 0xd9fb, None, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "frndint", 0, 0xd9fc, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fscale", 0, 0xd9fd, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fsin", 0, 0xd9fe, None, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fcos", 0, 0xd9ff, None, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fchs", 0, 0xd9e0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fabs", 0, 0xd9e1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fninit", 0, 0xdbe3, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "finit", 0, 0xdbe3, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait, { 0 } }, { "fldcw", 1, 0xd9, 0x5, 0, Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fnstcw", 1, 0xd9, 0x7, 0, Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fstcw", 1, 0xd9, 0x7, 0, Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fnstsw", 1, 0xdfe0, None, 0, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Acc } }, { "fnstsw", 1, 0xdd, 0x7, 0, Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fnstsw", 0, 0xdfe0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fstsw", 1, 0xdfe0, None, 0, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait, { Acc } }, { "fstsw", 1, 0xdd, 0x7, 0, Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fstsw", 0, 0xdfe0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait, { 0 } }, { "fnclex", 0, 0xdbe2, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fclex", 0, 0xdbe2, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait, { 0 } }, { "fnstenv", 1, 0xd9, 0x6, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fstenv", 1, 0xd9, 0x6, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf|FWait, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fldenv", 1, 0xd9, 0x4, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fnsave", 1, 0xdd, 0x6, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fsave", 1, 0xdd, 0x6, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf|FWait, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "frstor", 1, 0xdd, 0x4, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "ffree", 1, 0xddc0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } }, { "ffreep", 1, 0xdfc0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } }, { "fnop", 0, 0xd9d0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fwait", 0, 0x9b, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "addr16", 0, 0x67, None, Cpu386|CpuNo64, Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "addr32", 0, 0x67, None, Cpu386, Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "aword", 0, 0x67, None, Cpu386|CpuNo64, Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "adword", 0, 0x67, None, Cpu386, Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "data16", 0, 0x66, None, Cpu386, Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "data32", 0, 0x66, None, Cpu386|CpuNo64, Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "word", 0, 0x66, None, Cpu386, Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "dword", 0, 0x66, None, Cpu386|CpuNo64, Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "lock", 0, 0xf0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "wait", 0, 0x9b, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "cs", 0, 0x2e, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "ds", 0, 0x3e, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "es", 0, 0x26, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "fs", 0, 0x64, None, Cpu386, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "gs", 0, 0x65, None, Cpu386, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "ss", 0, 0x36, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "rep", 0, 0xf3, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "repe", 0, 0xf3, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "repz", 0, 0xf3, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "repne", 0, 0xf2, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "repnz", 0, 0xf2, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "ht", 0, 0x3e, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "hnt", 0, 0x2e, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "rex", 0, 0x40, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "rexz", 0, 0x41, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "rexy", 0, 0x42, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "rexyz", 0, 0x43, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "rexx", 0, 0x44, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "rexxz", 0, 0x45, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "rexxy", 0, 0x46, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "rexxyz", 0, 0x47, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "rex64", 0, 0x48, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "rex64z", 0, 0x49, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "rex64y", 0, 0x4a, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "rex64yz", 0, 0x4b, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "rex64x", 0, 0x4c, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "rex64xz", 0, 0x4d, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "rex64xy", 0, 0x4e, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "rex64xyz", 0, 0x4f, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "rex.b", 0, 0x41, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "rex.x", 0, 0x42, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "rex.xb", 0, 0x43, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "rex.r", 0, 0x44, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "rex.rb", 0, 0x45, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "rex.rx", 0, 0x46, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "rex.rxb", 0, 0x47, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "rex.w", 0, 0x48, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "rex.wb", 0, 0x49, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "rex.wx", 0, 0x4a, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "rex.wxb", 0, 0x4b, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "rex.wr", 0, 0x4c, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "rex.wrb", 0, 0x4d, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "rex.wrx", 0, 0x4e, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "rex.wrxb", 0, 0x4f, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, { 0 } }, { "bswap", 1, 0xfc8, None, Cpu486, ShortForm|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { Reg32|Reg64 } }, { "xadd", 2, 0xfc0, None, Cpu486, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "cmpxchg", 2, 0xfb0, None, Cpu486, W|Modrm|No_sSuf|No_xSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "invd", 0, 0xf08, None, Cpu486, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "wbinvd", 0, 0xf09, None, Cpu486, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "invlpg", 1, 0xf01, 0x7, Cpu486, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "cpuid", 0, 0xfa2, None, Cpu486, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "wrmsr", 0, 0xf30, None, Cpu586, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "rdtsc", 0, 0xf31, None, Cpu586, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "rdmsr", 0, 0xf32, None, Cpu586, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "cmpxchg8b", 1, 0xfc7, 0x1, Cpu586, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sysenter", 0, 0xf34, None, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "sysexit", 0, 0xf35, None, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fxsave", 1, 0xfae, 0x0, Cpu686, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fxrstor", 1, 0xfae, 0x1, Cpu686, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "rdpmc", 0, 0xf33, None, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "ud2", 0, 0xf0b, None, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "ud2a", 0, 0xf0b, None, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "ud2b", 0, 0xfb9, None, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "cmovo", 2, 0xf40, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovno", 2, 0xf41, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovb", 2, 0xf42, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovc", 2, 0xf42, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovnae", 2, 0xf42, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovae", 2, 0xf43, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovnc", 2, 0xf43, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovnb", 2, 0xf43, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmove", 2, 0xf44, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovz", 2, 0xf44, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovne", 2, 0xf45, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovnz", 2, 0xf45, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovbe", 2, 0xf46, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovna", 2, 0xf46, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmova", 2, 0xf47, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovnbe", 2, 0xf47, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovs", 2, 0xf48, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovns", 2, 0xf49, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovp", 2, 0xf4a, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovnp", 2, 0xf4b, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovl", 2, 0xf4c, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovnge", 2, 0xf4c, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovge", 2, 0xf4d, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovnl", 2, 0xf4d, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovle", 2, 0xf4e, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovng", 2, 0xf4e, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovg", 2, 0xf4f, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovnle", 2, 0xf4f, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "fcmovb", 2, 0xdac0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } }, { "fcmovnae", 2, 0xdac0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } }, { "fcmove", 2, 0xdac8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } }, { "fcmovbe", 2, 0xdad0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } }, { "fcmovna", 2, 0xdad0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } }, { "fcmovu", 2, 0xdad8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } }, { "fcmovae", 2, 0xdbc0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } }, { "fcmovnb", 2, 0xdbc0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } }, { "fcmovne", 2, 0xdbc8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } }, { "fcmova", 2, 0xdbd0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } }, { "fcmovnbe", 2, 0xdbd0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } }, { "fcmovnu", 2, 0xdbd8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } }, { "fcomi", 2, 0xdbf0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } }, { "fcomi", 0, 0xdbf1, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fcomi", 1, 0xdbf0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } }, { "fucomi", 2, 0xdbe8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } }, { "fucomi", 0, 0xdbe9, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fucomi", 1, 0xdbe8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } }, { "fcomip", 2, 0xdff0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } }, { "fcompi", 2, 0xdff0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } }, { "fcompi", 0, 0xdff1, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fcompi", 1, 0xdff0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } }, { "fucomip", 2, 0xdfe8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } }, { "fucompi", 2, 0xdfe8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg, FloatAcc } }, { "fucompi", 0, 0xdfe9, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "fucompi", 1, 0xdfe8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { FloatReg } }, { "movnti", 2, 0xfc3, None, CpuP4, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64, BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "clflush", 1, 0xfae, 0x7, CpuP4, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "lfence", 0, 0xfae, 0xe8, CpuP4, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } }, { "mfence", 0, 0xfae, 0xf0, CpuP4, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } }, { "pause", 0, 0xf390, None, CpuP4, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "emms", 0, 0xf77, None, CpuMMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "movd", 2, 0xf6e, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegMMX } }, { "movd", 2, 0xf7e, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegMMX, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "movd", 2, 0x660f6e, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } }, { "movd", 2, 0x660f7e, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "movq", 2, 0xf6f, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "movq", 2, 0xf7f, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { RegMMX, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX } }, { "movq", 2, 0xf30f7e, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "movq", 2, 0x660fd6, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } }, { "movq", 2, 0xf6e, None, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegMMX } }, { "movq", 2, 0xf7e, None, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegMMX, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "movq", 2, 0x660f6e, None, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } }, { "movq", 2, 0x660f7e, None, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "movq", 2, 0xa0, None, Cpu64, D|W|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Disp64, Acc } }, { "movq", 2, 0x88, None, Cpu64, D|W|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg64, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "movq", 2, 0xc6, 0x0, Cpu64, W|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm32S, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "movq", 2, 0xb0, None, Cpu64, W|ShortForm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm64, Reg64 } }, { "movq", 2, 0x8c, None, Cpu64, Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { SReg2|SReg3, Reg64|RegMem } }, { "movq", 2, 0x8e, None, Cpu64, Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg64, SReg2|SReg3 } }, { "movq", 2, 0xf20, None, Cpu64, D|Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { Control, Reg64|RegMem } }, { "movq", 2, 0xf21, None, Cpu64, D|Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { Debug, Reg64|RegMem } }, { "packssdw", 2, 0xf6b, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "packssdw", 2, 0x660f6b, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "packsswb", 2, 0xf63, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "packsswb", 2, 0x660f63, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "packuswb", 2, 0xf67, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "packuswb", 2, 0x660f67, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "paddb", 2, 0xffc, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "paddb", 2, 0x660ffc, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "paddw", 2, 0xffd, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "paddw", 2, 0x660ffd, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "paddd", 2, 0xffe, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "paddd", 2, 0x660ffe, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "paddq", 2, 0xfd4, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "paddq", 2, 0x660fd4, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "paddsb", 2, 0xfec, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "paddsb", 2, 0x660fec, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "paddsw", 2, 0xfed, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "paddsw", 2, 0x660fed, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "paddusb", 2, 0xfdc, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "paddusb", 2, 0x660fdc, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "paddusw", 2, 0xfdd, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "paddusw", 2, 0x660fdd, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pand", 2, 0xfdb, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pand", 2, 0x660fdb, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pandn", 2, 0xfdf, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pandn", 2, 0x660fdf, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pcmpeqb", 2, 0xf74, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pcmpeqb", 2, 0x660f74, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pcmpeqw", 2, 0xf75, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pcmpeqw", 2, 0x660f75, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pcmpeqd", 2, 0xf76, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pcmpeqd", 2, 0x660f76, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pcmpgtb", 2, 0xf64, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pcmpgtb", 2, 0x660f64, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pcmpgtw", 2, 0xf65, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pcmpgtw", 2, 0x660f65, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pcmpgtd", 2, 0xf66, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pcmpgtd", 2, 0x660f66, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmaddwd", 2, 0xff5, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pmaddwd", 2, 0x660ff5, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmulhw", 2, 0xfe5, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pmulhw", 2, 0x660fe5, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmullw", 2, 0xfd5, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pmullw", 2, 0x660fd5, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "por", 2, 0xfeb, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "por", 2, 0x660feb, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psllw", 2, 0xff1, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psllw", 2, 0x660ff1, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psllw", 2, 0xf71, 0x6, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegMMX } }, { "psllw", 2, 0x660f71, 0x6, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM } }, { "pslld", 2, 0xff2, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pslld", 2, 0x660ff2, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pslld", 2, 0xf72, 0x6, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegMMX } }, { "pslld", 2, 0x660f72, 0x6, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM } }, { "psllq", 2, 0xff3, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psllq", 2, 0x660ff3, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psllq", 2, 0xf73, 0x6, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegMMX } }, { "psllq", 2, 0x660f73, 0x6, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM } }, { "psraw", 2, 0xfe1, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psraw", 2, 0x660fe1, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psraw", 2, 0xf71, 0x4, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegMMX } }, { "psraw", 2, 0x660f71, 0x4, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM } }, { "psrad", 2, 0xfe2, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psrad", 2, 0x660fe2, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psrad", 2, 0xf72, 0x4, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegMMX } }, { "psrad", 2, 0x660f72, 0x4, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM } }, { "psrlw", 2, 0xfd1, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psrlw", 2, 0x660fd1, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psrlw", 2, 0xf71, 0x2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegMMX } }, { "psrlw", 2, 0x660f71, 0x2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM } }, { "psrld", 2, 0xfd2, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psrld", 2, 0x660fd2, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psrld", 2, 0xf72, 0x2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegMMX } }, { "psrld", 2, 0x660f72, 0x2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM } }, { "psrlq", 2, 0xfd3, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psrlq", 2, 0x660fd3, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psrlq", 2, 0xf73, 0x2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegMMX } }, { "psrlq", 2, 0x660f73, 0x2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM } }, { "psubb", 2, 0xff8, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psubb", 2, 0x660ff8, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psubw", 2, 0xff9, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psubw", 2, 0x660ff9, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psubd", 2, 0xffa, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psubd", 2, 0x660ffa, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psubq", 2, 0xffb, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psubq", 2, 0x660ffb, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psubsb", 2, 0xfe8, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psubsb", 2, 0x660fe8, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psubsw", 2, 0xfe9, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psubsw", 2, 0x660fe9, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psubusb", 2, 0xfd8, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psubusb", 2, 0x660fd8, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psubusw", 2, 0xfd9, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psubusw", 2, 0x660fd9, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "punpckhbw", 2, 0xf68, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "punpckhbw", 2, 0x660f68, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "punpckhwd", 2, 0xf69, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "punpckhwd", 2, 0x660f69, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "punpckhdq", 2, 0xf6a, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "punpckhdq", 2, 0x660f6a, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "punpcklbw", 2, 0xf60, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "punpcklbw", 2, 0x660f60, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "punpcklwd", 2, 0xf61, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "punpcklwd", 2, 0x660f61, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "punpckldq", 2, 0xf62, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "punpckldq", 2, 0x660f62, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pxor", 2, 0xfef, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pxor", 2, 0x660fef, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "addps", 2, 0xf58, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "addss", 2, 0xf30f58, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "andnps", 2, 0xf55, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "andps", 2, 0xf54, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpeqps", 2, 0xfc2, 0x0, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpeqss", 2, 0xf30fc2, 0x0, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpleps", 2, 0xfc2, 0x2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpless", 2, 0xf30fc2, 0x2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpltps", 2, 0xfc2, 0x1, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpltss", 2, 0xf30fc2, 0x1, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpneqps", 2, 0xfc2, 0x4, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpneqss", 2, 0xf30fc2, 0x4, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpnleps", 2, 0xfc2, 0x6, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpnless", 2, 0xf30fc2, 0x6, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpnltps", 2, 0xfc2, 0x5, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpnltss", 2, 0xf30fc2, 0x5, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpordps", 2, 0xfc2, 0x7, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpordss", 2, 0xf30fc2, 0x7, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpunordps", 2, 0xfc2, 0x3, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpunordss", 2, 0xf30fc2, 0x3, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpps", 3, 0xfc2, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpss", 3, 0xf30fc2, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "comiss", 2, 0xf2f, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cvtpi2ps", 2, 0xf2a, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegXMM } }, { "cvtps2pi", 2, 0xf2d, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegMMX } }, { "cvtsi2ss", 2, 0xf30f2a, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } }, { "cvtss2si", 2, 0xf30f2d, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } }, { "cvttps2pi", 2, 0xf2c, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegMMX } }, { "cvttss2si", 2, 0xf30f2c, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } }, { "divps", 2, 0xf5e, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "divss", 2, 0xf30f5e, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "ldmxcsr", 1, 0xfae, 0x2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "maskmovq", 2, 0xff7, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegMMX, RegMMX } }, { "maxps", 2, 0xf5f, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "maxss", 2, 0xf30f5f, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "minps", 2, 0xf5d, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "minss", 2, 0xf30f5d, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "movaps", 2, 0xf28, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "movaps", 2, 0xf29, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } }, { "movhlps", 2, 0xf12, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, RegXMM } }, { "movhps", 2, 0xf16, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } }, { "movhps", 2, 0xf17, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "movlhps", 2, 0xf16, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, RegXMM } }, { "movlps", 2, 0xf12, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } }, { "movlps", 2, 0xf13, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "movmskps", 2, 0xf50, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { RegXMM, Reg32|Reg64 } }, { "movntps", 2, 0xf2b, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "movntq", 2, 0xfe7, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegMMX, BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "movntdq", 2, 0x660fe7, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "movss", 2, 0xf30f10, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "movss", 2, 0xf30f11, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } }, { "movups", 2, 0xf10, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "movups", 2, 0xf11, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } }, { "mulps", 2, 0xf59, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "mulss", 2, 0xf30f59, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "orps", 2, 0xf56, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pavgb", 2, 0xfe0, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pavgb", 2, 0x660fe0, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pavgw", 2, 0xfe3, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pavgw", 2, 0x660fe3, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pextrw", 3, 0xfc5, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { Imm8, RegMMX, Reg32|Reg64 } }, { "pextrw", 3, 0x660fc5, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { Imm8, RegXMM, Reg32|Reg64 } }, { "pextrw", 3, 0x660f3a15, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "pinsrw", 3, 0xfc4, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { Imm8, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegMMX } }, { "pinsrw", 3, 0x660fc4, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { Imm8, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } }, { "pmaxsw", 2, 0xfee, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pmaxsw", 2, 0x660fee, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmaxub", 2, 0xfde, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pmaxub", 2, 0x660fde, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pminsw", 2, 0xfea, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pminsw", 2, 0x660fea, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pminub", 2, 0xfda, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pminub", 2, 0x660fda, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovmskb", 2, 0xfd7, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { RegMMX, Reg32|Reg64 } }, { "pmovmskb", 2, 0x660fd7, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { RegXMM, Reg32|Reg64 } }, { "pmulhuw", 2, 0xfe4, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pmulhuw", 2, 0x660fe4, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "prefetchnta", 1, 0xf18, 0x0, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "prefetcht0", 1, 0xf18, 0x1, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "prefetcht1", 1, 0xf18, 0x2, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "prefetcht2", 1, 0xf18, 0x3, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "psadbw", 2, 0xff6, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psadbw", 2, 0x660ff6, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pshufw", 3, 0xf70, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "rcpps", 2, 0xf53, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "rcpss", 2, 0xf30f53, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "rsqrtps", 2, 0xf52, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "rsqrtss", 2, 0xf30f52, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "sfence", 0, 0xfae, 0xf8, CpuMMX2, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } }, { "shufps", 3, 0xfc6, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "sqrtps", 2, 0xf51, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "sqrtss", 2, 0xf30f51, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "stmxcsr", 1, 0xfae, 0x3, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "subps", 2, 0xf5c, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "subss", 2, 0xf30f5c, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "ucomiss", 2, 0xf2e, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "unpckhps", 2, 0xf15, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "unpcklps", 2, 0xf14, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "xorps", 2, 0xf57, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "addpd", 2, 0x660f58, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "addsd", 2, 0xf20f58, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "andnpd", 2, 0x660f55, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "andpd", 2, 0x660f54, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpeqpd", 2, 0x660fc2, 0x0, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpeqsd", 2, 0xf20fc2, 0x0, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmplepd", 2, 0x660fc2, 0x2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmplesd", 2, 0xf20fc2, 0x2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpltpd", 2, 0x660fc2, 0x1, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpltsd", 2, 0xf20fc2, 0x1, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpneqpd", 2, 0x660fc2, 0x4, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpneqsd", 2, 0xf20fc2, 0x4, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpnlepd", 2, 0x660fc2, 0x6, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpnlesd", 2, 0xf20fc2, 0x6, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpnltpd", 2, 0x660fc2, 0x5, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpnltsd", 2, 0xf20fc2, 0x5, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpordpd", 2, 0x660fc2, 0x7, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpordsd", 2, 0xf20fc2, 0x7, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpunordpd", 2, 0x660fc2, 0x3, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpunordsd", 2, 0xf20fc2, 0x3, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmppd", 3, 0x660fc2, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpsd", 0, 0xa7, None, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString, { 0 } }, { "cmpsd", 2, 0xa7, None, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, { "cmpsd", 3, 0xf20fc2, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "comisd", 2, 0x660f2f, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cvtpi2pd", 2, 0x660f2a, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegXMM } }, { "cvtsi2sd", 2, 0xf20f2a, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } }, { "divpd", 2, 0x660f5e, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "divsd", 2, 0xf20f5e, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "maxpd", 2, 0x660f5f, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "maxsd", 2, 0xf20f5f, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "minpd", 2, 0x660f5d, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "minsd", 2, 0xf20f5d, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "movapd", 2, 0x660f28, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "movapd", 2, 0x660f29, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } }, { "movhpd", 2, 0x660f16, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } }, { "movhpd", 2, 0x660f17, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "movlpd", 2, 0x660f12, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } }, { "movlpd", 2, 0x660f13, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "movmskpd", 2, 0x660f50, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { RegXMM, Reg32|Reg64 } }, { "movntpd", 2, 0x660f2b, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "movsd", 0, 0xa5, None, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString, { 0 } }, { "movsd", 2, 0xa5, None, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, { "movsd", 2, 0xf20f10, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "movsd", 2, 0xf20f11, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } }, { "movupd", 2, 0x660f10, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "movupd", 2, 0x660f11, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } }, { "mulpd", 2, 0x660f59, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "mulsd", 2, 0xf20f59, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "orpd", 2, 0x660f56, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "shufpd", 3, 0x660fc6, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "sqrtpd", 2, 0x660f51, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "sqrtsd", 2, 0xf20f51, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "subpd", 2, 0x660f5c, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "subsd", 2, 0xf20f5c, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "ucomisd", 2, 0x660f2e, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "unpckhpd", 2, 0x660f15, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "unpcklpd", 2, 0x660f14, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "xorpd", 2, 0x660f57, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cvtdq2pd", 2, 0xf30fe6, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cvtpd2dq", 2, 0xf20fe6, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cvtdq2ps", 2, 0xf5b, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cvtpd2pi", 2, 0x660f2d, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegMMX } }, { "cvtpd2ps", 2, 0x660f5a, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cvtps2pd", 2, 0xf5a, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cvtps2dq", 2, 0x660f5b, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cvtsd2si", 2, 0xf20f2d, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } }, { "cvtsd2ss", 2, 0xf20f5a, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cvtss2sd", 2, 0xf30f5a, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cvttpd2pi", 2, 0x660f2c, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegMMX } }, { "cvttsd2si", 2, 0xf20f2c, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } }, { "cvttpd2dq", 2, 0x660fe6, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cvttps2dq", 2, 0xf30f5b, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "maskmovdqu", 2, 0x660ff7, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, RegXMM } }, { "movdqa", 2, 0x660f6f, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "movdqa", 2, 0x660f7f, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } }, { "movdqu", 2, 0xf30f6f, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "movdqu", 2, 0xf30f7f, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } }, { "movdq2q", 2, 0xf20fd6, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, RegMMX } }, { "movq2dq", 2, 0xf30fd6, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegMMX, RegXMM } }, { "pmuludq", 2, 0xff4, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pmuludq", 2, 0x660ff4, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pshufd", 3, 0x660f70, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pshufhw", 3, 0xf30f70, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pshuflw", 3, 0xf20f70, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pslldq", 2, 0x660f73, 0x7, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM } }, { "psrldq", 2, 0x660f73, 0x3, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM } }, { "punpckhqdq", 2, 0x660f6d, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "punpcklqdq", 2, 0x660f6c, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "addsubpd", 2, 0x660fd0, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "addsubps", 2, 0xf20fd0, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpxchg16b", 1, 0xfc7, 0x1, CpuSSE3|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fisttp", 1, 0xdf, 0x1, CpuSSE3, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fisttp", 1, 0xdd, 0x1, CpuSSE3, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fisttpll", 1, 0xdd, 0x1, CpuSSE3, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "haddpd", 2, 0x660f7c, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "haddps", 2, 0xf20f7c, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "hsubpd", 2, 0x660f7d, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "hsubps", 2, 0xf20f7d, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "lddqu", 2, 0xf20ff0, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } }, { "monitor", 0, 0xf01, 0xc8, CpuSSE3, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } }, { "monitor", 3, 0xf01, 0xc8, CpuSSE3|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { Reg16|Reg32, Reg32, Reg32 } }, { "monitor", 3, 0xf01, 0xc8, CpuSSE3|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64, { Reg32|Reg64, Reg64, Reg64 } }, { "movddup", 2, 0xf20f12, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "movshdup", 2, 0xf30f16, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "movsldup", 2, 0xf30f12, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "mwait", 0, 0xf01, 0xc9, CpuSSE3, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } }, { "mwait", 2, 0xf01, 0xc9, CpuSSE3|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { Reg32, Reg32 } }, { "mwait", 2, 0xf01, 0xc9, CpuSSE3|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64, { Reg64, Reg64 } }, { "vmcall", 0, 0xf01, 0xc1, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } }, { "vmclear", 1, 0x660fc7, 0x6, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "vmlaunch", 0, 0xf01, 0xc2, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } }, { "vmresume", 0, 0xf01, 0xc3, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } }, { "vmptrld", 1, 0xfc7, 0x6, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "vmptrst", 1, 0xfc7, 0x7, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "vmread", 2, 0xf78, None, CpuVMX|CpuNo64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf, { Reg32, Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "vmread", 2, 0xf78, None, CpuVMX|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Reg64, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "vmwrite", 2, 0xf79, None, CpuVMX|CpuNo64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf, { Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } }, { "vmwrite", 2, 0xf79, None, CpuVMX|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } }, { "vmxoff", 0, 0xf01, 0xc4, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } }, { "vmxon", 1, 0xf30fc7, 0x6, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "phaddw", 2, 0xf3801, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "phaddw", 2, 0x660f3801, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "phaddd", 2, 0xf3802, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "phaddd", 2, 0x660f3802, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "phaddsw", 2, 0xf3803, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "phaddsw", 2, 0x660f3803, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "phsubw", 2, 0xf3805, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "phsubw", 2, 0x660f3805, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "phsubd", 2, 0xf3806, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "phsubd", 2, 0x660f3806, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "phsubsw", 2, 0xf3807, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "phsubsw", 2, 0x660f3807, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmaddubsw", 2, 0xf3804, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pmaddubsw", 2, 0x660f3804, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmulhrsw", 2, 0xf380b, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pmulhrsw", 2, 0x660f380b, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pshufb", 2, 0xf3800, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pshufb", 2, 0x660f3800, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psignb", 2, 0xf3808, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psignb", 2, 0x660f3808, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psignw", 2, 0xf3809, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psignw", 2, 0x660f3809, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psignd", 2, 0xf380a, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psignd", 2, 0x660f380a, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "palignr", 3, 0xf3a0f, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "palignr", 3, 0x660f3a0f, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pabsb", 2, 0xf381c, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pabsb", 2, 0x660f381c, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pabsw", 2, 0xf381d, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pabsw", 2, 0x660f381d, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pabsd", 2, 0xf381e, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pabsd", 2, 0x660f381e, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "blendpd", 3, 0x660f3a0d, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "blendps", 3, 0x660f3a0c, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "blendvpd", 3, 0x660f3815, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|RegKludge, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "blendvps", 3, 0x660f3814, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|RegKludge, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "dppd", 3, 0x660f3a41, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "dpps", 3, 0x660f3a40, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "extractps", 3, 0x660f3a17, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "insertps", 3, 0x660f3a21, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "movntdqa", 2, 0x660f382a, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } }, { "mpsadbw", 3, 0x660f3a42, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "packusdw", 2, 0x660f382b, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pblendvb", 3, 0x660f3810, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|RegKludge, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pblendw", 3, 0x660f3a0e, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pcmpeqq", 2, 0x660f3829, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pextrb", 3, 0x660f3a14, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "pextrd", 3, 0x660f3a16, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM, Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "pextrq", 3, 0x660f3a16, None, CpuSSE4_1|Cpu64, Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "phminposuw", 2, 0x660f3841, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pinsrb", 3, 0x660f3a20, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } }, { "pinsrd", 3, 0x660f3a22, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } }, { "pinsrq", 3, 0x660f3a22, None, CpuSSE4_1|Cpu64, Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } }, { "pmaxsb", 2, 0x660f383c, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmaxsd", 2, 0x660f383d, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmaxud", 2, 0x660f383f, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmaxuw", 2, 0x660f383e, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pminsb", 2, 0x660f3838, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pminsd", 2, 0x660f3839, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pminud", 2, 0x660f383b, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pminuw", 2, 0x660f383a, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovsxbw", 2, 0x660f3820, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovsxbd", 2, 0x660f3821, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovsxbq", 2, 0x660f3822, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovsxwd", 2, 0x660f3823, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovsxwq", 2, 0x660f3824, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovsxdq", 2, 0x660f3825, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovzxbw", 2, 0x660f3830, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovzxbd", 2, 0x660f3831, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovzxbq", 2, 0x660f3832, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovzxwd", 2, 0x660f3833, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovzxwq", 2, 0x660f3834, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovzxdq", 2, 0x660f3835, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmuldq", 2, 0x660f3828, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmulld", 2, 0x660f3840, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, ! { "ptest", 2, 0x660f3817, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, ! { "roundpd", 3, 0x660f3a09, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, ! { "roundps", 3, 0x660f3a08, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, ! { "roundsd", 3, 0x660f3a0b, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, ! { "roundss", 3, 0x660f3a0a, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pcmpgtq", 2, 0x660f3837, None, CpuSSE4_2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pcmpestri", 3, 0x660f3a61, None, CpuSSE4_2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pcmpestrm", 3, 0x660f3a60, None, CpuSSE4_2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pcmpistri", 3, 0x660f3a63, None, CpuSSE4_2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pcmpistrm", 3, 0x660f3a62, None, CpuSSE4_2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "crc32", 2, 0xf20f38f1, None, CpuSSE4_2, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } }, { "crc32", 2, 0xf20f38f1, None, CpuSSE4_2|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|Rex64, { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } }, { "crc32", 2, 0xf20f38f0, None, CpuSSE4_2, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } }, { "crc32", 2, 0xf20f38f0, None, CpuSSE4_2|Cpu64, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } }, { "prefetch", 1, 0xf0d, 0x0, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "prefetchw", 1, 0xf0d, 0x1, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "femms", 0, 0xf0e, None, Cpu3dnow, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "pavgusb", 2, 0xf0f, 0xbf, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pf2id", 2, 0xf0f, 0x1d, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pf2iw", 2, 0xf0f, 0x1c, Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfacc", 2, 0xf0f, 0xae, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfadd", 2, 0xf0f, 0x9e, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfcmpeq", 2, 0xf0f, 0xb0, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfcmpge", 2, 0xf0f, 0x90, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfcmpgt", 2, 0xf0f, 0xa0, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfmax", 2, 0xf0f, 0xa4, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfmin", 2, 0xf0f, 0x94, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfmul", 2, 0xf0f, 0xb4, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfnacc", 2, 0xf0f, 0x8a, Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfpnacc", 2, 0xf0f, 0x8e, Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfrcp", 2, 0xf0f, 0x96, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfrcpit1", 2, 0xf0f, 0xa6, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfrcpit2", 2, 0xf0f, 0xb6, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfrsqit1", 2, 0xf0f, 0xa7, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfrsqrt", 2, 0xf0f, 0x97, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfsub", 2, 0xf0f, 0x9a, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfsubr", 2, 0xf0f, 0xaa, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pi2fd", 2, 0xf0f, 0xd, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pi2fw", 2, 0xf0f, 0xc, Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pmulhrw", 2, 0xf0f, 0xb7, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pswapd", 2, 0xf0f, 0xbb, Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "syscall", 0, 0xf05, None, CpuK6, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { 0 } }, { "sysret", 0, 0xf07, None, CpuK6, DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, { 0 } }, { "swapgs", 0, 0xf01, 0xf8, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } }, { "rdtscp", 0, 0xf01, 0xf9, CpuSledgehammer, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } }, { "clgi", 0, 0xf01, 0xdd, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } }, { "invlpga", 0, 0xf01, 0xdf, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } }, { "invlpga", 2, 0xf01, 0xdf, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } }, { "skinit", 0, 0xf01, 0xde, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } }, { "skinit", 1, 0xf01, 0xde, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "stgi", 0, 0xf01, 0xdc, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } }, { "vmload", 0, 0xf01, 0xda, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } }, { "vmload", 1, 0xf01, 0xda, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "vmmcall", 0, 0xf01, 0xd9, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } }, { "vmrun", 0, 0xf01, 0xd8, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } }, { "vmrun", 1, 0xf01, 0xd8, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "vmsave", 0, 0xf01, 0xdb, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } }, { "vmsave", 1, 0xf01, 0xdb, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "movntsd", 2, 0xf20f2b, None, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "movntss", 2, 0xf30f2b, None, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "extrq", 3, 0x660f78, 0x0, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, Imm8, RegXMM } }, { "extrq", 2, 0x660f79, None, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, RegXMM } }, { "insertq", 2, 0xf20f79, None, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, RegXMM } }, { "insertq", 4, 0xf20f78, None, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, Imm8, RegXMM, RegXMM } }, { "popcnt", 2, 0xf30fb8, None, CpuABM|CpuSSE4_2, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "lzcnt", 2, 0xf30fbd, None, CpuABM, Modrm|No_bSuf|No_sSuf|No_xSuf, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "xstore-rng", 0, 0xfa7, 0xc0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } }, { "xcrypt-ecb", 0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } }, { "xcrypt-cbc", 0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } }, { "xcrypt-ctr", 0, 0xf30fa7, 0xd8, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } }, { "xcrypt-cfb", 0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } }, { "xcrypt-ofb", 0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } }, { "montmul", 0, 0xf30fa6, 0xc0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } }, { "xsha1", 0, 0xf30fa6, 0xc8, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } }, { "xsha256", 0, 0xf30fa6, 0xd0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } }, { "xstorerng", 0, 0xfa7, 0xc0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } }, { "xcryptecb", 0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } }, { "xcryptcbc", 0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } }, { "xcryptctr", 0, 0xf30fa7, 0xd8, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } }, { "xcryptcfb", 0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } }, { "xcryptofb", 0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } }, { "xstore", 0, 0xfa7, 0xc0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } }, ! { NULL, 0, 0, 0, 0, 0, { 0 } } }; /* i386 register table. */ --- 24,7049 ---- { { "mov", 2, 0xa0, None, Cpu64, D|W|No_sSuf|No_xSuf, + 0, { Disp64, Acc } }, { "mov", 2, 0xa0, None, CpuNo64, D|W|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp16|Disp32, Acc } }, { "mov", 2, 0x88, None, 0, D|W|Modrm|No_sSuf|No_xSuf, + 0, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "mov", 2, 0xb0, None, 0, W|ShortForm|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32 } }, { "mov", 2, 0xc6, 0x0, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "mov", 2, 0xb0, None, Cpu64, W|ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, + 0, { Imm64, Reg64 } }, { "mov", 2, 0x8c, None, 0, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { SReg2, Reg16|Reg32|Reg64|RegMem } }, { "mov", 2, 0x8c, None, 0, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { SReg2, BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "mov", 2, 0x8c, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { SReg3, Reg16|Reg32|Reg64|RegMem } }, { "mov", 2, 0x8c, None, Cpu386, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { SReg3, BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "mov", 2, 0x8e, None, 0, Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64, SReg2 } }, { "mov", 2, 0x8e, None, 0, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, SReg2 } }, { "mov", 2, 0x8e, None, Cpu386, Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64, SReg3 } }, { "mov", 2, 0x8e, None, Cpu386, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, SReg3 } }, { "mov", 2, 0xf20, None, Cpu386|CpuNo64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Control, Reg32|RegMem } }, { "mov", 2, 0xf20, None, Cpu64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + 0, { Control, Reg64|RegMem } }, { "mov", 2, 0xf21, None, Cpu386|CpuNo64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Debug, Reg32|RegMem } }, { "mov", 2, 0xf21, None, Cpu64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + 0, { Debug, Reg64|RegMem } }, { "mov", 2, 0xf24, None, Cpu386|CpuNo64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Test, Reg32|RegMem } }, { "movabs", 2, 0xa0, None, Cpu64, D|W|No_sSuf|No_xSuf, + 0, { Disp64, Acc } }, { "movabs", 2, 0xb0, None, Cpu64, W|ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, + 0, { Imm64, Reg64 } }, { "movsbl", 2, 0xfbe, None, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } }, { "movsbw", 2, 0xfbe, None, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16 } }, { "movswl", 2, 0xfbf, None, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } }, { "movsbq", 2, 0xfbe, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } }, { "movswq", 2, 0xfbf, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, + 0, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } }, { "movslq", 2, 0x63, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, + 0, { Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } }, { "movsx", 2, 0xfbe, None, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "movsx", 2, 0xfbf, None, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 } }, { "movsx", 2, 0x63, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, + 0, { Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } }, { "movzb", 2, 0xfb6, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "movzbl", 2, 0xfb6, None, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } }, { "movzbw", 2, 0xfb6, None, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16 } }, { "movzwl", 2, 0xfb7, None, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } }, { "movzbq", 2, 0xfb6, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } }, { "movzwq", 2, 0xfb7, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, + 0, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } }, { "movzx", 2, 0xfb6, None, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "movzx", 2, 0xfb7, None, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 } }, { "push", 1, 0x50, None, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64 } }, { "push", 1, 0xff, 0x6, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "push", 1, 0x6a, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8S } }, { "push", 1, 0x68, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm16|Imm32 } }, { "push", 1, 0x6, None, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { SReg2 } }, { "push", 1, 0xfa0, None, Cpu386|CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { SReg3 } }, { "push", 1, 0x50, None, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + 0, { Reg16|Reg64 } }, { "push", 1, 0xff, 0x6, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + 0, { Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "push", 1, 0x6a, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + 0, { Imm8S } }, { "push", 1, 0x68, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + 0, { Imm16|Imm32S } }, { "push", 1, 0xfa0, None, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + 0, { SReg3 } }, { "pusha", 0, 0x60, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "pop", 1, 0x58, None, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64 } }, { "pop", 1, 0x8f, 0x0, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "pop", 1, 0x7, None, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { SReg2 } }, { "pop", 1, 0xfa1, None, Cpu386|CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { SReg3 } }, { "pop", 1, 0x58, None, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + 0, { Reg16|Reg64 } }, { "pop", 1, 0x8f, 0x0, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + 0, { Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "pop", 1, 0xfa1, None, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + 0, { SReg3 } }, { "popa", 0, 0x61, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "xchg", 2, 0x90, None, 0, ShortForm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64, Acc } }, { "xchg", 2, 0x90, None, 0, ShortForm|No_bSuf|No_sSuf|No_xSuf, + 0, { Acc, Reg16|Reg32|Reg64 } }, { "xchg", 2, 0x86, None, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "xchg", 2, 0x86, None, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg8|Reg16|Reg32|Reg64 } }, { "in", 2, 0xe4, None, 0, W|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, Acc } }, { "in", 2, 0xec, None, 0, W|No_sSuf|No_qSuf|No_xSuf, + 0, { InOutPortReg, Acc } }, { "in", 1, 0xe4, None, 0, W|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8 } }, { "in", 1, 0xec, None, 0, W|No_sSuf|No_qSuf|No_xSuf, + 0, { InOutPortReg } }, { "out", 2, 0xe6, None, 0, W|No_sSuf|No_qSuf|No_xSuf, + 0, { Acc, Imm8 } }, { "out", 2, 0xee, None, 0, W|No_sSuf|No_qSuf|No_xSuf, + 0, { Acc, InOutPortReg } }, { "out", 1, 0xe6, None, 0, W|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8 } }, { "out", 1, 0xee, None, 0, W|No_sSuf|No_qSuf|No_xSuf, + 0, { InOutPortReg } }, { "lea", 2, 0x8d, None, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "lds", 2, 0xc5, None, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "les", 2, 0xc4, None, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "lfs", 2, 0xfb4, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "lgs", 2, 0xfb5, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "lss", 2, 0xfb2, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "clc", 0, 0xf8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "cld", 0, 0xfc, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "cli", 0, 0xfa, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "clts", 0, 0xf06, None, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "cmc", 0, 0xf5, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "lahf", 0, 0x9f, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "sahf", 0, 0x9e, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "pushf", 0, 0x9c, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "pushf", 0, 0x9c, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + 0, { 0 } }, { "popf", 0, 0x9d, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "popf", 0, 0x9d, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + 0, { 0 } }, { "stc", 0, 0xf9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "std", 0, 0xfd, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "sti", 0, 0xfb, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "add", 2, 0x0, None, 0, D|W|Modrm|No_sSuf|No_xSuf, + 0, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "add", 2, 0x83, 0x0, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "add", 2, 0x4, None, 0, W|No_sSuf|No_xSuf, + 0, { Imm8|Imm16|Imm32|Imm32S, Acc } }, { "add", 2, 0x80, 0x0, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "inc", 1, 0x40, None, CpuNo64, ShortForm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64 } }, { "inc", 1, 0xfe, 0x0, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sub", 2, 0x28, None, 0, D|W|Modrm|No_sSuf|No_xSuf, + 0, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sub", 2, 0x83, 0x5, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sub", 2, 0x2c, None, 0, W|No_sSuf|No_xSuf, + 0, { Imm8|Imm16|Imm32|Imm32S, Acc } }, { "sub", 2, 0x80, 0x5, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "dec", 1, 0x48, None, CpuNo64, ShortForm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64 } }, { "dec", 1, 0xfe, 0x1, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sbb", 2, 0x18, None, 0, D|W|Modrm|No_sSuf|No_xSuf, + 0, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sbb", 2, 0x83, 0x3, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sbb", 2, 0x1c, None, 0, W|No_sSuf|No_xSuf, + 0, { Imm8|Imm16|Imm32|Imm32S, Acc } }, { "sbb", 2, 0x80, 0x3, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "cmp", 2, 0x38, None, 0, D|W|Modrm|No_sSuf|No_xSuf, + 0, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "cmp", 2, 0x83, 0x7, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "cmp", 2, 0x3c, None, 0, W|No_sSuf|No_xSuf, + 0, { Imm8|Imm16|Imm32|Imm32S, Acc } }, { "cmp", 2, 0x80, 0x7, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "test", 2, 0x84, None, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "test", 2, 0x84, None, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg8|Reg16|Reg32|Reg64 } }, { "test", 2, 0xa8, None, 0, W|No_sSuf|No_xSuf, + 0, { Imm8|Imm16|Imm32|Imm32S, Acc } }, { "test", 2, 0xf6, 0x0, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "and", 2, 0x20, None, 0, D|W|Modrm|No_sSuf|No_xSuf, + 0, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "and", 2, 0x83, 0x4, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "and", 2, 0x24, None, 0, W|No_sSuf|No_xSuf, + 0, { Imm8|Imm16|Imm32|Imm32S, Acc } }, { "and", 2, 0x80, 0x4, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "or", 2, 0x8, None, 0, D|W|Modrm|No_sSuf|No_xSuf, + 0, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "or", 2, 0x83, 0x1, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "or", 2, 0xc, None, 0, W|No_sSuf|No_xSuf, + 0, { Imm8|Imm16|Imm32|Imm32S, Acc } }, { "or", 2, 0x80, 0x1, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "xor", 2, 0x30, None, 0, D|W|Modrm|No_sSuf|No_xSuf, + 0, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "xor", 2, 0x83, 0x6, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "xor", 2, 0x34, None, 0, W|No_sSuf|No_xSuf, + 0, { Imm8|Imm16|Imm32|Imm32S, Acc } }, { "xor", 2, 0x80, 0x6, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "clr", 1, 0x30, None, 0, W|Modrm|No_sSuf|No_xSuf|RegKludge, + 0, { Reg8|Reg16|Reg32|Reg64 } }, { "adc", 2, 0x10, None, 0, D|W|Modrm|No_sSuf|No_xSuf, + 0, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "adc", 2, 0x83, 0x2, 0, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "adc", 2, 0x14, None, 0, W|No_sSuf|No_xSuf, + 0, { Imm8|Imm16|Imm32|Imm32S, Acc } }, { "adc", 2, 0x80, 0x2, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "neg", 1, 0xf6, 0x3, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "not", 1, 0xf6, 0x2, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "aaa", 0, 0x37, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "aas", 0, 0x3f, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "daa", 0, 0x27, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "das", 0, 0x2f, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "aad", 0, 0xd50a, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "aad", 1, 0xd5, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8 } }, { "aam", 0, 0xd40a, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "aam", 1, 0xd4, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8 } }, { "cbw", 0, 0x98, None, 0, Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "cdqe", 0, 0x98, None, Cpu64, Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "cwde", 0, 0x98, None, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "cwd", 0, 0x99, None, 0, Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "cdq", 0, 0x99, None, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "cqo", 0, 0x99, None, Cpu64, Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "cbtw", 0, 0x98, None, 0, Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "cltq", 0, 0x98, None, Cpu64, Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "cwtl", 0, 0x98, None, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "cwtd", 0, 0x99, None, 0, Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "cltd", 0, 0x99, None, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "cqto", 0, 0x99, None, Cpu64, Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "mul", 1, 0xf6, 0x4, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "imul", 1, 0xf6, 0x5, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "imul", 2, 0xfaf, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "imul", 3, 0x6b, None, Cpu186, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Imm8S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "imul", 3, 0x69, None, Cpu186, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "imul", 2, 0x6b, None, Cpu186, Modrm|No_bSuf|No_sSuf|No_xSuf|RegKludge, + 0, { Imm8S, Reg16|Reg32|Reg64 } }, { "imul", 2, 0x69, None, Cpu186, Modrm|No_bSuf|No_sSuf|No_xSuf|RegKludge, + 0, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64 } }, { "div", 1, 0xf6, 0x6, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "div", 2, 0xf6, 0x6, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Acc } }, { "idiv", 1, 0xf6, 0x7, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "idiv", 2, 0xf6, 0x7, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Acc } }, { "rol", 2, 0xd0, 0x0, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "rol", 2, 0xc0, 0x0, Cpu186, W|Modrm|No_sSuf|No_xSuf, + 0, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "rol", 2, 0xd2, 0x0, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "rol", 1, 0xd0, 0x0, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "ror", 2, 0xd0, 0x1, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "ror", 2, 0xc0, 0x1, Cpu186, W|Modrm|No_sSuf|No_xSuf, + 0, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "ror", 2, 0xd2, 0x1, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "ror", 1, 0xd0, 0x1, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "rcl", 2, 0xd0, 0x2, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "rcl", 2, 0xc0, 0x2, Cpu186, W|Modrm|No_sSuf|No_xSuf, + 0, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "rcl", 2, 0xd2, 0x2, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "rcl", 1, 0xd0, 0x2, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "rcr", 2, 0xd0, 0x3, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "rcr", 2, 0xc0, 0x3, Cpu186, W|Modrm|No_sSuf|No_xSuf, + 0, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "rcr", 2, 0xd2, 0x3, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "rcr", 1, 0xd0, 0x3, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sal", 2, 0xd0, 0x4, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sal", 2, 0xc0, 0x4, Cpu186, W|Modrm|No_sSuf|No_xSuf, + 0, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sal", 2, 0xd2, 0x4, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sal", 1, 0xd0, 0x4, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "shl", 2, 0xd0, 0x4, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "shl", 2, 0xc0, 0x4, Cpu186, W|Modrm|No_sSuf|No_xSuf, + 0, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "shl", 2, 0xd2, 0x4, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "shl", 1, 0xd0, 0x4, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "shr", 2, 0xd0, 0x5, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "shr", 2, 0xc0, 0x5, Cpu186, W|Modrm|No_sSuf|No_xSuf, + 0, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "shr", 2, 0xd2, 0x5, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "shr", 1, 0xd0, 0x5, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sar", 2, 0xd0, 0x7, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Imm1, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sar", 2, 0xc0, 0x7, Cpu186, W|Modrm|No_sSuf|No_xSuf, + 0, { Imm8, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sar", 2, 0xd2, 0x7, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { ShiftCount, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sar", 1, 0xd0, 0x7, 0, W|Modrm|No_sSuf|No_xSuf, + 0, { Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "shld", 3, 0xfa4, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "shld", 3, 0xfa5, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "shld", 2, 0xfa5, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "shrd", 3, 0xfac, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "shrd", 3, 0xfad, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "shrd", 2, 0xfad, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "call", 1, 0xe8, None, CpuNo64, JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp16|Disp32 } }, { "call", 1, 0xe8, None, Cpu64, JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + 0, { Disp16|Disp32 } }, { "call", 1, 0xff, 0x2, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } }, { "call", 1, 0xff, 0x2, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + 0, { Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } }, { "call", 2, 0x9a, None, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm16, Imm16|Imm32 } }, { "call", 1, 0xff, 0x3, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } }, { "lcall", 2, 0x9a, None, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm16, Imm16|Imm32 } }, { "lcall", 1, 0xff, 0x3, 0, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } }, { "jmp", 1, 0xeb, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jmp", 1, 0xff, 0x4, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } }, { "jmp", 1, 0xff, 0x4, Cpu64, Modrm|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + 0, { Reg16|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } }, { "jmp", 2, 0xea, None, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm16, Imm16|Imm32 } }, { "jmp", 1, 0xff, 0x5, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } }, { "ljmp", 2, 0xea, None, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm16, Imm16|Imm32 } }, { "ljmp", 1, 0xff, 0x5, 0, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|JumpAbsolute } }, { "ret", 0, 0xc3, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "ret", 1, 0xc2, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm16 } }, { "ret", 0, 0xc3, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + 0, { 0 } }, { "ret", 1, 0xc2, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + 0, { Imm16 } }, { "lret", 0, 0xcb, None, 0, DefaultSize|No_bSuf|No_sSuf|No_xSuf, + 0, { 0 } }, { "lret", 1, 0xca, None, 0, DefaultSize|No_bSuf|No_sSuf|No_xSuf, + 0, { Imm16 } }, { "enter", 2, 0xc8, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm16, Imm8 } }, { "enter", 2, 0xc8, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + 0, { Imm16, Imm8 } }, { "leave", 0, 0xc9, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "leave", 0, 0xc9, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + 0, { 0 } }, { "jo", 1, 0x70, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jno", 1, 0x71, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jb", 1, 0x72, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jc", 1, 0x72, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jnae", 1, 0x72, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jnb", 1, 0x73, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jnc", 1, 0x73, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jae", 1, 0x73, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "je", 1, 0x74, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jz", 1, 0x74, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jne", 1, 0x75, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jnz", 1, 0x75, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jbe", 1, 0x76, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jna", 1, 0x76, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jnbe", 1, 0x77, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "ja", 1, 0x77, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "js", 1, 0x78, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jns", 1, 0x79, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jp", 1, 0x7a, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jpe", 1, 0x7a, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jnp", 1, 0x7b, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jpo", 1, 0x7b, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jl", 1, 0x7c, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jnge", 1, 0x7c, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jnl", 1, 0x7d, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jge", 1, 0x7d, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jle", 1, 0x7e, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jng", 1, 0x7e, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jnle", 1, 0x7f, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jg", 1, 0x7f, None, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jcxz", 1, 0xe3, None, CpuNo64, JumpByte|Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jecxz", 1, 0xe3, None, CpuNo64, JumpByte|Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jecxz", 1, 0x67e3, None, Cpu64, JumpByte|Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "jrcxz", 1, 0xe3, None, Cpu64, JumpByte|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "loop", 1, 0xe2, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "loop", 1, 0xe2, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "loopz", 1, 0xe1, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "loopz", 1, 0xe1, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "loope", 1, 0xe1, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "loope", 1, 0xe1, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "loopnz", 1, 0xe0, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "loopnz", 1, 0xe0, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "loopne", 1, 0xe0, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "loopne", 1, 0xe0, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_xSuf|NoRex64, + 0, { Disp8|Disp16|Disp32|Disp32S|Disp64 } }, { "seto", 1, 0xf90, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setno", 1, 0xf91, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setb", 1, 0xf92, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setc", 1, 0xf92, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setnae", 1, 0xf92, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setnb", 1, 0xf93, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setnc", 1, 0xf93, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setae", 1, 0xf93, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sete", 1, 0xf94, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setz", 1, 0xf94, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setne", 1, 0xf95, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setnz", 1, 0xf95, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setbe", 1, 0xf96, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setna", 1, 0xf96, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setnbe", 1, 0xf97, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "seta", 1, 0xf97, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sets", 1, 0xf98, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setns", 1, 0xf99, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setp", 1, 0xf9a, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setpe", 1, 0xf9a, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setnp", 1, 0xf9b, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setpo", 1, 0xf9b, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setl", 1, 0xf9c, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setnge", 1, 0xf9c, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setnl", 1, 0xf9d, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setge", 1, 0xf9d, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setle", 1, 0xf9e, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setng", 1, 0xf9e, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setnle", 1, 0xf9f, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "setg", 1, 0xf9f, 0x0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "cmps", 0, 0xa6, None, 0, W|No_sSuf|No_xSuf|IsString, + 0, { 0 } }, { "cmps", 2, 0xa6, None, 0, W|No_sSuf|No_xSuf|IsString, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg, BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "scmp", 0, 0xa6, None, 0, W|No_sSuf|No_xSuf|IsString, + 0, { 0 } }, { "scmp", 2, 0xa6, None, 0, W|No_sSuf|No_xSuf|IsString, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg, BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "ins", 0, 0x6c, None, Cpu186, W|No_sSuf|No_qSuf|No_xSuf|IsString, + 0, { 0 } }, { "ins", 2, 0x6c, None, Cpu186, W|No_sSuf|No_qSuf|No_xSuf|IsString, + 0, { InOutPortReg, BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, { "outs", 0, 0x6e, None, Cpu186, W|No_sSuf|No_qSuf|No_xSuf|IsString, + 0, { 0 } }, { "outs", 2, 0x6e, None, Cpu186, W|No_sSuf|No_qSuf|No_xSuf|IsString, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, InOutPortReg } }, { "lods", 0, 0xac, None, 0, W|No_sSuf|No_xSuf|IsString, + 0, { 0 } }, { "lods", 1, 0xac, None, 0, W|No_sSuf|No_xSuf|IsString, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "lods", 2, 0xac, None, 0, W|No_sSuf|No_xSuf|IsString, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Acc } }, { "slod", 0, 0xac, None, 0, W|No_sSuf|No_xSuf|IsString, + 0, { 0 } }, { "slod", 1, 0xac, None, 0, W|No_sSuf|No_xSuf|IsString, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "slod", 2, 0xac, None, 0, W|No_sSuf|No_xSuf|IsString, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Acc } }, { "movs", 0, 0xa4, None, 0, W|No_sSuf|No_xSuf|IsString, + 0, { 0 } }, { "movs", 2, 0xa4, None, 0, W|No_sSuf|No_xSuf|IsString, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, { "smov", 0, 0xa4, None, 0, W|No_sSuf|No_xSuf|IsString, + 0, { 0 } }, { "smov", 2, 0xa4, None, 0, W|No_sSuf|No_xSuf|IsString, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, { "scas", 0, 0xae, None, 0, W|No_sSuf|No_xSuf|IsString, + 0, { 0 } }, { "scas", 1, 0xae, None, 0, W|No_sSuf|No_xSuf|IsString, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, { "scas", 2, 0xae, None, 0, W|No_sSuf|No_xSuf|IsString, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg, Acc } }, { "ssca", 0, 0xae, None, 0, W|No_sSuf|No_xSuf|IsString, + 0, { 0 } }, { "ssca", 1, 0xae, None, 0, W|No_sSuf|No_xSuf|IsString, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, { "ssca", 2, 0xae, None, 0, W|No_sSuf|No_xSuf|IsString, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg, Acc } }, { "stos", 0, 0xaa, None, 0, W|No_sSuf|No_xSuf|IsString, + 0, { 0 } }, { "stos", 1, 0xaa, None, 0, W|No_sSuf|No_xSuf|IsString, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, { "stos", 2, 0xaa, None, 0, W|No_sSuf|No_xSuf|IsString, + 0, { Acc, BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, { "ssto", 0, 0xaa, None, 0, W|No_sSuf|No_xSuf|IsString, + 0, { 0 } }, { "ssto", 1, 0xaa, None, 0, W|No_sSuf|No_xSuf|IsString, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, { "ssto", 2, 0xaa, None, 0, W|No_sSuf|No_xSuf|IsString, + 0, { Acc, BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, { "xlat", 0, 0xd7, None, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString, + 0, { 0 } }, { "xlat", 1, 0xd7, None, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "bsf", 2, 0xfbc, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "bsr", 2, 0xfbd, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "bt", 2, 0xfa3, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "bt", 2, 0xfba, 0x4, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Imm8, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "btc", 2, 0xfbb, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "btc", 2, 0xfba, 0x7, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Imm8, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "btr", 2, 0xfb3, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "btr", 2, 0xfba, 0x6, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Imm8, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "bts", 2, 0xfab, None, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "bts", 2, 0xfba, 0x5, Cpu386, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Imm8, Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "int", 1, 0xcd, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8 } }, { "int3", 0, 0xcc, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "into", 0, 0xce, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "iret", 0, 0xcf, None, 0, DefaultSize|No_bSuf|No_sSuf|No_xSuf, + 0, { 0 } }, { "rsm", 0, 0xfaa, None, Cpu386, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "bound", 2, 0x62, None, Cpu186|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64, BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "hlt", 0, 0xf4, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "nop", 1, 0xf1f, 0x0, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "nop", 0, 0x90, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "arpl", 2, 0x63, None, Cpu286|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg16, Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "lar", 2, 0xf02, None, Cpu286, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "lgdt", 1, 0xf01, 0x2, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "lgdt", 1, 0xf01, 0x2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "lidt", 1, 0xf01, 0x3, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "lidt", 1, 0xf01, 0x3, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "lldt", 1, 0xf00, 0x2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "lmsw", 1, 0xf01, 0x6, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "lsl", 2, 0xf03, None, Cpu286, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "ltr", 1, 0xf00, 0x3, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sgdt", 1, 0xf01, 0x0, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sgdt", 1, 0xf01, 0x0, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sidt", 1, 0xf01, 0x1, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sidt", 1, 0xf01, 0x1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sldt", 1, 0xf00, 0x0, Cpu286, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64 } }, { "sldt", 1, 0xf00, 0x0, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "smsw", 1, 0xf01, 0x4, Cpu286, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64 } }, { "smsw", 1, 0xf01, 0x4, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "str", 1, 0xf00, 0x1, Cpu286, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64 } }, { "str", 1, 0xf00, 0x1, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "verr", 1, 0xf00, 0x4, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "verw", 1, 0xf00, 0x5, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg16|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fld", 1, 0xd9c0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg } }, { "fld", 1, 0xd9, 0x0, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fld", 1, 0xd9c0, None, 0, ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + 0, { FloatReg } }, { "fld", 1, 0xdb, 0x5, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fild", 1, 0xdf, 0x0, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fild", 1, 0xdf, 0x5, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fildll", 1, 0xdf, 0x5, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fldt", 1, 0xdb, 0x5, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fbld", 1, 0xdf, 0x4, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fst", 1, 0xddd0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg } }, { "fst", 1, 0xd9, 0x2, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fst", 1, 0xddd0, None, 0, ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + 0, { FloatReg } }, { "fist", 1, 0xdf, 0x2, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fstp", 1, 0xddd8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg } }, { "fstp", 1, 0xd9, 0x3, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fstp", 1, 0xddd8, None, 0, ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + 0, { FloatReg } }, { "fstp", 1, 0xdb, 0x7, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fistp", 1, 0xdf, 0x3, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fistp", 1, 0xdf, 0x7, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fistpll", 1, 0xdf, 0x7, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fstpt", 1, 0xdb, 0x7, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fbstp", 1, 0xdf, 0x6, 0, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fxch", 1, 0xd9c8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg } }, { "fxch", 0, 0xd9c9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fcom", 1, 0xd8d0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg } }, { "fcom", 0, 0xd8d1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fcom", 1, 0xd8, 0x2, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fcom", 1, 0xd8d0, None, 0, ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + 0, { FloatReg } }, { "ficom", 1, 0xde, 0x2, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fcomp", 1, 0xd8d8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg } }, { "fcomp", 0, 0xd8d9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fcomp", 1, 0xd8, 0x3, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fcomp", 1, 0xd8d8, None, 0, ShortForm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + 0, { FloatReg } }, { "ficomp", 1, 0xde, 0x3, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fcompp", 0, 0xded9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fucom", 1, 0xdde0, None, Cpu286, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg } }, { "fucom", 0, 0xdde1, None, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fucomp", 1, 0xdde8, None, Cpu286, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg } }, { "fucomp", 0, 0xdde9, None, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fucompp", 0, 0xdae9, None, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "ftst", 0, 0xd9e4, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fxam", 0, 0xd9e5, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fld1", 0, 0xd9e8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fldl2t", 0, 0xd9e9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fldl2e", 0, 0xd9ea, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fldpi", 0, 0xd9eb, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fldlg2", 0, 0xd9ec, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fldln2", 0, 0xd9ed, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fldz", 0, 0xd9ee, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fadd", 2, 0xd8c0, None, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg, FloatAcc } }, { "fadd", 1, 0xd8c0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg } }, #if SYSV386_COMPAT { "fadd", 0, 0xdec1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + 0, { 0 } }, #endif { "fadd", 1, 0xd8, 0x0, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fiadd", 1, 0xde, 0x0, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "faddp", 2, 0xdec0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatAcc, FloatReg } }, { "faddp", 1, 0xdec0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg } }, { "faddp", 0, 0xdec1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "faddp", 2, 0xdec0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + 0, { FloatReg, FloatAcc } }, { "fsub", 1, 0xd8e0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg } }, #if SYSV386_COMPAT { "fsub", 2, 0xd8e0, None, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg, FloatAcc } }, { "fsub", 0, 0xdee1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + 0, { 0 } }, #else { "fsub", 2, 0xd8e0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR, + 0, { FloatReg, FloatAcc } }, #endif { "fsub", 1, 0xd8, 0x4, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fisub", 1, 0xde, 0x4, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, #if SYSV386_COMPAT { "fsubp", 2, 0xdee0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatAcc, FloatReg } }, { "fsubp", 1, 0xdee0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg } }, { "fsubp", 0, 0xdee1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, #if OLDGCC_COMPAT { "fsubp", 2, 0xdee0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + 0, { FloatReg, FloatAcc } }, #endif #else { "fsubp", 2, 0xdee8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, + 0, { FloatAcc, FloatReg } }, { "fsubp", 1, 0xdee8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, + 0, { FloatReg } }, { "fsubp", 0, 0xdee9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf, + 0, { 0 } }, #endif { "fsubr", 1, 0xd8e8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg } }, #if SYSV386_COMPAT { "fsubr", 2, 0xd8e8, None, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg, FloatAcc } }, { "fsubr", 0, 0xdee9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + 0, { 0 } }, #else { "fsubr", 2, 0xd8e8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR, + 0, { FloatReg, FloatAcc } }, #endif { "fsubr", 1, 0xd8, 0x5, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fisubr", 1, 0xde, 0x5, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, #if SYSV386_COMPAT { "fsubrp", 2, 0xdee8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatAcc, FloatReg } }, { "fsubrp", 1, 0xdee8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg } }, { "fsubrp", 0, 0xdee9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, #if OLDGCC_COMPAT { "fsubrp", 2, 0xdee8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + 0, { FloatReg, FloatAcc } }, #endif #else { "fsubrp", 2, 0xdee0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, + 0, { FloatAcc, FloatReg } }, { "fsubrp", 1, 0xdee0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, + 0, { FloatReg } }, { "fsubrp", 0, 0xdee1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf, + 0, { 0 } }, #endif { "fmul", 2, 0xd8c8, None, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg, FloatAcc } }, { "fmul", 1, 0xd8c8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg } }, #if SYSV386_COMPAT { "fmul", 0, 0xdec9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + 0, { 0 } }, #endif { "fmul", 1, 0xd8, 0x1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fimul", 1, 0xde, 0x1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fmulp", 2, 0xdec8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatAcc, FloatReg } }, { "fmulp", 1, 0xdec8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg } }, { "fmulp", 0, 0xdec9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fmulp", 2, 0xdec8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + 0, { FloatReg, FloatAcc } }, { "fdiv", 1, 0xd8f0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg } }, #if SYSV386_COMPAT { "fdiv", 2, 0xd8f0, None, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg, FloatAcc } }, { "fdiv", 0, 0xdef1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + 0, { 0 } }, #else { "fdiv", 2, 0xd8f0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR, + 0, { FloatReg, FloatAcc } }, #endif { "fdiv", 1, 0xd8, 0x6, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fidiv", 1, 0xde, 0x6, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, #if SYSV386_COMPAT { "fdivp", 2, 0xdef0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatAcc, FloatReg } }, { "fdivp", 1, 0xdef0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg } }, { "fdivp", 0, 0xdef1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, #if OLDGCC_COMPAT { "fdivp", 2, 0xdef0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + 0, { FloatReg, FloatAcc } }, #endif #else { "fdivp", 2, 0xdef8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, + 0, { FloatAcc, FloatReg } }, { "fdivp", 1, 0xdef8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, + 0, { FloatReg } }, { "fdivp", 0, 0xdef9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf, + 0, { 0 } }, #endif { "fdivr", 1, 0xd8f8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg } }, #if SYSV386_COMPAT { "fdivr", 2, 0xd8f8, None, 0, ShortForm|FloatD|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg, FloatAcc } }, { "fdivr", 0, 0xdef9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + 0, { 0 } }, #else { "fdivr", 2, 0xd8f8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm|FloatD|FloatR, + 0, { FloatReg, FloatAcc } }, #endif { "fdivr", 1, 0xd8, 0x7, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fidivr", 1, 0xde, 0x7, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, #if SYSV386_COMPAT { "fdivrp", 2, 0xdef8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatAcc, FloatReg } }, { "fdivrp", 1, 0xdef8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg } }, { "fdivrp", 0, 0xdef9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, #if OLDGCC_COMPAT { "fdivrp", 2, 0xdef8, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Ugh, + 0, { FloatReg, FloatAcc } }, #endif #else { "fdivrp", 2, 0xdef0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, + 0, { FloatAcc, FloatReg } }, { "fdivrp", 1, 0xdef0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf|ShortForm, + 0, { FloatReg } }, { "fdivrp", 0, 0xdef1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf, + 0, { 0 } }, #endif { "f2xm1", 0, 0xd9f0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fyl2x", 0, 0xd9f1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fptan", 0, 0xd9f2, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fpatan", 0, 0xd9f3, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fxtract", 0, 0xd9f4, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fprem1", 0, 0xd9f5, None, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fdecstp", 0, 0xd9f6, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fincstp", 0, 0xd9f7, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fprem", 0, 0xd9f8, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fyl2xp1", 0, 0xd9f9, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fsqrt", 0, 0xd9fa, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fsincos", 0, 0xd9fb, None, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "frndint", 0, 0xd9fc, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fscale", 0, 0xd9fd, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fsin", 0, 0xd9fe, None, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fcos", 0, 0xd9ff, None, Cpu286, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fchs", 0, 0xd9e0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fabs", 0, 0xd9e1, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fninit", 0, 0xdbe3, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "finit", 0, 0xdbe3, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait, + 0, { 0 } }, { "fldcw", 1, 0xd9, 0x5, 0, Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fnstcw", 1, 0xd9, 0x7, 0, Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fstcw", 1, 0xd9, 0x7, 0, Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fnstsw", 1, 0xdfe0, None, 0, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Acc } }, { "fnstsw", 1, 0xdd, 0x7, 0, Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fnstsw", 0, 0xdfe0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fstsw", 1, 0xdfe0, None, 0, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait, + 0, { Acc } }, { "fstsw", 1, 0xdd, 0x7, 0, Modrm|FloatMF|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fstsw", 0, 0xdfe0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait, + 0, { 0 } }, { "fnclex", 0, 0xdbe2, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fclex", 0, 0xdbe2, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|FWait, + 0, { 0 } }, { "fnstenv", 1, 0xd9, 0x6, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fstenv", 1, 0xd9, 0x6, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf|FWait, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fldenv", 1, 0xd9, 0x4, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fnsave", 1, 0xdd, 0x6, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fsave", 1, 0xdd, 0x6, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf|FWait, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "frstor", 1, 0xdd, 0x4, 0, Modrm|DefaultSize|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "ffree", 1, 0xddc0, None, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg } }, { "ffreep", 1, 0xdfc0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg } }, { "fnop", 0, 0xd9d0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fwait", 0, 0x9b, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "addr16", 0, 0x67, None, Cpu386|CpuNo64, Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "addr32", 0, 0x67, None, Cpu386, Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "aword", 0, 0x67, None, Cpu386|CpuNo64, Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "adword", 0, 0x67, None, Cpu386, Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "data16", 0, 0x66, None, Cpu386, Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "data32", 0, 0x66, None, Cpu386|CpuNo64, Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "word", 0, 0x66, None, Cpu386, Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "dword", 0, 0x66, None, Cpu386|CpuNo64, Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "lock", 0, 0xf0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "wait", 0, 0x9b, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "cs", 0, 0x2e, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "ds", 0, 0x3e, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "es", 0, 0x26, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "fs", 0, 0x64, None, Cpu386, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "gs", 0, 0x65, None, Cpu386, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "ss", 0, 0x36, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "rep", 0, 0xf3, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "repe", 0, 0xf3, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "repz", 0, 0xf3, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "repne", 0, 0xf2, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "repnz", 0, 0xf2, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "ht", 0, 0x3e, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "hnt", 0, 0x2e, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "rex", 0, 0x40, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "rexz", 0, 0x41, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "rexy", 0, 0x42, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "rexyz", 0, 0x43, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "rexx", 0, 0x44, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "rexxz", 0, 0x45, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "rexxy", 0, 0x46, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "rexxyz", 0, 0x47, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "rex64", 0, 0x48, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "rex64z", 0, 0x49, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "rex64y", 0, 0x4a, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "rex64yz", 0, 0x4b, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "rex64x", 0, 0x4c, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "rex64xz", 0, 0x4d, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "rex64xy", 0, 0x4e, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "rex64xyz", 0, 0x4f, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "rex.b", 0, 0x41, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "rex.x", 0, 0x42, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "rex.xb", 0, 0x43, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "rex.r", 0, 0x44, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "rex.rb", 0, 0x45, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "rex.rx", 0, 0x46, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "rex.rxb", 0, 0x47, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "rex.w", 0, 0x48, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "rex.wb", 0, 0x49, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "rex.wx", 0, 0x4a, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "rex.wxb", 0, 0x4b, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "rex.wr", 0, 0x4c, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "rex.wrb", 0, 0x4d, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "rex.wrx", 0, 0x4e, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "rex.wrxb", 0, 0x4f, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsPrefix, + 0, { 0 } }, { "bswap", 1, 0xfc8, None, Cpu486, ShortForm|No_bSuf|No_wSuf|No_sSuf|No_xSuf, + 0, { Reg32|Reg64 } }, { "xadd", 2, 0xfc0, None, Cpu486, W|Modrm|No_sSuf|No_xSuf, + 0, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "cmpxchg", 2, 0xfb0, None, Cpu486, W|Modrm|No_sSuf|No_xSuf, + 0, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "invd", 0, 0xf08, None, Cpu486, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "wbinvd", 0, 0xf09, None, Cpu486, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "invlpg", 1, 0xf01, 0x7, Cpu486, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "cpuid", 0, 0xfa2, None, Cpu486, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "wrmsr", 0, 0xf30, None, Cpu586, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "rdtsc", 0, 0xf31, None, Cpu586, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "rdmsr", 0, 0xf32, None, Cpu586, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "cmpxchg8b", 1, 0xfc7, 0x1, Cpu586, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "sysenter", 0, 0xf34, None, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "sysexit", 0, 0xf35, None, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fxsave", 1, 0xfae, 0x0, Cpu686, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fxrstor", 1, 0xfae, 0x1, Cpu686, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "rdpmc", 0, 0xf33, None, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "ud2", 0, 0xf0b, None, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "ud2a", 0, 0xf0b, None, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "ud2b", 0, 0xfb9, None, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "cmovo", 2, 0xf40, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovno", 2, 0xf41, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovb", 2, 0xf42, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovc", 2, 0xf42, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovnae", 2, 0xf42, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovae", 2, 0xf43, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovnc", 2, 0xf43, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovnb", 2, 0xf43, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmove", 2, 0xf44, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovz", 2, 0xf44, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovne", 2, 0xf45, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovnz", 2, 0xf45, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovbe", 2, 0xf46, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovna", 2, 0xf46, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmova", 2, 0xf47, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovnbe", 2, 0xf47, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovs", 2, 0xf48, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovns", 2, 0xf49, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovp", 2, 0xf4a, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovnp", 2, 0xf4b, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovl", 2, 0xf4c, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovnge", 2, 0xf4c, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovge", 2, 0xf4d, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovnl", 2, 0xf4d, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovle", 2, 0xf4e, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovng", 2, 0xf4e, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovg", 2, 0xf4f, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "cmovnle", 2, 0xf4f, None, Cpu686, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "fcmovb", 2, 0xdac0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg, FloatAcc } }, { "fcmovnae", 2, 0xdac0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg, FloatAcc } }, { "fcmove", 2, 0xdac8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg, FloatAcc } }, { "fcmovbe", 2, 0xdad0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg, FloatAcc } }, { "fcmovna", 2, 0xdad0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg, FloatAcc } }, { "fcmovu", 2, 0xdad8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg, FloatAcc } }, { "fcmovae", 2, 0xdbc0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg, FloatAcc } }, { "fcmovnb", 2, 0xdbc0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg, FloatAcc } }, { "fcmovne", 2, 0xdbc8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg, FloatAcc } }, { "fcmova", 2, 0xdbd0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg, FloatAcc } }, { "fcmovnbe", 2, 0xdbd0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg, FloatAcc } }, { "fcmovnu", 2, 0xdbd8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg, FloatAcc } }, { "fcomi", 2, 0xdbf0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg, FloatAcc } }, { "fcomi", 0, 0xdbf1, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fcomi", 1, 0xdbf0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg } }, { "fucomi", 2, 0xdbe8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg, FloatAcc } }, { "fucomi", 0, 0xdbe9, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fucomi", 1, 0xdbe8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg } }, { "fcomip", 2, 0xdff0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg, FloatAcc } }, { "fcompi", 2, 0xdff0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg, FloatAcc } }, { "fcompi", 0, 0xdff1, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fcompi", 1, 0xdff0, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg } }, { "fucomip", 2, 0xdfe8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg, FloatAcc } }, { "fucompi", 2, 0xdfe8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg, FloatAcc } }, { "fucompi", 0, 0xdfe9, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "fucompi", 1, 0xdfe8, None, Cpu686, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { FloatReg } }, { "movnti", 2, 0xfc3, None, CpuP4, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64, BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "clflush", 1, 0xfae, 0x7, CpuP4, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "lfence", 0, 0xfae, 0xe8, CpuP4, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { 0 } }, { "mfence", 0, 0xfae, 0xf0, CpuP4, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { 0 } }, { "pause", 0, 0xf390, None, CpuP4, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "emms", 0, 0xf77, None, CpuMMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "movd", 2, 0xf6e, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegMMX } }, { "movd", 2, 0xf7e, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { RegMMX, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "movd", 2, 0x660f6e, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } }, { "movd", 2, 0x660f7e, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { RegXMM, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "movq", 2, 0xf6f, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "movq", 2, 0xf7f, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, + 0, { RegMMX, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX } }, { "movq", 2, 0xf30f7e, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "movq", 2, 0x660fd6, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, + 0, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } }, { "movq", 2, 0xf6e, None, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegMMX } }, { "movq", 2, 0xf7e, None, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { RegMMX, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "movq", 2, 0x660f6e, None, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } }, { "movq", 2, 0x660f7e, None, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { RegXMM, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "movq", 2, 0xa0, None, Cpu64, D|W|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Disp64, Acc } }, { "movq", 2, 0x88, None, Cpu64, D|W|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg64, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "movq", 2, 0xc6, 0x0, Cpu64, W|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm32S, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "movq", 2, 0xb0, None, Cpu64, W|ShortForm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm64, Reg64 } }, { "movq", 2, 0x8c, None, Cpu64, Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { SReg2|SReg3, Reg64|RegMem } }, { "movq", 2, 0x8e, None, Cpu64, Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg64, SReg2|SReg3 } }, { "movq", 2, 0xf20, None, Cpu64, D|Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, + 0, { Control, Reg64|RegMem } }, { "movq", 2, 0xf21, None, Cpu64, D|Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, + 0, { Debug, Reg64|RegMem } }, { "packssdw", 2, 0xf6b, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "packssdw", 2, 0x660f6b, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "packsswb", 2, 0xf63, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "packsswb", 2, 0x660f63, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "packuswb", 2, 0xf67, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "packuswb", 2, 0x660f67, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "paddb", 2, 0xffc, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "paddb", 2, 0x660ffc, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "paddw", 2, 0xffd, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "paddw", 2, 0x660ffd, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "paddd", 2, 0xffe, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "paddd", 2, 0x660ffe, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "paddq", 2, 0xfd4, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "paddq", 2, 0x660fd4, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "paddsb", 2, 0xfec, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "paddsb", 2, 0x660fec, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "paddsw", 2, 0xfed, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "paddsw", 2, 0x660fed, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "paddusb", 2, 0xfdc, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "paddusb", 2, 0x660fdc, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "paddusw", 2, 0xfdd, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "paddusw", 2, 0x660fdd, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pand", 2, 0xfdb, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pand", 2, 0x660fdb, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pandn", 2, 0xfdf, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pandn", 2, 0x660fdf, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pcmpeqb", 2, 0xf74, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pcmpeqb", 2, 0x660f74, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pcmpeqw", 2, 0xf75, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pcmpeqw", 2, 0x660f75, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pcmpeqd", 2, 0xf76, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pcmpeqd", 2, 0x660f76, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pcmpgtb", 2, 0xf64, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pcmpgtb", 2, 0x660f64, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pcmpgtw", 2, 0xf65, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pcmpgtw", 2, 0x660f65, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pcmpgtd", 2, 0xf66, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pcmpgtd", 2, 0x660f66, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmaddwd", 2, 0xff5, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pmaddwd", 2, 0x660ff5, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmulhw", 2, 0xfe5, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pmulhw", 2, 0x660fe5, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmullw", 2, 0xfd5, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pmullw", 2, 0x660fd5, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "por", 2, 0xfeb, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "por", 2, 0x660feb, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psllw", 2, 0xff1, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psllw", 2, 0x660ff1, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psllw", 2, 0xf71, 0x6, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, RegMMX } }, { "psllw", 2, 0x660f71, 0x6, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, RegXMM } }, { "pslld", 2, 0xff2, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pslld", 2, 0x660ff2, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pslld", 2, 0xf72, 0x6, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, RegMMX } }, { "pslld", 2, 0x660f72, 0x6, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, RegXMM } }, { "psllq", 2, 0xff3, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psllq", 2, 0x660ff3, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psllq", 2, 0xf73, 0x6, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, RegMMX } }, { "psllq", 2, 0x660f73, 0x6, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, RegXMM } }, { "psraw", 2, 0xfe1, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psraw", 2, 0x660fe1, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psraw", 2, 0xf71, 0x4, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, RegMMX } }, { "psraw", 2, 0x660f71, 0x4, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, RegXMM } }, { "psrad", 2, 0xfe2, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psrad", 2, 0x660fe2, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psrad", 2, 0xf72, 0x4, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, RegMMX } }, { "psrad", 2, 0x660f72, 0x4, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, RegXMM } }, { "psrlw", 2, 0xfd1, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psrlw", 2, 0x660fd1, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psrlw", 2, 0xf71, 0x2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, RegMMX } }, { "psrlw", 2, 0x660f71, 0x2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, RegXMM } }, { "psrld", 2, 0xfd2, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psrld", 2, 0x660fd2, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psrld", 2, 0xf72, 0x2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, RegMMX } }, { "psrld", 2, 0x660f72, 0x2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, RegXMM } }, { "psrlq", 2, 0xfd3, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psrlq", 2, 0x660fd3, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psrlq", 2, 0xf73, 0x2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, RegMMX } }, { "psrlq", 2, 0x660f73, 0x2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, RegXMM } }, { "psubb", 2, 0xff8, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psubb", 2, 0x660ff8, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psubw", 2, 0xff9, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psubw", 2, 0x660ff9, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psubd", 2, 0xffa, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psubd", 2, 0x660ffa, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psubq", 2, 0xffb, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psubq", 2, 0x660ffb, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psubsb", 2, 0xfe8, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psubsb", 2, 0x660fe8, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psubsw", 2, 0xfe9, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psubsw", 2, 0x660fe9, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psubusb", 2, 0xfd8, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psubusb", 2, 0x660fd8, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psubusw", 2, 0xfd9, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psubusw", 2, 0x660fd9, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "punpckhbw", 2, 0xf68, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "punpckhbw", 2, 0x660f68, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "punpckhwd", 2, 0xf69, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "punpckhwd", 2, 0x660f69, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "punpckhdq", 2, 0xf6a, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "punpckhdq", 2, 0x660f6a, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "punpcklbw", 2, 0xf60, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "punpcklbw", 2, 0x660f60, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "punpcklwd", 2, 0xf61, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "punpcklwd", 2, 0x660f61, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "punpckldq", 2, 0xf62, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "punpckldq", 2, 0x660f62, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pxor", 2, 0xfef, None, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pxor", 2, 0x660fef, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "addps", 2, 0xf58, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "addss", 2, 0xf30f58, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "andnps", 2, 0xf55, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "andps", 2, 0xf54, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpeqps", 2, 0xfc2, 0x0, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpeqss", 2, 0xf30fc2, 0x0, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpleps", 2, 0xfc2, 0x2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpless", 2, 0xf30fc2, 0x2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpltps", 2, 0xfc2, 0x1, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpltss", 2, 0xf30fc2, 0x1, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpneqps", 2, 0xfc2, 0x4, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpneqss", 2, 0xf30fc2, 0x4, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpnleps", 2, 0xfc2, 0x6, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpnless", 2, 0xf30fc2, 0x6, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpnltps", 2, 0xfc2, 0x5, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpnltss", 2, 0xf30fc2, 0x5, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpordps", 2, 0xfc2, 0x7, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpordss", 2, 0xf30fc2, 0x7, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpunordps", 2, 0xfc2, 0x3, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpunordss", 2, 0xf30fc2, 0x3, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpps", 3, 0xfc2, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpss", 3, 0xf30fc2, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "comiss", 2, 0xf2f, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cvtpi2ps", 2, 0xf2a, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegXMM } }, { "cvtps2pi", 2, 0xf2d, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegMMX } }, { "cvtsi2ss", 2, 0xf30f2a, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, + 0, { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } }, { "cvtss2si", 2, 0xf30f2d, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } }, { "cvttps2pi", 2, 0xf2c, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegMMX } }, { "cvttss2si", 2, 0xf30f2c, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } }, { "divps", 2, 0xf5e, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "divss", 2, 0xf30f5e, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "ldmxcsr", 1, 0xfae, 0x2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "maskmovq", 2, 0xff7, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { RegMMX, RegMMX } }, { "maxps", 2, 0xf5f, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "maxss", 2, 0xf30f5f, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "minps", 2, 0xf5d, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "minss", 2, 0xf30f5d, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "movaps", 2, 0xf28, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "movaps", 2, 0xf29, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } }, { "movhlps", 2, 0xf12, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { RegXMM, RegXMM } }, { "movhps", 2, 0xf16, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } }, { "movhps", 2, 0xf17, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "movlhps", 2, 0xf16, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { RegXMM, RegXMM } }, { "movlps", 2, 0xf12, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } }, { "movlps", 2, 0xf13, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "movmskps", 2, 0xf50, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, + 0, { RegXMM, Reg32|Reg64 } }, { "movntps", 2, 0xf2b, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "movntq", 2, 0xfe7, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { RegMMX, BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "movntdq", 2, 0x660fe7, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "movss", 2, 0xf30f10, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "movss", 2, 0xf30f11, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } }, { "movups", 2, 0xf10, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "movups", 2, 0xf11, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } }, { "mulps", 2, 0xf59, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "mulss", 2, 0xf30f59, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "orps", 2, 0xf56, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pavgb", 2, 0xfe0, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pavgb", 2, 0x660fe0, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pavgw", 2, 0xfe3, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pavgw", 2, 0x660fe3, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pextrw", 3, 0xfc5, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, + 0, { Imm8, RegMMX, Reg32|Reg64 } }, { "pextrw", 3, 0x660fc5, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, + 0, { Imm8, RegXMM, Reg32|Reg64 } }, { "pextrw", 3, 0x660f3a15, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, RegXMM, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "pinsrw", 3, 0xfc4, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, + 0, { Imm8, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegMMX } }, { "pinsrw", 3, 0x660fc4, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, + 0, { Imm8, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } }, { "pmaxsw", 2, 0xfee, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pmaxsw", 2, 0x660fee, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmaxub", 2, 0xfde, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pmaxub", 2, 0x660fde, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pminsw", 2, 0xfea, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pminsw", 2, 0x660fea, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pminub", 2, 0xfda, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pminub", 2, 0x660fda, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovmskb", 2, 0xfd7, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, + 0, { RegMMX, Reg32|Reg64 } }, { "pmovmskb", 2, 0x660fd7, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, + 0, { RegXMM, Reg32|Reg64 } }, { "pmulhuw", 2, 0xfe4, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pmulhuw", 2, 0x660fe4, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "prefetchnta", 1, 0xf18, 0x0, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "prefetcht0", 1, 0xf18, 0x1, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "prefetcht1", 1, 0xf18, 0x2, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "prefetcht2", 1, 0xf18, 0x3, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "psadbw", 2, 0xff6, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psadbw", 2, 0x660ff6, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pshufw", 3, 0xf70, None, CpuMMX2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "rcpps", 2, 0xf53, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "rcpss", 2, 0xf30f53, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "rsqrtps", 2, 0xf52, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "rsqrtss", 2, 0xf30f52, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "sfence", 0, 0xfae, 0xf8, CpuMMX2, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { 0 } }, { "shufps", 3, 0xfc6, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "sqrtps", 2, 0xf51, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "sqrtss", 2, 0xf30f51, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "stmxcsr", 1, 0xfae, 0x3, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "subps", 2, 0xf5c, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "subss", 2, 0xf30f5c, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "ucomiss", 2, 0xf2e, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "unpckhps", 2, 0xf15, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "unpcklps", 2, 0xf14, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "xorps", 2, 0xf57, None, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "addpd", 2, 0x660f58, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "addsd", 2, 0xf20f58, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "andnpd", 2, 0x660f55, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "andpd", 2, 0x660f54, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpeqpd", 2, 0x660fc2, 0x0, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpeqsd", 2, 0xf20fc2, 0x0, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmplepd", 2, 0x660fc2, 0x2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmplesd", 2, 0xf20fc2, 0x2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpltpd", 2, 0x660fc2, 0x1, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpltsd", 2, 0xf20fc2, 0x1, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpneqpd", 2, 0x660fc2, 0x4, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpneqsd", 2, 0xf20fc2, 0x4, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpnlepd", 2, 0x660fc2, 0x6, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpnlesd", 2, 0xf20fc2, 0x6, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpnltpd", 2, 0x660fc2, 0x5, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpnltsd", 2, 0xf20fc2, 0x5, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpordpd", 2, 0x660fc2, 0x7, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpordsd", 2, 0xf20fc2, 0x7, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpunordpd", 2, 0x660fc2, 0x3, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpunordsd", 2, 0xf20fc2, 0x3, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmppd", 3, 0x660fc2, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpsd", 0, 0xa7, None, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString, + 0, { 0 } }, { "cmpsd", 2, 0xa7, None, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, { "cmpsd", 3, 0xf20fc2, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "comisd", 2, 0x660f2f, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cvtpi2pd", 2, 0x660f2a, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegXMM } }, { "cvtsi2sd", 2, 0xf20f2a, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, + 0, { Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } }, { "divpd", 2, 0x660f5e, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "divsd", 2, 0xf20f5e, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "maxpd", 2, 0x660f5f, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "maxsd", 2, 0xf20f5f, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "minpd", 2, 0x660f5d, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "minsd", 2, 0xf20f5d, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "movapd", 2, 0x660f28, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "movapd", 2, 0x660f29, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } }, { "movhpd", 2, 0x660f16, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } }, { "movhpd", 2, 0x660f17, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "movlpd", 2, 0x660f12, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } }, { "movlpd", 2, 0x660f13, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "movmskpd", 2, 0x660f50, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, + 0, { RegXMM, Reg32|Reg64 } }, { "movntpd", 2, 0x660f2b, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "movsd", 0, 0xa5, None, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString, + 0, { 0 } }, { "movsd", 2, 0xa5, None, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg } }, { "movsd", 2, 0xf20f10, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "movsd", 2, 0xf20f11, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } }, { "movupd", 2, 0x660f10, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "movupd", 2, 0x660f11, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } }, { "mulpd", 2, 0x660f59, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "mulsd", 2, 0xf20f59, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "orpd", 2, 0x660f56, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "shufpd", 3, 0x660fc6, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "sqrtpd", 2, 0x660f51, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "sqrtsd", 2, 0xf20f51, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "subpd", 2, 0x660f5c, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "subsd", 2, 0xf20f5c, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "ucomisd", 2, 0x660f2e, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "unpckhpd", 2, 0x660f15, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "unpcklpd", 2, 0x660f14, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "xorpd", 2, 0x660f57, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cvtdq2pd", 2, 0xf30fe6, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cvtpd2dq", 2, 0xf20fe6, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cvtdq2ps", 2, 0xf5b, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cvtpd2pi", 2, 0x660f2d, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegMMX } }, { "cvtpd2ps", 2, 0x660f5a, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cvtps2pd", 2, 0xf5a, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cvtps2dq", 2, 0x660f5b, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cvtsd2si", 2, 0xf20f2d, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } }, { "cvtsd2ss", 2, 0xf20f5a, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cvtss2sd", 2, 0xf30f5a, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cvttpd2pi", 2, 0x660f2c, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegMMX } }, { "cvttsd2si", 2, 0xf20f2c, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, Reg32|Reg64 } }, { "cvttpd2dq", 2, 0x660fe6, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cvttps2dq", 2, 0xf30f5b, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "maskmovdqu", 2, 0x660ff7, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { RegXMM, RegXMM } }, { "movdqa", 2, 0x660f6f, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "movdqa", 2, 0x660f7f, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } }, { "movdqu", 2, 0xf30f6f, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "movdqu", 2, 0xf30f7f, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } }, { "movdq2q", 2, 0xf20fd6, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { RegXMM, RegMMX } }, { "movq2dq", 2, 0xf30fd6, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { RegMMX, RegXMM } }, { "pmuludq", 2, 0xff4, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pmuludq", 2, 0x660ff4, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pshufd", 3, 0x660f70, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pshufhw", 3, 0xf30f70, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pshuflw", 3, 0xf20f70, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pslldq", 2, 0x660f73, 0x7, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, RegXMM } }, { "psrldq", 2, 0x660f73, 0x3, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, RegXMM } }, { "punpckhqdq", 2, 0x660f6d, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "punpcklqdq", 2, 0x660f6c, None, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "addsubpd", 2, 0x660fd0, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "addsubps", 2, 0xf20fd0, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "cmpxchg16b", 1, 0xfc7, 0x1, CpuSSE3|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fisttp", 1, 0xdf, 0x1, CpuSSE3, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fisttp", 1, 0xdd, 0x1, CpuSSE3, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "fisttpll", 1, 0xdd, 0x1, CpuSSE3, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "haddpd", 2, 0x660f7c, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "haddps", 2, 0xf20f7c, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "hsubpd", 2, 0x660f7d, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "hsubps", 2, 0xf20f7d, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "lddqu", 2, 0xf20ff0, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } }, { "monitor", 0, 0xf01, 0xc8, CpuSSE3, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { 0 } }, { "monitor", 3, 0xf01, 0xc8, CpuSSE3|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { Reg16|Reg32, Reg32, Reg32 } }, { "monitor", 3, 0xf01, 0xc8, CpuSSE3|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64, + 0, { Reg32|Reg64, Reg64, Reg64 } }, { "movddup", 2, 0xf20f12, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "movshdup", 2, 0xf30f16, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "movsldup", 2, 0xf30f12, None, CpuSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "mwait", 0, 0xf01, 0xc9, CpuSSE3, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { 0 } }, { "mwait", 2, 0xf01, 0xc9, CpuSSE3|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { Reg32, Reg32 } }, { "mwait", 2, 0xf01, 0xc9, CpuSSE3|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64, + 0, { Reg64, Reg64 } }, { "vmcall", 0, 0xf01, 0xc1, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { 0 } }, { "vmclear", 1, 0x660fc7, 0x6, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "vmlaunch", 0, 0xf01, 0xc2, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { 0 } }, { "vmresume", 0, 0xf01, 0xc3, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { 0 } }, { "vmptrld", 1, 0xfc7, 0x6, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "vmptrst", 1, 0xfc7, 0x7, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "vmread", 2, 0xf78, None, CpuVMX|CpuNo64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg32, Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "vmread", 2, 0xf78, None, CpuVMX|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + 0, { Reg64, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "vmwrite", 2, 0xf79, None, CpuVMX|CpuNo64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } }, { "vmwrite", 2, 0xf79, None, CpuVMX|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|NoRex64, + 0, { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } }, { "vmxoff", 0, 0xf01, 0xc4, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { 0 } }, { "vmxon", 1, 0xf30fc7, 0x6, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "phaddw", 2, 0xf3801, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "phaddw", 2, 0x660f3801, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "phaddd", 2, 0xf3802, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "phaddd", 2, 0x660f3802, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "phaddsw", 2, 0xf3803, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "phaddsw", 2, 0x660f3803, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "phsubw", 2, 0xf3805, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "phsubw", 2, 0x660f3805, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "phsubd", 2, 0xf3806, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "phsubd", 2, 0x660f3806, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "phsubsw", 2, 0xf3807, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "phsubsw", 2, 0x660f3807, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmaddubsw", 2, 0xf3804, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pmaddubsw", 2, 0x660f3804, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmulhrsw", 2, 0xf380b, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pmulhrsw", 2, 0x660f380b, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pshufb", 2, 0xf3800, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pshufb", 2, 0x660f3800, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psignb", 2, 0xf3808, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psignb", 2, 0x660f3808, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psignw", 2, 0xf3809, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psignw", 2, 0x660f3809, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "psignd", 2, 0xf380a, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "psignd", 2, 0x660f380a, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "palignr", 3, 0xf3a0f, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "palignr", 3, 0x660f3a0f, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pabsb", 2, 0xf381c, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pabsb", 2, 0x660f381c, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pabsw", 2, 0xf381d, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pabsw", 2, 0x660f381d, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pabsd", 2, 0xf381e, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pabsd", 2, 0x660f381e, None, CpuSSSE3, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "blendpd", 3, 0x660f3a0d, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "blendps", 3, 0x660f3a0c, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "blendvpd", 3, 0x660f3815, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|RegKludge, + 0, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "blendvps", 3, 0x660f3814, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|RegKludge, + 0, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "dppd", 3, 0x660f3a41, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "dpps", 3, 0x660f3a40, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "extractps", 3, 0x660f3a17, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, RegXMM, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "insertps", 3, 0x660f3a21, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "movntdqa", 2, 0x660f382a, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } }, { "mpsadbw", 3, 0x660f3a42, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "packusdw", 2, 0x660f382b, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pblendvb", 3, 0x660f3810, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|RegKludge, + 0, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pblendw", 3, 0x660f3a0e, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pcmpeqq", 2, 0x660f3829, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pextrb", 3, 0x660f3a14, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, RegXMM, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "pextrd", 3, 0x660f3a16, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, RegXMM, Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "pextrq", 3, 0x660f3a16, None, CpuSSE4_1|Cpu64, Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, RegXMM, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "phminposuw", 2, 0x660f3841, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pinsrb", 3, 0x660f3a20, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } }, { "pinsrd", 3, 0x660f3a22, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } }, { "pinsrq", 3, 0x660f3a22, None, CpuSSE4_1|Cpu64, Modrm|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } }, { "pmaxsb", 2, 0x660f383c, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmaxsd", 2, 0x660f383d, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmaxud", 2, 0x660f383f, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmaxuw", 2, 0x660f383e, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pminsb", 2, 0x660f3838, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pminsd", 2, 0x660f3839, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pminud", 2, 0x660f383b, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pminuw", 2, 0x660f383a, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovsxbw", 2, 0x660f3820, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovsxbd", 2, 0x660f3821, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovsxbq", 2, 0x660f3822, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovsxwd", 2, 0x660f3823, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovsxwq", 2, 0x660f3824, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovsxdq", 2, 0x660f3825, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovzxbw", 2, 0x660f3830, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovzxbd", 2, 0x660f3831, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovzxbq", 2, 0x660f3832, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovzxwd", 2, 0x660f3833, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovzxwq", 2, 0x660f3834, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovzxdq", 2, 0x660f3835, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmuldq", 2, 0x660f3828, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmulld", 2, 0x660f3840, None, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, ! { "ptest", 2, 0x660f3817, None, CpuSSE4_1|CpuSSE5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, ! { "roundpd", 3, 0x660f3a09, None, CpuSSE4_1|CpuSSE5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, ! { "roundps", 3, 0x660f3a08, None, CpuSSE4_1|CpuSSE5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, ! { "roundsd", 3, 0x660f3a0b, None, CpuSSE4_1|CpuSSE5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, + 0, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, ! { "roundss", 3, 0x660f3a0a, None, CpuSSE4_1|CpuSSE5, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pcmpgtq", 2, 0x660f3837, None, CpuSSE4_2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pcmpestri", 3, 0x660f3a61, None, CpuSSE4_2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pcmpestrm", 3, 0x660f3a60, None, CpuSSE4_2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pcmpistri", 3, 0x660f3a63, None, CpuSSE4_2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pcmpistrm", 3, 0x660f3a62, None, CpuSSE4_2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "crc32", 2, 0xf20f38f1, None, CpuSSE4_2, Modrm|No_bSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg16|Reg32|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } }, { "crc32", 2, 0xf20f38f1, None, CpuSSE4_2|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|Rex64, + 0, { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } }, { "crc32", 2, 0xf20f38f0, None, CpuSSE4_2, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } }, { "crc32", 2, 0xf20f38f0, None, CpuSSE4_2|Cpu64, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|Rex64, + 0, { Reg8|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } }, { "prefetch", 1, 0xf0d, 0x0, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "prefetchw", 1, 0xf0d, 0x1, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "femms", 0, 0xf0e, None, Cpu3dnow, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "pavgusb", 2, 0xf0f, 0xbf, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pf2id", 2, 0xf0f, 0x1d, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pf2iw", 2, 0xf0f, 0x1c, Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfacc", 2, 0xf0f, 0xae, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfadd", 2, 0xf0f, 0x9e, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfcmpeq", 2, 0xf0f, 0xb0, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfcmpge", 2, 0xf0f, 0x90, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfcmpgt", 2, 0xf0f, 0xa0, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfmax", 2, 0xf0f, 0xa4, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfmin", 2, 0xf0f, 0x94, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfmul", 2, 0xf0f, 0xb4, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfnacc", 2, 0xf0f, 0x8a, Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfpnacc", 2, 0xf0f, 0x8e, Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfrcp", 2, 0xf0f, 0x96, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfrcpit1", 2, 0xf0f, 0xa6, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfrcpit2", 2, 0xf0f, 0xb6, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfrsqit1", 2, 0xf0f, 0xa7, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfrsqrt", 2, 0xf0f, 0x97, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfsub", 2, 0xf0f, 0x9a, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pfsubr", 2, 0xf0f, 0xaa, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pi2fd", 2, 0xf0f, 0xd, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pi2fw", 2, 0xf0f, 0xc, Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pmulhrw", 2, 0xf0f, 0xb7, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "pswapd", 2, 0xf0f, 0xbb, Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } }, { "syscall", 0, 0xf05, None, CpuK6, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { 0 } }, { "sysret", 0, 0xf07, None, CpuK6, DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_xSuf, + 0, { 0 } }, { "swapgs", 0, 0xf01, 0xf8, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { 0 } }, { "rdtscp", 0, 0xf01, 0xf9, CpuSledgehammer, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { 0 } }, { "clgi", 0, 0xf01, 0xdd, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { 0 } }, { "invlpga", 0, 0xf01, 0xdf, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { 0 } }, { "invlpga", 2, 0xf01, 0xdf, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } }, { "skinit", 0, 0xf01, 0xde, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { 0 } }, { "skinit", 1, 0xf01, 0xde, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "stgi", 0, 0xf01, 0xdc, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { 0 } }, { "vmload", 0, 0xf01, 0xda, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { 0 } }, { "vmload", 1, 0xf01, 0xda, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "vmmcall", 0, 0xf01, 0xd9, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { 0 } }, { "vmrun", 0, 0xf01, 0xd8, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { 0 } }, { "vmrun", 1, 0xf01, 0xd8, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "vmsave", 0, 0xf01, 0xdb, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { 0 } }, { "vmsave", 1, 0xf01, 0xdb, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, + 0, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "movntsd", 2, 0xf20f2b, None, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "movntss", 2, 0xf30f2b, None, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, { "extrq", 3, 0x660f78, 0x0, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, Imm8, RegXMM } }, { "extrq", 2, 0x660f79, None, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { RegXMM, RegXMM } }, { "insertq", 2, 0xf20f79, None, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { RegXMM, RegXMM } }, { "insertq", 4, 0xf20f78, None, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + 0, { Imm8, Imm8, RegXMM, RegXMM } }, { "popcnt", 2, 0xf30fb8, None, CpuABM|CpuSSE4_2, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, { "lzcnt", 2, 0xf30fbd, None, CpuABM, Modrm|No_bSuf|No_sSuf|No_xSuf, + 0, { Reg16|Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 } }, + { "fmaddps", 4, 0x0f2400, None, CpuSSE5, + Sse5Common1, + Drex|Drexv, + { RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM } }, + { "fmaddpd", 4, 0x0f2401, None, CpuSSE5, + Sse5Common1, + Drex|Drexv, + { RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM } }, + { "fmaddss", 4, 0x0f2402, None, CpuSSE5, + Sse5Common1, + Drex|Drexv, + { RegXMM|LongMem, + RegXMM|LongMem, + RegXMM|LongMem, + RegXMM } }, + { "fmaddsd", 4, 0x0f2403, None, CpuSSE5, + Sse5Common1, + Drex|Drexv, + { RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM } }, + { "fmsubps", 4, 0x0f2408, None, CpuSSE5, + Sse5Common1, + Drex|Drexv, + { RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM } }, + { "fmsubpd", 4, 0x0f2409, None, CpuSSE5, + Sse5Common1, + Drex|Drexv, + { RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM } }, + { "fmsubss", 4, 0x0f240a, None, CpuSSE5, + Sse5Common1, + Drex|Drexv, + { RegXMM|LongMem, + RegXMM|LongMem, + RegXMM|LongMem, + RegXMM } }, + { "fmsubsd", 4, 0x0f240b, None, CpuSSE5, + Sse5Common1, + Drex|Drexv, + { RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM } }, + { "fnmaddps", 4, 0x0f2410, None, CpuSSE5, + Sse5Common1, + Drex|Drexv, + { RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM } }, + { "fnmaddpd", 4, 0x0f2411, None, CpuSSE5, + Sse5Common1, + Drex|Drexv, + { RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM } }, + { "fnmaddss", 4, 0x0f2412, None, CpuSSE5, + Sse5Common1, + Drex|Drexv, + { RegXMM|LongMem, + RegXMM|LongMem, + RegXMM|LongMem, + RegXMM } }, + { "fnmaddsd", 4, 0x0f2413, None, CpuSSE5, + Sse5Common1, + Drex|Drexv, + { RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM } }, + { "fnmsubps", 4, 0x0f2418, None, CpuSSE5, + Sse5Common1, + Drex|Drexv, + { RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM } }, + { "fnmsubpd", 4, 0x0f2419, None, CpuSSE5, + Sse5Common1, + Drex|Drexv, + { RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM } }, + { "fnmsubss", 4, 0x0f241a, None, CpuSSE5, + Sse5Common1, + Drex|Drexv, + { RegXMM|LongMem, + RegXMM|LongMem, + RegXMM|LongMem, + RegXMM } }, + { "fnmsubsd", 4, 0x0f241b, None, CpuSSE5, + Sse5Common1, + Drex|Drexv, + { RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM } }, + { "pmacssww", 4, 0x0f2485, 0x0, CpuSSE5, + Sse5Common1, + Drex, + { RegXMM, + RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pmacsww", 4, 0x0f2495, 0x0, CpuSSE5, + Sse5Common1, + Drex, + { RegXMM, + RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pmacsswd", 4, 0x0f2486, 0x0, CpuSSE5, + Sse5Common1, + Drex, + { RegXMM, + RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pmacswd", 4, 0x0f2496, 0x0, CpuSSE5, + Sse5Common1, + Drex, + { RegXMM, + RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pmacssdd", 4, 0x0f248e, 0x0, CpuSSE5, + Sse5Common1, + Drex, + { RegXMM, + RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pmacsdd", 4, 0x0f249e, 0x0, CpuSSE5, + Sse5Common1, + Drex, + { RegXMM, + RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pmacssdql", 4, 0x0f2487, 0x0, CpuSSE5, + Sse5Common1, + Drex, + { RegXMM, + RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pmacssdqh", 4, 0x0f248f, 0x0, CpuSSE5, + Sse5Common1, + Drex, + { RegXMM, + RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pmacsdql", 4, 0x0f2497, 0x0, CpuSSE5, + Sse5Common1, + Drex, + { RegXMM, + RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pmacsdqh", 4, 0x0f249f, 0x0, CpuSSE5, + Sse5Common1, + Drex, + { RegXMM, + RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pmadcsswd", 4, 0x0f24a6, 0x0, CpuSSE5, + Sse5Common1, + Drex, + { RegXMM, + RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pmadcswd", 4, 0x0f24b6, 0x0, CpuSSE5, + Sse5Common1, + Drex, + { RegXMM, + RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "phaddbw", 2, 0x0f7a41, None, CpuSSE5, + Sse5Common1, + 0, + { RegXMM|LLongMem, + RegXMM } }, + { "phaddbd", 2, 0x0f7a42, None, CpuSSE5, + Sse5Common1, + 0, + { RegXMM|LLongMem, + RegXMM } }, + { "phaddbq", 2, 0x0f7a43, None, CpuSSE5, + Sse5Common1, + 0, + { RegXMM|LLongMem, + RegXMM } }, + { "phaddwd", 2, 0x0f7a46, None, CpuSSE5, + Sse5Common1, + 0, + { RegXMM|LLongMem, + RegXMM } }, + { "phaddwq", 2, 0x0f7a47, None, CpuSSE5, + Sse5Common1, + 0, + { RegXMM|LLongMem, + RegXMM } }, + { "phadddq", 2, 0x0f7a4b, None, CpuSSE5, + Sse5Common1, + 0, + { RegXMM|LLongMem, + RegXMM } }, + { "phaddubw", 2, 0x0f7a51, None, CpuSSE5, + Sse5Common1, + 0, + { RegXMM|LLongMem, + RegXMM } }, + { "phaddubd", 2, 0x0f7a52, None, CpuSSE5, + Sse5Common1, + 0, + { RegXMM|LLongMem, + RegXMM } }, + { "phaddubq", 2, 0x0f7a53, None, CpuSSE5, + Sse5Common1, + 0, + { RegXMM|LLongMem, + RegXMM } }, + { "phadduwd", 2, 0x0f7a56, None, CpuSSE5, + Sse5Common1, + 0, + { RegXMM|LLongMem, + RegXMM } }, + { "phadduwq", 2, 0x0f7a57, None, CpuSSE5, + Sse5Common1, + 0, + { RegXMM|LLongMem, + RegXMM } }, + { "phaddudq", 2, 0x0f7a5b, None, CpuSSE5, + Sse5Common1, + 0, + { RegXMM|LLongMem, + RegXMM } }, + { "phsubbw", 2, 0x0f7a61, None, CpuSSE5, + Sse5Common1, + 0, + { RegXMM|LLongMem, + RegXMM } }, + { "phsubwd", 2, 0x0f7a62, None, CpuSSE5, + Sse5Common1, + 0, + { RegXMM|LLongMem, + RegXMM } }, + { "phsubdq", 2, 0x0f7a63, None, CpuSSE5, + Sse5Common1, + 0, + { RegXMM|LLongMem, + RegXMM } }, + { "pcmov", 4, 0x0f2422, None, CpuSSE5, + Sse5Common1, + Drex|Drexv, + { RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM } }, + { "pperm", 4, 0x0f2423, None, CpuSSE5, + Sse5Common1, + Drex|Drexv, + { RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM } }, + { "permps", 4, 0x0f2420, None, CpuSSE5, + Sse5Common1, + Drex|Drexv, + { RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM } }, + { "permpd", 4, 0x0f2421, None, CpuSSE5, + Sse5Common1, + Drex|Drexv, + { RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM } }, + { "protb", 3, 0x0f2440, None, CpuSSE5, + Sse5Common1, + Drex|Drexv, + { RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM } }, + { "protb", 3, 0x0f7b40, 0x0, CpuSSE5, + Sse5Common1, + 0, + { Imm8, + RegXMM, + RegXMM } }, + { "protw", 3, 0x0f2441, None, CpuSSE5, + Sse5Common1, + Drex|Drexv, + { RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM } }, + { "protw", 3, 0x0f7b41, 0x0, CpuSSE5, + Sse5Common1, + 0, + { Imm8, + RegXMM, + RegXMM } }, + { "protd", 3, 0x0f2442, None, CpuSSE5, + Sse5Common1, + Drex|Drexv, + { RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM } }, + { "protd", 3, 0x0f7b42, 0x0, CpuSSE5, + Sse5Common1, + 0, + { Imm8, + RegXMM, + RegXMM } }, + { "protq", 3, 0x0f2443, None, CpuSSE5, + Sse5Common1, + Drex|Drexv, + { RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM } }, + { "protq", 3, 0x0f7b43, 0x0, CpuSSE5, + Sse5Common1, + 0, + { Imm8, + RegXMM, + RegXMM } }, + { "pshlb", 3, 0x0f2444, None, CpuSSE5, + Sse5Common1, + Drex|Drexv, + { RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM } }, + { "pshlw", 3, 0x0f2445, None, CpuSSE5, + Sse5Common1, + Drex|Drexv, + { RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM } }, + { "pshld", 3, 0x0f2446, None, CpuSSE5, + Sse5Common1, + Drex|Drexv, + { RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM } }, + { "pshlq", 3, 0x0f2447, None, CpuSSE5, + Sse5Common1, + Drex|Drexv, + { RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM } }, + { "pshab", 3, 0x0f2448, 0x0, CpuSSE5, + Sse5Common1, + Drex|Drexv, + { RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM } }, + { "pshaw", 3, 0x0f2449, 0x0, CpuSSE5, + Sse5Common1, + Drex|Drexv, + { RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM } }, + { "pshad", 3, 0x0f244a, 0x0, CpuSSE5, + Sse5Common1, + Drex|Drexv, + { RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM } }, + { "pshaq", 3, 0x0f244b, 0x0, CpuSSE5, + Sse5Common1, + Drex|Drexv, + { RegXMM|LLongMem, + RegXMM|LLongMem, + RegXMM } }, + { "comps", 4, 0x0f252c, 0x0, CpuSSE5, + Sse5Common2, + Drexc, + { Imm8, + RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comeqps", 3, 0x0f252c, 0x0, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comltps", 3, 0x0f252c, 0x1, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comungeps", 3, 0x0f252c, 0x1, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comleps", 3, 0x0f252c, 0x2, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comungtps", 3, 0x0f252c, 0x2, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comunordps", 3, 0x0f252c, 0x3, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comneps", 3, 0x0f252c, 0x4, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comneqps", 3, 0x0f252c, 0x4, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comnltps", 3, 0x0f252c, 0x5, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comugeps", 3, 0x0f252c, 0x5, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comnleps", 3, 0x0f252c, 0x6, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comugtps", 3, 0x0f252c, 0x6, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comordps", 3, 0x0f252c, 0x7, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comueqps", 3, 0x0f252c, 0x8, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comultps", 3, 0x0f252c, 0x9, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comngeps", 3, 0x0f252c, 0x9, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comuleps", 3, 0x0f252c, 0xa, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comngtps", 3, 0x0f252c, 0xa, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comfalseps", 3, 0x0f252c, 0xb, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comuneps", 3, 0x0f252c, 0xc, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comuneqps", 3, 0x0f252c, 0xc, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comunltps", 3, 0x0f252c, 0xd, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comgeps", 3, 0x0f252c, 0xd, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comunleps", 3, 0x0f252c, 0xe, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comgtps", 3, 0x0f252c, 0xe, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comtrueps", 3, 0x0f252c, 0xf, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "compd", 4, 0x0f252d, 0x0, CpuSSE5, + Sse5Common2, + Drexc, + { Imm8, + RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comeqpd", 3, 0x0f252d, 0x0, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comltpd", 3, 0x0f252d, 0x1, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comungepd", 3, 0x0f252d, 0x1, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comlepd", 3, 0x0f252d, 0x2, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comungtpd", 3, 0x0f252d, 0x2, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comunordpd", 3, 0x0f252d, 0x3, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comnepd", 3, 0x0f252d, 0x4, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comneqpd", 3, 0x0f252d, 0x4, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comnltpd", 3, 0x0f252d, 0x5, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comugepd", 3, 0x0f252d, 0x5, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comnlepd", 3, 0x0f252d, 0x6, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comugtpd", 3, 0x0f252d, 0x6, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comordpd", 3, 0x0f252d, 0x7, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comueqpd", 3, 0x0f252d, 0x8, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comultpd", 3, 0x0f252d, 0x9, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comngepd", 3, 0x0f252d, 0x9, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comulepd", 3, 0x0f252d, 0xa, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comngtpd", 3, 0x0f252d, 0xa, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comfalsepd", 3, 0x0f252d, 0xb, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comunepd", 3, 0x0f252d, 0xc, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comuneqpd", 3, 0x0f252d, 0xc, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comunltpd", 3, 0x0f252d, 0xd, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comgepd", 3, 0x0f252d, 0xd, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comunlepd", 3, 0x0f252d, 0xe, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comgtpd", 3, 0x0f252d, 0xe, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comtruepd", 3, 0x0f252d, 0xf, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comss", 4, 0x0f252e, 0x0, CpuSSE5, + Sse5Common2, + Drexc, + { Imm8, + RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comeqss", 3, 0x0f252e, 0x0, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comltss", 3, 0x0f252e, 0x1, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comungess", 3, 0x0f252e, 0x1, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comless", 3, 0x0f252e, 0x2, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comungtss", 3, 0x0f252e, 0x2, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comunordss", 3, 0x0f252e, 0x3, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comness", 3, 0x0f252e, 0x4, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comneqss", 3, 0x0f252e, 0x4, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comnltss", 3, 0x0f252e, 0x5, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comugess", 3, 0x0f252e, 0x5, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comnless", 3, 0x0f252e, 0x6, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comugtss", 3, 0x0f252e, 0x6, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comordss", 3, 0x0f252e, 0x7, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comueqss", 3, 0x0f252e, 0x8, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comultss", 3, 0x0f252e, 0x9, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comngess", 3, 0x0f252e, 0x9, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comuless", 3, 0x0f252e, 0xa, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comngtss", 3, 0x0f252e, 0xa, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comfalsess", 3, 0x0f252e, 0xb, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comuness", 3, 0x0f252e, 0xc, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comuneqss", 3, 0x0f252e, 0xc, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comunltss", 3, 0x0f252e, 0xd, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comgess", 3, 0x0f252e, 0xd, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comunless", 3, 0x0f252e, 0xe, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comgtss", 3, 0x0f252e, 0xe, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comtruess", 3, 0x0f252e, 0xf, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comsd", 4, 0x0f252f, 0x0, CpuSSE5, + Sse5Common2, + Drexc, + { Imm8, + RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comeqsd", 3, 0x0f252f, 0x0, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comltsd", 3, 0x0f252f, 0x1, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comungesd", 3, 0x0f252f, 0x1, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comlesd", 3, 0x0f252f, 0x2, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comungtsd", 3, 0x0f252f, 0x2, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comunordsd", 3, 0x0f252f, 0x3, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comnesd", 3, 0x0f252f, 0x4, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comneqsd", 3, 0x0f252f, 0x4, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comnltsd", 3, 0x0f252f, 0x5, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comugesd", 3, 0x0f252f, 0x5, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comnlesd", 3, 0x0f252f, 0x6, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comugtsd", 3, 0x0f252f, 0x6, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comordsd", 3, 0x0f252f, 0x7, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comueqsd", 3, 0x0f252f, 0x8, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comultsd", 3, 0x0f252f, 0x9, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comngesd", 3, 0x0f252f, 0x9, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comulesd", 3, 0x0f252f, 0xa, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comngtsd", 3, 0x0f252f, 0xa, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comfalsesd", 3, 0x0f252f, 0xb, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comunesd", 3, 0x0f252f, 0xc, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comuneqsd", 3, 0x0f252f, 0xc, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comunltsd", 3, 0x0f252f, 0xd, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comgesd", 3, 0x0f252f, 0xd, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comunlesd", 3, 0x0f252f, 0xe, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comgtsd", 3, 0x0f252f, 0xe, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "comtruesd", 3, 0x0f252f, 0xf, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomub", 4, 0x0f256c, 0x0, CpuSSE5, + Sse5Common2, + Drexc, + { Imm8, + RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomltub", 3, 0x0f256c, 0x0, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomleub", 3, 0x0f256c, 0x1, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomgtub", 3, 0x0f256c, 0x2, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomgeub", 3, 0x0f256c, 0x3, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomequb", 3, 0x0f256c, 0x4, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomnequb", 3, 0x0f256c, 0x5, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomneub", 3, 0x0f256c, 0x5, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomfalseub", 3, 0x0f256c, 0x6, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomtrueub", 3, 0x0f256c, 0x7, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomuw", 4, 0x0f256d, 0x0, CpuSSE5, + Sse5Common2, + Drexc, + { Imm8, + RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomltuw", 3, 0x0f256d, 0x0, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomleuw", 3, 0x0f256d, 0x1, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomgtuw", 3, 0x0f256d, 0x2, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomgeuw", 3, 0x0f256d, 0x3, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomequw", 3, 0x0f256d, 0x4, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomnequw", 3, 0x0f256d, 0x5, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomneuw", 3, 0x0f256d, 0x5, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomfalseuw", 3, 0x0f256d, 0x6, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomtrueuw", 3, 0x0f256d, 0x7, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomud", 4, 0x0f256e, 0x0, CpuSSE5, + Sse5Common2, + Drexc, + { Imm8, + RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomltud", 3, 0x0f256e, 0x0, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomleud", 3, 0x0f256e, 0x1, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomgtud", 3, 0x0f256e, 0x2, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomgeud", 3, 0x0f256e, 0x3, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomequd", 3, 0x0f256e, 0x4, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomnequd", 3, 0x0f256e, 0x5, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomneud", 3, 0x0f256e, 0x5, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomfalseud", 3, 0x0f256e, 0x6, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomtrueud", 3, 0x0f256e, 0x7, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomuq", 4, 0x0f256f, 0x0, CpuSSE5, + Sse5Common2, + Drexc, + { Imm8, + RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomltuq", 3, 0x0f256f, 0x0, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomleuq", 3, 0x0f256f, 0x1, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomgtuq", 3, 0x0f256f, 0x2, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomgeuq", 3, 0x0f256f, 0x3, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomequq", 3, 0x0f256f, 0x4, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomnequq", 3, 0x0f256f, 0x5, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomneuq", 3, 0x0f256f, 0x5, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomfalseuq", 3, 0x0f256f, 0x6, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomtrueuq", 3, 0x0f256f, 0x7, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomb", 4, 0x0f254c, 0x0, CpuSSE5, + Sse5Common2, + Drexc, + { Imm8, + RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomltb", 3, 0x0f254c, 0x0, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomleb", 3, 0x0f254c, 0x1, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomgtb", 3, 0x0f254c, 0x2, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomgeb", 3, 0x0f254c, 0x3, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomeqb", 3, 0x0f254c, 0x4, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomneqb", 3, 0x0f254c, 0x5, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomneb", 3, 0x0f254c, 0x5, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomfalseb", 3, 0x0f254c, 0x6, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomtrueb", 3, 0x0f254c, 0x7, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomw", 4, 0x0f254d, 0x0, CpuSSE5, + Sse5Common2, + Drexc, + { Imm8, + RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomltw", 3, 0x0f254d, 0x0, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomlew", 3, 0x0f254d, 0x1, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomgtw", 3, 0x0f254d, 0x2, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomgew", 3, 0x0f254d, 0x3, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomeqw", 3, 0x0f254d, 0x4, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomneqw", 3, 0x0f254d, 0x5, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomnew", 3, 0x0f254d, 0x5, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomfalsew", 3, 0x0f254d, 0x6, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomtruew", 3, 0x0f254d, 0x7, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomd", 4, 0x0f254e, 0x0, CpuSSE5, + Sse5Common2, + Drexc, + { Imm8, + RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomltd", 3, 0x0f254e, 0x0, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomled", 3, 0x0f254e, 0x1, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomgtd", 3, 0x0f254e, 0x2, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomged", 3, 0x0f254e, 0x3, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomeqd", 3, 0x0f254e, 0x4, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomneqd", 3, 0x0f254e, 0x5, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomned", 3, 0x0f254e, 0x5, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomfalsed", 3, 0x0f254e, 0x6, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomtrued", 3, 0x0f254e, 0x7, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomq", 4, 0x0f254f, 0x0, CpuSSE5, + Sse5Common2, + Drexc, + { Imm8, + RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomltq", 3, 0x0f254f, 0x0, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomleq", 3, 0x0f254f, 0x1, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomgtq", 3, 0x0f254f, 0x2, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomgeq", 3, 0x0f254f, 0x3, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomeqq", 3, 0x0f254f, 0x4, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomneqq", 3, 0x0f254f, 0x5, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomneq", 3, 0x0f254f, 0x5, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomfalseq", 3, 0x0f254f, 0x6, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "pcomtrueq", 3, 0x0f254f, 0x7, CpuSSE5, + Sse5Common2|ImmExt, + Drexc, + { RegXMM|LLongMem, + RegXMM, + RegXMM } }, + { "frczps", 2, 0x0f7a10, None, CpuSSE5, + Sse5Common2, + 0, + { RegXMM|LLongMem, + RegXMM } }, + { "frczpd", 2, 0x0f7a11, None, CpuSSE5, + Sse5Common2, + 0, + { RegXMM|LLongMem, + RegXMM } }, + { "frczss", 2, 0x0f7a12, None, CpuSSE5, + Sse5Common2, + 0, + { RegXMM|LongMem, + RegXMM } }, + { "frczsd", 2, 0x0f7a13, None, CpuSSE5, + Sse5Common2, + 0, + { RegXMM|LLongMem, + RegXMM } }, + { "cvtph2ps", 2, 0x0f7a30, None, CpuSSE5, + Sse5Common1, + 0, + { RegXMM|LongMem, + RegXMM } }, + { "cvtps2ph", 2, 0x0f7a31, None, CpuSSE5, + Sse5Common1, + 0, + { RegXMM, + RegXMM|LongMem } }, { "xstore-rng", 0, 0xfa7, 0xc0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, + 0, { 0 } }, { "xcrypt-ecb", 0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, + 0, { 0 } }, { "xcrypt-cbc", 0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, + 0, { 0 } }, { "xcrypt-ctr", 0, 0xf30fa7, 0xd8, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, + 0, { 0 } }, { "xcrypt-cfb", 0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, + 0, { 0 } }, { "xcrypt-ofb", 0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, + 0, { 0 } }, { "montmul", 0, 0xf30fa6, 0xc0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, + 0, { 0 } }, { "xsha1", 0, 0xf30fa6, 0xc8, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, + 0, { 0 } }, { "xsha256", 0, 0xf30fa6, 0xd0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, + 0, { 0 } }, { "xstorerng", 0, 0xfa7, 0xc0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, + 0, { 0 } }, { "xcryptecb", 0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, + 0, { 0 } }, { "xcryptcbc", 0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, + 0, { 0 } }, { "xcryptctr", 0, 0xf30fa7, 0xd8, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, + 0, { 0 } }, { "xcryptcfb", 0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, + 0, { 0 } }, { "xcryptofb", 0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, + 0, { 0 } }, { "xstore", 0, 0xfa7, 0xc0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, + 0, { 0 } }, ! { NULL, 0, 0, 0, 0, 0, 0, { 0 } } }; /* i386 register table. */ *** opcodes/i386-dis.c.~1~ 2007-08-31 11:40:01.877246000 -0400 --- opcodes/i386-dis.c 2007-08-31 10:34:59.967782000 -0400 *************** *** 37,42 **** --- 37,43 ---- #include "sysdep.h" #include "opintl.h" #include "opcode/i386.h" + #include "libiberty.h" #include *************** static void oappend (const char *); *** 52,57 **** --- 53,59 ---- static void append_seg (void); static void OP_indirE (int, int); static void print_operand_value (char *, int, bfd_vma); + static void OP_E_extended (int, int, int); static void print_displacement (char *, bfd_vma); static void OP_E (int, int); static void OP_G (int, int); *************** static void REP_Fixup (int, int); *** 100,105 **** --- 102,112 ---- static void CMPXCHG8B_Fixup (int, int); static void XMM_Fixup (int, int); static void CRC32_Fixup (int, int); + static void print_drex_arg (unsigned int, int, int); + static void OP_DREX4 (int, int); + static void OP_DREX3 (int, int); + static void OP_DREX_ICMP (int, int); + static void OP_DREX_FCMP (int, int); struct dis_private { /* Points to first byte not fetched. */ *************** static int rex_used; *** 141,146 **** --- 148,167 ---- rex_used |= REX_OPCODE; \ } + /* Special 'registers' for DREX handling */ + #define DREX_REG_UNKNOWN 1000 /* not initialized */ + #define DREX_REG_MEMORY 1001 /* use MODRM/SIB/OFFSET memory */ + + /* The DREX byte has the following fields: + Bits 7-4 -- DREX.Dest, xmm destination register + Bit 3 -- DREX.OC0, operand config bit defines operand order + Bit 2 -- DREX.R, equivalent to REX_R bit, to extend ModRM register + Bit 1 -- DREX.X, equivalent to REX_X bit, to extend SIB index field + Bit 0 -- DREX.W, equivalent to REX_B bit, to extend ModRM r/m field, + SIB base field, or opcode reg field. */ + #define DREX_XMM(drex) ((drex >> 4) & 0xf) + #define DREX_OC0(drex) ((drex >> 3) & 0x1) + /* Flags for prefixes which we somehow handled when printing the current instruction. */ static int used_prefixes; *************** fetch_data (struct disassemble_info *inf *** 361,366 **** --- 382,392 ---- #define dqb_mode 18 /* registers like dq_mode, memory like b_mode. */ #define dqd_mode 19 /* registers like dq_mode, memory like d_mode. */ + /* Flags that are OR'ed into the bytemode field to pass extra information. */ + #define DREX_OC1 0x4000 /* OC1 bit set */ + #define DREX_NO_OC0 0x2000 /* OC0 bit not used */ + #define DREX_MASK 0x6000 /* mask to delete */ + #define es_reg 100 #define cs_reg 101 #define ss_reg 102 *************** fetch_data (struct disassemble_info *inf *** 554,561 **** #define X86_64_2 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 2 } } #define X86_64_3 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 3 } } ! #define THREE_BYTE_0 NULL, { { NULL, IS_3BYTE_OPCODE }, { NULL, 0 } } ! #define THREE_BYTE_1 NULL, { { NULL, IS_3BYTE_OPCODE }, { NULL, 1 } } #define OPC_EXT_0 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 0 } } #define OPC_EXT_1 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 1 } } --- 580,591 ---- #define X86_64_2 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 2 } } #define X86_64_3 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 3 } } ! #define THREE_BYTE_0 NULL, { { NULL, IS_3BYTE_OPCODE }, { NULL, 0 } } ! #define THREE_BYTE_1 NULL, { { NULL, IS_3BYTE_OPCODE }, { NULL, 1 } } ! #define THREE_BYTE_SSE5_0F24 NULL, { { NULL, IS_3BYTE_OPCODE }, { NULL, 2 } } ! #define THREE_BYTE_SSE5_0F25 NULL, { { NULL, IS_3BYTE_OPCODE }, { NULL, 3 } } ! #define THREE_BYTE_SSE5_0F7A NULL, { { NULL, IS_3BYTE_OPCODE }, { NULL, 4 } } ! #define THREE_BYTE_SSE5_0F7B NULL, { { NULL, IS_3BYTE_OPCODE }, { NULL, 5 } } #define OPC_EXT_0 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 0 } } #define OPC_EXT_1 NULL, { { NULL, USE_OPC_EXT_TABLE }, { NULL, 1 } } *************** static const struct dis386 dis386[] = { *** 947,952 **** --- 977,987 ---- { GRP5 }, }; + /* SSE5 0f 24 instructions overlap with the 386 mov test instructions. */ + static const struct dis386 dis386_move_test = { + "movL", { Rd, Td } + }; + static const struct dis386 dis386_twobyte[] = { /* 00 */ { GRP6 }, *************** static const struct dis386 dis386_twobyt *** 989,996 **** { "movZ", { Rm, Dm } }, { "movZ", { Cm, Rm } }, { "movZ", { Dm, Rm } }, ! { "movL", { Rd, Td } }, ! { "(bad)", { XX } }, { "movL", { Td, Rd } }, { "(bad)", { XX } }, /* 28 */ --- 1024,1031 ---- { "movZ", { Rm, Dm } }, { "movZ", { Cm, Rm } }, { "movZ", { Dm, Rm } }, ! { THREE_BYTE_SSE5_0F24 }, /* also movL {Td, Rd} in 386/486 */ ! { THREE_BYTE_SSE5_0F25 }, { "movL", { Td, Rd } }, { "(bad)", { XX } }, /* 28 */ *************** static const struct dis386 dis386_twobyt *** 1086,1093 **** /* 78 */ { PREGRP34 }, { PREGRP35 }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, { PREGRP28 }, { PREGRP29 }, { PREGRP23 }, --- 1121,1128 ---- /* 78 */ { PREGRP34 }, { PREGRP35 }, ! { THREE_BYTE_SSE5_0F7A }, ! { THREE_BYTE_SSE5_0F7B }, { PREGRP28 }, { PREGRP29 }, { PREGRP23 }, *************** static const unsigned char twobyte_has_m *** 1266,1277 **** /* ------------------------------- */ /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ /* 10 */ 1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,1, /* 1f */ ! /* 20 */ 1,1,1,1,1,0,1,0,1,1,1,1,1,1,1,1, /* 2f */ /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ ! /* 70 */ 1,1,1,1,1,1,1,0,1,1,0,0,1,1,1,1, /* 7f */ /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ --- 1301,1312 ---- /* ------------------------------- */ /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ /* 10 */ 1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,1, /* 1f */ ! /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ ! /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ *************** static const struct dis386 three_byte_ta *** 2997,3064 **** { "(bad)", { XX } }, { "(bad)", { XX } }, /* c8 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, /* d0 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, /* d8 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, /* e0 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, /* e8 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, /* f0 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, /* f8 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, } }; --- 3032,4263 ---- { "(bad)", { XX } }, { "(bad)", { XX } }, /* c8 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* d0 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* d8 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* e0 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* e8 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* f0 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* f8 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! }, ! /* THREE_BYTE_SSE5_0F24 */ ! { ! /* 00 */ ! { "fmaddps", { { OP_DREX4, q_mode } } }, ! { "fmaddpd", { { OP_DREX4, q_mode } } }, ! { "fmaddss", { { OP_DREX4, w_mode } } }, ! { "fmaddsd", { { OP_DREX4, d_mode } } }, ! { "fmaddps", { { OP_DREX4, DREX_OC1 + q_mode } } }, ! { "fmaddpd", { { OP_DREX4, DREX_OC1 + q_mode } } }, ! { "fmaddss", { { OP_DREX4, DREX_OC1 + w_mode } } }, ! { "fmaddsd", { { OP_DREX4, DREX_OC1 + d_mode } } }, ! /* 08 */ ! { "fmsubps", { { OP_DREX4, q_mode } } }, ! { "fmsubpd", { { OP_DREX4, q_mode } } }, ! { "fmsubss", { { OP_DREX4, w_mode } } }, ! { "fmsubsd", { { OP_DREX4, d_mode } } }, ! { "fmsubps", { { OP_DREX4, DREX_OC1 + q_mode } } }, ! { "fmsubpd", { { OP_DREX4, DREX_OC1 + q_mode } } }, ! { "fmsubss", { { OP_DREX4, DREX_OC1 + w_mode } } }, ! { "fmsubsd", { { OP_DREX4, DREX_OC1 + d_mode } } }, ! /* 10 */ ! { "fnmaddps", { { OP_DREX4, q_mode } } }, ! { "fnmaddpd", { { OP_DREX4, q_mode } } }, ! { "fnmaddss", { { OP_DREX4, w_mode } } }, ! { "fnmaddsd", { { OP_DREX4, d_mode } } }, ! { "fnmaddps", { { OP_DREX4, DREX_OC1 + q_mode } } }, ! { "fnmaddpd", { { OP_DREX4, DREX_OC1 + q_mode } } }, ! { "fnmaddss", { { OP_DREX4, DREX_OC1 + w_mode } } }, ! { "fnmaddsd", { { OP_DREX4, DREX_OC1 + d_mode } } }, ! /* 18 */ ! { "fnmsubps", { { OP_DREX4, q_mode } } }, ! { "fnmsubpd", { { OP_DREX4, q_mode } } }, ! { "fnmsubss", { { OP_DREX4, w_mode } } }, ! { "fnmsubsd", { { OP_DREX4, d_mode } } }, ! { "fnmsubps", { { OP_DREX4, DREX_OC1 + q_mode } } }, ! { "fnmsubpd", { { OP_DREX4, DREX_OC1 + q_mode } } }, ! { "fnmsubss", { { OP_DREX4, DREX_OC1 + w_mode } } }, ! { "fnmsubsd", { { OP_DREX4, DREX_OC1 + d_mode } } }, ! /* 20 */ ! { "permps", { { OP_DREX4, q_mode } } }, ! { "permpd", { { OP_DREX4, q_mode } } }, ! { "pcmov", { { OP_DREX4, q_mode } } }, ! { "pperm", { { OP_DREX4, q_mode } } }, ! { "permps", { { OP_DREX4, DREX_OC1 + q_mode } } }, ! { "permpd", { { OP_DREX4, DREX_OC1 + q_mode } } }, ! { "pcmov", { { OP_DREX4, DREX_OC1 + w_mode } } }, ! { "pperm", { { OP_DREX4, DREX_OC1 + d_mode } } }, ! /* 28 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* 30 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* 38 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* 40 */ ! { "protb", { { OP_DREX3, q_mode } } }, ! { "protw", { { OP_DREX3, q_mode } } }, ! { "protd", { { OP_DREX3, q_mode } } }, ! { "protq", { { OP_DREX3, q_mode } } }, ! { "pshlb", { { OP_DREX3, q_mode } } }, ! { "pshlw", { { OP_DREX3, q_mode } } }, ! { "pshld", { { OP_DREX3, q_mode } } }, ! { "pshlq", { { OP_DREX3, q_mode } } }, ! /* 48 */ ! { "pshab", { { OP_DREX3, q_mode } } }, ! { "pshaw", { { OP_DREX3, q_mode } } }, ! { "pshad", { { OP_DREX3, q_mode } } }, ! { "pshaq", { { OP_DREX3, q_mode } } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* 50 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* 58 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* 60 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* 68 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* 70 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* 78 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* 80 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "pmacssww", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } }, ! { "pmacsswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } }, ! { "pmacssdql", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } }, ! /* 88 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "pmacssdd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } }, ! { "pmacssdqh", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } }, ! /* 90 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "pmacsww", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } }, ! { "pmacswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } }, ! { "pmacsdql", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } }, ! /* 98 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } 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"(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* e0 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* e8 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* f0 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* f8 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! }, ! /* THREE_BYTE_SSE5_0F7B */ ! { ! /* 00 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* 08 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* 10 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* 18 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* 20 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* 28 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* 30 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* 38 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* 40 */ ! { "protb", { XM, EXq, Ib } }, ! { "protw", { XM, EXq, Ib } }, ! { "protd", { XM, EXq, Ib } }, ! { "protq", { XM, EXq, Ib } }, ! { "pshlb", { XM, EXq, Ib } }, ! { "pshlw", { XM, EXq, Ib } }, ! { "pshld", { XM, EXq, Ib } }, ! { "pshlq", { XM, EXq, Ib } }, ! /* 48 */ ! { "pshab", { XM, EXq, Ib } }, ! { "pshaw", { XM, EXq, Ib } }, ! { "pshad", { XM, EXq, Ib } }, ! { "pshaq", { XM, EXq, Ib } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* 50 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* 58 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* 60 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* 68 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* 70 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* 78 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* 80 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* 88 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* 90 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* 98 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* a0 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* a8 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* b0 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* b8 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* c0 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! /* c8 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, /* d0 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, /* d8 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, /* e0 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, /* e8 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, /* f0 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, /* f8 */ ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, ! { "(bad)", { XX } }, } }; *************** print_insn (bfd_vma pc, disassemble_info *** 3841,3853 **** unsigned char threebyte; FETCH_DATA (info, codep + 2); threebyte = *++codep; ! dp = &dis386_twobyte[threebyte]; ! need_modrm = twobyte_has_modrm[*codep]; ! codep++; ! if (dp->name == NULL && dp->op[0].bytemode == IS_3BYTE_OPCODE) { ! FETCH_DATA (info, codep + 2); ! op = *codep++; } } else --- 5040,5068 ---- unsigned char threebyte; FETCH_DATA (info, codep + 2); threebyte = *++codep; ! ! /* SSE5 0f 24 overlaps with the 386 mov test instruction. SSE5 3rd ! opcode doesn't have the upper 2 bits set, which are set with mov test ! MODRM register-register encoding, so special case this. */ ! if (threebyte == 0x24) ! FETCH_DATA (info, codep + 2); ! ! if (threebyte == 0x24 && (codep[1] & 0xc0) == 0xc0) ! { ! dp = &dis386_move_test; ! need_modrm = 1; ! codep++; ! } ! else { ! dp = &dis386_twobyte[threebyte]; ! need_modrm = twobyte_has_modrm[*codep]; ! codep++; ! if (dp->name == NULL && dp->op[0].bytemode == IS_3BYTE_OPCODE) ! { ! FETCH_DATA (info, codep + 2); ! op = *codep++; ! } } } else *************** intel_operand_size (int bytemode, int si *** 4977,4983 **** } static void ! OP_E (int bytemode, int sizeflag) { bfd_vma disp; int add = 0; --- 6192,6198 ---- } static void ! OP_E_extended (int bytemode, int sizeflag, int has_drex) { bfd_vma disp; int add = 0; *************** OP_E (int bytemode, int sizeflag) *** 5083,5088 **** --- 6298,6310 ---- } base += add; + /* If we have a DREX byte, skip it now (it has already been handled) */ + if (has_drex) + { + FETCH_DATA (the_info, codep + 1); + codep++; + } + switch (modrm.mod) { case 0: *************** OP_E (int bytemode, int sizeflag) *** 5269,5274 **** --- 6491,6503 ---- } static void + OP_E (int bytemode, int sizeflag) + { + OP_E_extended (bytemode, sizeflag, 0); + } + + + static void OP_G (int bytemode, int sizeflag) { int add = 0; *************** CRC32_Fixup (int bytemode, int sizeflag) *** 6488,6490 **** --- 7717,8050 ---- else OP_E (bytemode, sizeflag); } + + /* Print a DREX argument as either a register or memory operation. */ + static void + print_drex_arg (unsigned int reg, int bytemode, int sizeflag) + { + if (reg == DREX_REG_UNKNOWN) + BadOp (); + + else if (reg != DREX_REG_MEMORY) + { + sprintf (scratchbuf, "%%xmm%d", reg); + oappend (scratchbuf + intel_syntax); + } + + else + OP_E_extended (bytemode, sizeflag, 1); + } + + /* SSE5 instructions that have 4 arguments are encoded as: + 0f 24 . + + The byte has 1 bit (0x4) that is combined with 1 bit in the + DREX field (0x8) to determine how the arguments are laid out. The + destination register must be the same register as one of the inputs, and it + is encoded in the DREX byte. No REX prefix is used for these instructions, + since the DREX field contains the 3 extension bits provided by the REX + prefix. + + The bytemode argument adds 2 extra bits for passing extra information: + DREX_OC1 -- Set the OC1 bit to indicate dest == 1st arg + DREX_NO_OC0 -- OC0 in DREX is invalid (but pretend it is set). */ + + static void + OP_DREX4 (int flag_bytemode, int sizeflag) + { + unsigned int drex_byte; + unsigned int regs[4]; + unsigned int modrm_regmem; + unsigned int modrm_reg; + unsigned int drex_reg; + int bytemode; + int rex_save = rex; + int rex_used_save = rex_used; + int has_sib = 0; + int oc1 = (flag_bytemode & DREX_OC1) ? 2 : 0; + int oc0; + int i; + + bytemode = flag_bytemode & ~ DREX_MASK; + + for (i = 0; i < 4; i++) + regs[i] = DREX_REG_UNKNOWN; + + /* Determine if we have a SIB byte in addition to MODRM before the DREX + byte. */ + if (((sizeflag & AFLAG) || address_mode == mode_64bit) + && (modrm.mod != 3) + && (modrm.rm == 4)) + has_sib = 1; + + /* Get the DREX byte. */ + FETCH_DATA (the_info, codep + 2 + has_sib); + drex_byte = codep[has_sib+1]; + drex_reg = DREX_XMM (drex_byte); + modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0); + + /* Is OC0 legal? If not, hardwire oc0 == 1. */ + if (flag_bytemode & DREX_NO_OC0) + { + oc0 = 1; + if (DREX_OC0 (drex_byte)) + BadOp (); + } + else + oc0 = DREX_OC0 (drex_byte); + + if (modrm.mod == 3) + { /* regmem == register */ + modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0); + rex = rex_used = 0; + codep += 2; /* skip modrm/drex since we don't call OP_E_extended */ + } + else + { /* regmem == memory, fill in appropriate REX bits */ + modrm_regmem = DREX_REG_MEMORY; + rex = drex_byte & (REX_B | REX_X | REX_R); + if (rex) + rex |= REX_OPCODE; + rex_used = rex; + } + + /* Based on the OC1/OC0 bits, lay out the arguments in the correct order. */ + switch (oc0 + oc1) + { + default: + BadOp (); + return; + + case 0: + regs[0] = modrm_regmem; + regs[1] = modrm_reg; + regs[2] = drex_reg; + regs[3] = drex_reg; + break; + + case 1: + regs[0] = modrm_reg; + regs[1] = modrm_regmem; + regs[2] = drex_reg; + regs[3] = drex_reg; + break; + + case 2: + regs[0] = drex_reg; + regs[1] = modrm_regmem; + regs[2] = modrm_reg; + regs[3] = drex_reg; + break; + + case 3: + regs[0] = drex_reg; + regs[1] = modrm_reg; + regs[2] = modrm_regmem; + regs[3] = drex_reg; + break; + } + + /* Print out the arguments. */ + for (i = 0; i < 4; i++) + { + int j = (intel_syntax) ? 3 - i : i; + if (i > 0) + { + *obufp++ = ','; + *obufp = '\0'; + } + + print_drex_arg (regs[j], bytemode, sizeflag); + } + + rex = rex_save; + rex_used = rex_used_save; + } + + /* SSE5 instructions that have 3 arguments, and are encoded as: + 0f 24 (or) + 0f 25 + + The DREX field has 1 bit (0x8) to determine how the arguments are laid out. + The destination register is encoded in the DREX byte. No REX prefix is used + for these instructions, since the DREX field contains the 3 extension bits + provided by the REX prefix. */ + + static void + OP_DREX3 (int flag_bytemode, int sizeflag) + { + unsigned int drex_byte; + unsigned int regs[3]; + unsigned int modrm_regmem; + unsigned int modrm_reg; + unsigned int drex_reg; + int bytemode; + int rex_save = rex; + int rex_used_save = rex_used; + int has_sib = 0; + int oc0; + int i; + + bytemode = flag_bytemode & ~ DREX_MASK; + + for (i = 0; i < 3; i++) + regs[i] = DREX_REG_UNKNOWN; + + /* Determine if we have a SIB byte in addition to MODRM before the DREX + byte. */ + if (((sizeflag & AFLAG) || address_mode == mode_64bit) + && (modrm.mod != 3) + && (modrm.rm == 4)) + has_sib = 1; + + /* Get the DREX byte. */ + FETCH_DATA (the_info, codep + 2 + has_sib); + drex_byte = codep[has_sib+1]; + drex_reg = DREX_XMM (drex_byte); + modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0); + + /* Is OC0 legal? If not, hardwire oc0 == 0 */ + oc0 = DREX_OC0 (drex_byte); + if ((flag_bytemode & DREX_NO_OC0) && oc0) + BadOp (); + + if (modrm.mod == 3) + { /* regmem == register */ + modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0); + rex = rex_used = 0; + codep += 2; /* skip modrm/drex since we don't call + OP_E_extended. */ + } + else + { /* regmem == memory, fill in appropriate REX bits. */ + modrm_regmem = DREX_REG_MEMORY; + rex = drex_byte & (REX_B | REX_X | REX_R); + if (rex) + rex |= REX_OPCODE; + rex_used = rex; + } + + /* Based on the OC1/OC0 bits, lay out the arguments in the correct order. */ + switch (oc0) + { + default: + BadOp (); + return; + + case 0: + regs[0] = modrm_regmem; + regs[1] = modrm_reg; + regs[2] = drex_reg; + break; + + case 1: + regs[0] = modrm_reg; + regs[1] = modrm_regmem; + regs[2] = drex_reg; + break; + } + + /* Print out the arguments. */ + for (i = 0; i < 3; i++) + { + int j = (intel_syntax) ? 2 - i : i; + if (i > 0) + { + *obufp++ = ','; + *obufp = '\0'; + } + + print_drex_arg (regs[j], bytemode, sizeflag); + } + + rex = rex_save; + rex_used = rex_used_save; + } + + /* Emit a floating point comparison for comp instructions. */ + + static void + OP_DREX_FCMP (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) + { + unsigned char byte; + + static const char *const cmp_test[] = { + "eq", + "lt", + "le", + "unord", + "ne", + "nlt", + "nle", + "ord", + "ueq", + "ult", + "ule", + "false", + "une", + "unlt", + "unle", + "true" + }; + + FETCH_DATA (the_info, codep + 1); + byte = *codep & 0xff; + + if (byte >= ARRAY_SIZE (cmp_test) + || obuf[0] != 'c' + || obuf[1] != 'o' + || obuf[2] != 'm') + { + /* The instruction isn't one we know about, so just append the extension + byte as a numeric value. */ + OP_I (b_mode, 0); + } + + else + { + sprintf (scratchbuf, "com%s%s", cmp_test[byte], obuf+3); + strcpy (obuf, scratchbuf); + codep++; + } + } + + /* Emit an integer point comparison for pcom instructions, rewriting the + instruction to have the test inside of it. */ + + static void + OP_DREX_ICMP (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) + { + unsigned char byte; + + static const char *const cmp_test[] = { + "lt", + "le", + "gt", + "ge", + "eq", + "ne", + "false", + "true" + }; + + FETCH_DATA (the_info, codep + 1); + byte = *codep & 0xff; + + if (byte >= ARRAY_SIZE (cmp_test) + || obuf[0] != 'p' + || obuf[1] != 'c' + || obuf[2] != 'o' + || obuf[3] != 'm') + { + /* The instruction isn't one we know about, so just print the comparison + test byte as a numeric value. */ + OP_I (b_mode, 0); + } + + else + { + sprintf (scratchbuf, "pcom%s%s", cmp_test[byte], obuf+4); + strcpy (obuf, scratchbuf); + codep++; + } + } *** opcodes/Makefile.am.~1~ 2007-08-31 11:40:02.892233000 -0400 --- opcodes/Makefile.am 2007-08-28 20:28:32.639949000 -0400 *************** i370-opc.lo: i370-opc.c sysdep.h config. *** 802,808 **** $(INCDIR)/opcode/i370.h i386-dis.lo: i386-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \ ! $(INCDIR)/ansidecl.h opintl.h $(INCDIR)/opcode/i386.h i386-opc.lo: i386-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h i386-opc.h \ $(INCDIR)/opcode/i386.h i386-tbl.h --- 802,809 ---- $(INCDIR)/opcode/i370.h i386-dis.lo: i386-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \ ! $(INCDIR)/ansidecl.h opintl.h $(INCDIR)/opcode/i386.h \ ! $(INCDIR)/libiberty.h i386-opc.lo: i386-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h i386-opc.h \ $(INCDIR)/opcode/i386.h i386-tbl.h *** opcodes/Makefile.in.~1~ 2007-08-31 11:40:02.940608000 -0400 --- opcodes/Makefile.in 2007-08-28 20:28:10.059552000 -0400 *************** i370-opc.lo: i370-opc.c sysdep.h config. *** 1353,1359 **** $(INCDIR)/opcode/i370.h i386-dis.lo: i386-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \ ! $(INCDIR)/ansidecl.h opintl.h $(INCDIR)/opcode/i386.h i386-opc.lo: i386-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h i386-opc.h \ $(INCDIR)/opcode/i386.h i386-tbl.h --- 1353,1360 ---- $(INCDIR)/opcode/i370.h i386-dis.lo: i386-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \ ! $(INCDIR)/ansidecl.h opintl.h $(INCDIR)/opcode/i386.h \ ! $(INCDIR)/libiberty.h i386-opc.lo: i386-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h i386-opc.h \ $(INCDIR)/opcode/i386.h i386-tbl.h