[Bug gas/9856] generates "illegal" opcodes in unified mode instead of error

[bastian dot schick at sciopta dot com]

------- Additional Comments From bastian dot schick at sciopta dot com  
2009-04-09 15:20 -------
(In reply to comment #2)

Hi Nick

>   This is not a bug.  The assembler is quite reasonably translating the
> requested operation (move low register to low register whilst setting the 
> status
> bits) into a machine instruction that will perform the operation.  The fact 
> that
> it needs to use an ADDS opcode instead of a MOVS opcode is a technical issue,
> not a cause for the assembler to generate an error.

Maybe I was not clear enough. The second opcode is correct, as you describe.
But the "mov r1,r0" is incorrect for ARMv4T,ARMv5T machines.
Check ARM ARM A7.1.44 :
"  If H1==0 and H2==0 in the encoding, the instruction specifies a 
non-flag-setting 
copy move from one low register to another low register. This instruction 
cannot be 
written using the MOV syntax, because MOV <Rd>, <Rm> generates a flag-setting 
copy. However, you can write it using the CPY mnemonic, see CPY on page A7-41.
Note
  Prior to ARMv6, specifying a low register for <Rd> and <Rm> (H1 == 0 and H2 
== 0), the result is UNPREDICTABLE."

Since the CPU selected (XScale) is ARMv5TE, I still thing it is a bug.


-- 
           What    |Removed                     |Added
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             Status|RESOLVED                    |REOPENED
         Resolution|INVALID                     |


http://sourceware.org/bugzilla/show_bug.cgi?id=9856

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