Re: [Bug gas/13215] New: ARM Cortex M3 strexh strexb instructions with same registers generates error

[Benjamin Green]

I had the same problem with my cross compiler, as you can see the code 
translates into the same number of instructions.

DaniBoy's solution:

register uint32_t result asm ("r2");

00000000 <__STREXB>:
   0:   e8c1 0f42       strexb  r2, r0, [r1]
   4:   4610            mov     r0, r2
   6:   4770            bx      lr

Hans-Peter Nilsson's solution:

__ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" 
(value) );

00000000 <__STREXB>:
   0:   4603            mov     r3, r0
   2:   e8c1 3f50       strexb  r0, r3, [r1]
   6:   4770            bx      lr

r0, r1, r2 and r3 are all argument registers and r0 is the integer 
function result register (alternate names are a1, a2, a3 and a4) so I 
cannot see an obvious problem with either of these solutions. I think 
perhaps I would lean twards Hans-Peter Nilsson's solution as if this 
function were inlined the compiler may be able to optimise register 
usage. I also did not check the impact ordering would have on the 
instruction pipeline.

This bug is invalid (as Bugzilla says) and also more concern to ARM 
Cortex-M3 users... sorry for the clutter.

Benjamin.