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[Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3


From: meadori at codesourcery dot com
Subject: [Bug ld/16017] LD creates invalid PLT instructions on CORTEX-M3
Date: Fri, 31 Jan 2014 18:45:20 +0000

https://sourceware.org/bugzilla/show_bug.cgi?id=16017

--- Comment #18 from Meador Inge <meadori at codesourcery dot com> ---
Right, my reading of the ARM manuals suggest that with 'ADD <Rdn>, <Rm>' (T2
encoding) that Rm can be PC. Only things like 'ADD PC, Rm' and 'ADD PC, PC' are
unpredictable.

I came up with a similar encoding:

   0:    f240 0c00     movw    ip, #0
   4:    f2c0 0c00     movt    ip, #0
   8:    44fc          add    ip, pc
   a:    f8dc f000     ldr.w    pc, [ip]
   e:    bf00          nop

We might need the nop to group things into a multiple of 4.

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