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[Bug gas/23956] RISC-V 4-operand add doesn't check for %tprel_add
From: |
wilson at gcc dot gnu.org |
Subject: |
[Bug gas/23956] RISC-V 4-operand add doesn't check for %tprel_add |
Date: |
Fri, 07 Dec 2018 00:41:04 +0000 |
https://sourceware.org/bugzilla/show_bug.cgi?id=23956
Jim Wilson <wilson at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|UNCONFIRMED |NEW
Last reconfirmed| |2018-12-07
Assignee|unassigned at sourceware dot org |wilson at gcc dot
gnu.org
Ever confirmed|0 |1
--- Comment #1 from Jim Wilson <wilson at gcc dot gnu.org> ---
I consider it a bug, but not serious enough that I had gotten around to trying
to fix it yet. The support for the 4-operand add is overloaded with the amo*
instruction support that requires addresses with a constant 0 immediate offset.
It is an odd design. I don't know why it was done this way. The fact that we
accept 0 for an amo* instruction is why zero gets accepted for the 4-operand
add, which looked like a fairly harmless bug to me. But looking at this
closer, I see that the same overload means that we can use %tprel_add in an
amo* instruction, which is a more serious problem that I think justifies a fix
now.
rohan:2097$ cat tmp2.s
amoadd.w x8,x9,%tprel_add(i)(x10)
.globl i
.section .tbss,"awT",@nobits
.align 2
.type i, @object
.size i, 4
i:
.zero 4
rohan:2098$ ./as-new tmp2.s
rohan:2099$ ../binutils/objdump -dr a.out
a.out: file format elf32-littleriscv
Disassembly of section .text:
00000000 <.text>:
0: 0095242f amoadd.w s0,s1,(a0)
0: R_RISCV_TPREL_ADD i
0: R_RISCV_RELAX *ABS*
rohan:2100$
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