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Re: asyncsafe-spin, simple-atomic: Add support for tcc
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From: |
Bruno Haible |
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Subject: |
Re: asyncsafe-spin, simple-atomic: Add support for tcc |
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Date: |
Thu, 04 Mar 2021 21:58:59 +0100 |
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User-agent: |
KMail/5.1.3 (Linux/4.4.0-203-generic; KDE/5.18.0; x86_64; ; ) |
Hi Christian,
> Hi wouldn't be better to ask tcc maintainers to support mfence for __i386
> target?
I don't see it as a bug if tcc/x86 assumes a target that does not support SSE
instructions. "gcc -m32 -mno-sse" also assumes a target that does not support
SSE instructions.
Similarly, GCC/SPARC by default assumes only the SPARC v7 instruction set,
although all SPARC CPUs made since 1993 support the SPARC v8+ instruction set.
It's not a bug, just a choice made by the developers of the compiler.
However, it would be useful if tcc/x86 had an option to enable and allow
SSE instructions. In version 0.9.27, 'tcc -hh' does not list such an option.
Bruno