Re: SMP, barriers, etc.

[Da Zheng]

On 09-12-28 下午8:32, Samuel Thibault wrote:
>> So when a write memory barrier instruction is executed, the processor
>> has to remember the order of writes, so the read memory barrier
>> instruction executed on another processor can somehow get the
>> information?
> 
> In principle, yes. The actual implementation in the hardware cache
> coherency protocol can be a barrier that prevents reordering, or
> sequential numbers, etc.
I think I get some vague ideas about barriers and cache coherency now. I really
should take some courses about multiprocessor architectures when I was at
school. Unfortunately, my school only has this kind of course after I left it:-(

Thank you very much for your explanation, Samuel.

Zheng Da