clean dependencies

[Lindner, Mike]

I wouldn't call this a bug, but it is a problem, and the GNU make
documentation lists this as the address for this kind of thing. I have a
makefile that looks like:

        %.d: %.cpp
        $(SHELL) -ec '$(CC) -MM $(CPPFLAGS) $< \
                | sed '\''s/\($*\)\.o[ :]*/\1.o $@ : /g'\'' > $@; \
                        [ -s $@ ] || rm -f $@'

        SRC = a.cpp b.cpp c.cpp
        DEPS = $(SRC:.cpp=.d)
        OBJS = $(SRC:.cpp=.o)

        clean:
                rm -f $(DEPS) $(OBJS)

        include $(DEPS)

...and when I do a "make clean" in a clean directory it builds the
dependencies, which takes quite some time (needless to say, there's more
meat in the real makefile). I'd like some way of avoiding the rebuliding of
dependencies for targets (liek clean) that don't need them. I thought of
testing the target and making the include conditional, but there doesn't
seem to be a way to access the target variable before the include happens. I
found no solution in the online documentation. Is there a way to do this, or
is there a better way to write the makefile to avoid the problem?

Thanks,
---
Mike Lindner