Jim wrote:
Hmm not sure how eval equates to include...
Since the actual end in mind is a Makefile.cache, which is the literal
expanded targets, rules nessecary to genearte the product defined by
the makefile... This must be dependant on all makefiles which may
have changed... the final result is a huge tree of includable .cache
files which have the rules needed for all dependants (libraries in
other branches, etc )
I'm not sure, but the following may help:
# sets __FILE__ macro to file to be included, then includes the file.
# allows included file to know where it is in relation to includer.
# caching of included makefile is allowed if $(2)!contents is defined as
the contents of the makefile.
# $(1) is the include method, either "include" or "-include"
# $(2) is the file to be included
# $(3) is the includer
define _include-makefile
__FILE__ := $(2)
ifndef $(2)!contents
# using an order rule suppresses the error when $(1) is "include"
ifeq ($(wildcard $(dir $(2))),)
$(shell mkdir -p $(dir $(2)))
endif
$(1) $(2)
else
$$(eval $$($(2)!contents))
endif
__FILE__ := $(3)
endef
# optionally include makefile passing in its name as __FILE__
# allows included file to know where it is in relation to includer.
# caching of included makefile is allowed if $(2)!contents is defined as
the contents of the makefile.
# $(1) is the file to be included
-include-makefile = $(foreach \
m, \
$(1), \
$(eval $(call _include-makefile,-include,$(m),$(__FILE__))))
# include makefile passing in its name as __FILE__
# allows included file to know where it is in relation to includer.
# caching of included makefile is allowed if $(2)!contents is defined as
the contents of the makefile.
# $(1) is the file to be included
include-makefile = $(foreach \
m, \
$(1), \
$(eval $(call _include-makefile,include,$(m),$(__FILE__))))
If the file's corresponding !contents macro is defined, it the macro
just eval's it. Usually, the !contents macro is defined within the file
itself.