proposal: "module" declaration instead of recursive make

[Jason Eisner]

Hi,

If the following proposal is new, please let me know whether I am
sending it to the right place (would address@hidden be better?).

As pointed out in "Recursive Make Considered Harmful," information
about dependencies is not visible across makefiles.

But couldn't GNU make have a facility for exposing this information?
This would solve most of the problems with recursive make.

What I have in mind is a "module" directive that's like "include," 
with two differences:

(a) it corrects for the fact that targets, prereqs, and commands
    in the included makefile should be interpreted relative to a
    different working directory.  

(b) it keeps the variable namespaces separate.

Example:

+-- child/Makefile --------
| 
| var = kid
| foo: bar
|       echo $(var)
| clean: 
|       rm *.o

+-- Makefile --------------
|
| module child/Makefile, ch-
|
| var = parent
| target: child/foo
|      echo $(ch-var), $(var)

has basically the same effect as

+---------------------------
|
| ch-var = kid
| child/foo: child/bar  # uses dir of module's makefile (rel. or abs.)
|       cd child; echo $(ch-var)  # uses namespace prefix from module directive
| child/clean: 
|       cd child; rm *.o
| 
| var = parent
| target: child/foo
|      echo $(ch-var), $(var)   

Advantages:

- the child makefile can still be written and run as a standalone.

- the parent makefile can see and analyze all the dependencies in the
  child makefile.  It uses the child makefile to ensure that child/foo
  is up to date, and rebuilds target ONLY IF child/foo needed
  updating.

- to speed up makes for large projects, it may be possible to perform
  the include processing lazily (I'm not convinced of that, though).

Notes: 

- To avoid accidental name conflicts, an unambiguous namespace qualifier
  would be preferable to the simple namespace prefix suggested above.

- It should be okay for two makefiles to use each other as modules.
  This allows you to partition your work however you want across
  multiple makefiles (within one directory or across directories).

  This is not possible by a naive implementation as a munged include
  (because of recursion) but seems straightforward enough to support
  in principle.

  Ideally, it would allow the user to write arbitrarily deep variable 
  names:
    $(module1-module2-module1-module2-var):

Regards,

Jason Eisner
Assistant Professor of Computer Science
Johns Hopkins University