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Re: issue when using MAKEFILES variable


From: jean-luc malet
Subject: Re: issue when using MAKEFILES variable
Date: Sun, 1 Nov 2009 10:40:43 +0100

ok I found the culpit....
in one of the sub included makefiles there is

SELF    = $(firstword $(MAKEFILE_LIST))
MKFLAGS = $(foreach tmp, $(MAKEFLAGS), $(addsuffix \",$(addprefix
\",$(shell echo $(tmp) | grep =))))

mytodo:
        @$(MAKE) GENDEP=1 -f $(SELF) -r --no-print-directory todo $(MKFLAGS)


the issue is that SELF is used in lot of places.... and that it must
remain possible to use the previous behaviour ie not using
MAKEFILES....

however, this isn't a make bug.... sorry for the inconvenience. And
thanks for the help, I thought about checking MAKEFILES but didn't
thought that someone could use MAKEFILE_LIST to re-call a submake...

thanks and regards,
JLM

On Sun, Nov 1, 2009 at 12:40 AM, Martin Dorey <address@hidden> wrote:
>> sadely I can't give you the real files
>
> If you copy them, then strip out everything that turns out to be irrelevant, 
> then rename all the remaining targets, variables and files, then you'll end 
> up with an example that you can send us.  I've done that on a number of 
> occasions for compiler bugs and, while I can attest that it's tedious work, 
> it rarely takes longer than, say, an hour.
>
> ----- Original Message -----
> From: jean-luc malet <address@hidden>
> To: Martin Dorey
> Cc: address@hidden <address@hidden>
> Sent: Sat Oct 31 12:24:45 2009
> Subject: Re: issue when using MAKEFILES variable
>
> Hi! thanks for the reply
> I tried with another makefile created from scratch and indeed the
> behaviour is the expected one...
> the problem still arise with the makefile used in product....
> this makefile does include some other makefiles containing default rules
> in fact this looks like this :
>
> ====== Makefile.top ========
> include default.rules
>
> SOURCES=1.c 2.c 3.c
> todo : lib
> ====== default.rules ========
> all : todo
>
> some other rules that convert SOURCES variable into something usefull
> =========================
>
> when I add
> include to Makefile.top this work each time (first and other times)
> when I come back to the above and run it using MAKEFILES it never run
> sadely I can't give you the real files because the files used are
> owned by the corporation I'm working for...
>
> I don't understand but it seems that the fact that make parse the
> Makefile.top before the Makefile.conf and that make parse the
> Makefile.conf before the Makefile.top change the behaviour....
>
> I was thinking about some ':=' variables.... but I don't think this is the 
> issue
> since Makefile.conf contain only export variable=values it can be
> sourced into a sh.... when I do
> source Makefile.conf; make -f Makefile.top all
> this is working again....
>
> to summarise :
> 1) if I set the env before running make using sh this is working
> 2) if I use MAKEFILES variable to have make set the env for me this never work
> 3) if I use include directive in Makefile to have make set the env for
> me it is working
>
> for me 1) and 2) should behave the same way and for some reason it don't...
> thanks and regard
> JLM
>
>
> On Fri, Oct 30, 2009 at 10:18 PM, Martin Dorey <address@hidden> wrote:
>> I'm having trouble understanding what you mean.  When you've read my example
>> below, if the lack of "hello from theconffile" output in the first run of
>> make, and its presence in the second run, doesn't answer your question and
>> show you how to solve the problem, then please modify my example to
>> illustrate your problem, saying what you think the output should be where
>> the actual output differs.
>>
>>
>>
>> address@hidden:~/tmp/make-jpm$ cat > theconffile
>>
>> $(info hello from theconffile)
>>
>> address@hidden:~/tmp/make-jpm$ cat > Makefile
>>
>> default:
>>
>> ^       MAKEFILES=theconffile $(MAKE) -C component -f Makefile
>>
>> address@hidden:~/tmp/make-jpm$ mkdir component
>>
>> address@hidden:~/tmp/make-jpm$ cat > component/Makefile
>>
>> $(info hello from component/Makefile)
>>
>> default:;
>>
>> address@hidden:~/tmp/make-jpm$ make
>>
>> MAKEFILES=theconffile make -C component -f Makefile
>>
>> hello from component/Makefile
>>
>> make[1]: Entering directory `/home/martind/tmp/make-jpm/component'
>>
>> make[1]: `default' is up to date.
>>
>> make[1]: Leaving directory `/home/martind/tmp/make-jpm/component'
>>
>> address@hidden:~/tmp/make-jpm$ cat > Makefile
>>
>> default:
>>
>> ^       MAKEFILES=$(CURDIR)/theconffile $(MAKE) -C component -f Makefile
>>
>> address@hidden:~/tmp/make-jpm$ make
>>
>> MAKEFILES=/home/martind/tmp/make-jpm/theconffile make -C component -f
>> Makefile
>>
>> hello from theconffile
>>
>> hello from component/Makefile
>>
>> make[1]: Entering directory `/home/martind/tmp/make-jpm/component'
>>
>> make[1]: `default' is up to date.
>>
>> make[1]: Leaving directory `/home/martind/tmp/make-jpm/component'
>>
>> address@hidden:~/tmp/make-jpm$
>>
>>
>>
>> -----Original Message-----
>> From: address@hidden
>> [mailto:address@hidden On Behalf Of jean-luc
>> malet
>> Sent: Friday, October 30, 2009 04:24
>> To: address@hidden
>> Subject: issue when using MAKEFILES variable
>>
>>
>>
>> hi!
>>
>> I face issue when using MAKEFILES variable
>>
>> this variable is set into a toplevel makefile and contain only
>>
>>        export varname=varvalue
>>
>> lines
>>
>>
>>
>> then submake is called into rules like this
>>
>> target :
>>
>>           MAKEFILES=theconffile ${MAKE} -C the/component/path -f Makefile
>> target
>>
>>
>>
>> into the/component/path/Makefile
>>
>> I have several include, some targets....
>>
>> and
>>
>> $(warning ${VAR})
>>
>> $(warning ${MAKEFILE_LIST})
>>
>> $(warning ${MAKEFILES})
>>
>>
>>
>> where VAR is a variable found only in theconffile
>>
>>
>>
>> MAKEFILE_LIST and MAKEFILES warning show correct behaviour :
>>
>> theconfile is first makefile read then Makefile is....
>>
>> VAR warning is correct, thus I think that the behaviour in correct....
>>
>>
>>
>> BUT all targets fails
>>
>> there is a target todo: into the Makefile
>>
>> and make complain about not knowing how to do todo....
>>
>>
>>
>> HOWEVER if I do
>>
>>    include theconffile
>>
>> into Makefile
>>
>> and run sub make with
>>
>>   ${MAKE} -C the/component/path -f Makefile target
>>
>>
>>
>> then it works.......
>>
>> I'm puzzled....
>>
>> thanks a lot
>>
>> JLM
>>
>>
>>
>> --
>>
>> KISS! (Keep It Simple, Stupid!)
>>
>> (garde le simple, imbécile!)
>>
>> "mais qu'est-ce que tu m'as pondu comme usine à gaz? fait des choses
>>
>> simples et qui marchent, espèce d'imbécile!"
>>
>> -----------------------------
>>
>> "Si vous pensez que vous êtes trop petit pour changer quoique ce soit,
>>
>> essayez donc de dormir avec un moustique dans votre chambre." Betty
>>
>> Reese
>>
>> http://www.grainesdechangement.com/citations.htm
>>
>>
>>
>>
>>
>> _______________________________________________
>>
>> Bug-make mailing list
>>
>> address@hidden
>>
>> http://lists.gnu.org/mailman/listinfo/bug-make
>
>
>
> --
> KISS! (Keep It Simple, Stupid!)
> (garde le simple, imbécile!)
> "mais qu'est-ce que tu m'as pondu comme usine à gaz? fait des choses
> simples et qui marchent, espèce d'imbécile!"
> -----------------------------
> "Si vous pensez que vous êtes trop petit pour changer quoique ce soit,
> essayez donc de dormir avec un moustique dans votre chambre." Betty
> Reese
> http://www.grainesdechangement.com/citations.htm
>



-- 
KISS! (Keep It Simple, Stupid!)
(garde le simple, imbécile!)
"mais qu'est-ce que tu m'as pondu comme usine à gaz? fait des choses
simples et qui marchent, espèce d'imbécile!"
-----------------------------
"Si vous pensez que vous êtes trop petit pour changer quoique ce soit,
essayez donc de dormir avec un moustique dans votre chambre." Betty
Reese
http://www.grainesdechangement.com/citations.htm




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