[Qemu-commits] [qemu/qemu] f022b8: hw/arm/virt: add linux, stdout-path to /chosen DT ...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: f022b8e95379b0433d13509706b66f38fc15dde8
      
https://github.com/qemu/qemu/commit/f022b8e95379b0433d13509706b66f38fc15dde8
  Author: Ard Biesheuvel <address@hidden>
  Date:   2014-09-12 (Fri, 12 Sep 2014)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: add linux, stdout-path to /chosen DT node

Add a property "linux,stdout-path" to the /chosen DT node and make
it point to the emulated UART. This allows users such as the Linux
kernel to produce console output without the need to pass console=
or earlycon=pl011,0x... command line arguments.

Signed-off-by: Ard Biesheuvel <address@hidden>
Message-id: address@hidden
Reviewed-by: Rob Herring <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c3c8d6b3ddc881fb2ebd651e320cda36b2ec079b
      
https://github.com/qemu/qemu/commit/c3c8d6b3ddc881fb2ebd651e320cda36b2ec079b
  Author: David Hoover <address@hidden>
  Date:   2014-09-12 (Fri, 12 Sep 2014)

  Changed paths:
    M cpu-exec.c

  Log Message:
  -----------
  cpu-exec.c: Allow disabling of IRQs on ARM Cortex-M CPUs

Correct an error in the logic for deciding whether we can
take an IRQ interrupt which meant that on M profile cores
it was never possible to disable them.

The design here is still bogus in that M profile doesn't
have separate "IRQ" and "FIQ", which are an A/R profile
concept; we should ideally implement the proper priority
based scheme.

Signed-off-by: David Hoover <address@hidden>
[PMM: Wrote a proper commit message]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: bfb27e6042e80fca90dc250657b420a73c1c42be
      
https://github.com/qemu/qemu/commit/bfb27e6042e80fca90dc250657b420a73c1c42be
  Author: Colin Leitner <address@hidden>
  Date:   2014-09-12 (Fri, 12 Sep 2014)

  Changed paths:
    M hw/gpio/pl061.c

  Log Message:
  -----------
  pl061: implement input interrupt logic

This patch adds the missing input interrupt logic to the pl061 GPIO device. To
keep the floating output pins to stay high, the old state variable had to be
split into two separate ones for input and output - which brings the vmstate
version to 3.

Edge level interrupts and I/O were tested under Linux 3.14. Level interrupt
handling hasn't been tested.

Signed-off-by: Colin Leitner <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6e3cf5df01bfa192ca162716670cf368ba1338dd
      
https://github.com/qemu/qemu/commit/6e3cf5df01bfa192ca162716670cf368ba1338dd
  Author: Martin Galvan <address@hidden>
  Date:   2014-09-12 (Fri, 12 Sep 2014)

  Changed paths:
    M target-arm/cpu.c

  Log Message:
  -----------
  target-arm: Fix resetting issues on ARMv7-M CPUs

When calling qemu_system_reset after startup on a Cortex-M
CPU, the initial values of PC, MSP and the Thumb bit weren't being set
correctly if the vector table was in ROM. In particular, since Thumb was 0, a
Usage Fault would arise immediately after trying to execute any instruction
on a Cortex-M.

Signed-off-by: Martin Galvan <address@hidden>
Message-id: address@hidden
[PMM: removed an incorrect comment]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 34bf774485a1259fc50515e8d761bd543bb316c8
      
https://github.com/qemu/qemu/commit/34bf774485a1259fc50515e8d761bd543bb316c8
  Author: Martin Galvan <address@hidden>
  Date:   2014-09-12 (Fri, 12 Sep 2014)

  Changed paths:
    M target-arm/cpu.c

  Log Message:
  -----------
  target-arm: Fix broken indentation in arm_cpu_reest()

Fix a single misindented line in arm_cpu_reset().

Signed-off-by: Martin Galvan <address@hidden>
[PMM: split this out from the previous commit]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: acf82361c61afe1fa842f0ae0d68b729509ec1ac
      
https://github.com/qemu/qemu/commit/acf82361c61afe1fa842f0ae0d68b729509ec1ac
  Author: Peter Maydell <address@hidden>
  Date:   2014-09-12 (Fri, 12 Sep 2014)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: Provide flash devices for boot ROMs

Add two flash devices to the virt board, so that it can be used for
running guests which want a bootrom image such as UEFI. We provide
two flash devices to make it more convenient to provide both a
read-only UEFI image and a read-write place to store guest-set
UEFI config variables. The '-bios' command line option is set up
to provide an image for the first of the two flash devices.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Paolo Bonzini <address@hidden>
Message-id: address@hidden


  Commit: 05068c0dfb5b23dde42ad0112123bdc8408a1f44
      
https://github.com/qemu/qemu/commit/05068c0dfb5b23dde42ad0112123bdc8408a1f44
  Author: Peter Maydell <address@hidden>
  Date:   2014-09-12 (Fri, 12 Sep 2014)

  Changed paths:
    M exec.c
    M include/qom/cpu.h
    M linux-user/main.c

  Log Message:
  -----------
  exec.c: Relax restrictions on watchpoint length and alignment

The current implementation of watchpoints requires that they
have a power of 2 length which is not greater than TARGET_PAGE_SIZE
and that their address is a multiple of their length. Watchpoints
on ARM don't fit these restrictions, so change the implementation
so they can be relaxed.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 3ee887e8ff7610d83bf05b0ebd5a1d891f0d8816
      
https://github.com/qemu/qemu/commit/3ee887e8ff7610d83bf05b0ebd5a1d891f0d8816
  Author: Peter Maydell <address@hidden>
  Date:   2014-09-12 (Fri, 12 Sep 2014)

  Changed paths:
    M exec.c

  Log Message:
  -----------
  exec.c: Provide full set of dummy wp remove functions in user-mode

We already provide dummy versions of the cpu_watchpoint_insert
and cpu_watchpoint_remove_all functions when CONFIG_USER_ONLY
is defined. Complete the set by providing cpu_watchpoint_remove
and cpu_watchpoint_remove_by_ref as well.

This allows target-* code using these functions to avoid
some ifdeffery.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 08225676b279fd14683275b65ed701972e008043
      
https://github.com/qemu/qemu/commit/08225676b279fd14683275b65ed701972e008043
  Author: Peter Maydell <address@hidden>
  Date:   2014-09-12 (Fri, 12 Sep 2014)

  Changed paths:
    M exec.c
    M include/qom/cpu.h

  Log Message:
  -----------
  exec.c: Record watchpoint fault address and direction

When we check whether we've hit a watchpoint we know the address
that we were attempting to access and whether it was a read or a
write. Record this information in the CPUWatchpoint struct so that
target-specific code can report it to the guest.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 86025ee4438e6e46eed767aad7c17ea94bb5c19b
      
https://github.com/qemu/qemu/commit/86025ee4438e6e46eed767aad7c17ea94bb5c19b
  Author: Peter Maydell <address@hidden>
  Date:   2014-09-12 (Fri, 12 Sep 2014)

  Changed paths:
    M cpu-exec.c
    M include/exec/exec-all.h
    M include/qom/cpu.h
    M qom/cpu.c
    M target-i386/cpu.c
    M target-i386/cpu.h
    M target-i386/helper.c
    M target-lm32/cpu.c
    M target-lm32/cpu.h
    M target-lm32/helper.c
    M target-xtensa/cpu.c
    M target-xtensa/cpu.h
    M target-xtensa/helper.c

  Log Message:
  -----------
  cpu-exec: Make debug_excp_handler a QOM CPU method

Make the debug_excp_handler target specific hook into a QOM
CPU method.

Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9ee98ce81089a123dd0c37f782d726bb14c67bf6
      
https://github.com/qemu/qemu/commit/9ee98ce81089a123dd0c37f782d726bb14c67bf6
  Author: Peter Maydell <address@hidden>
  Date:   2014-09-12 (Fri, 12 Sep 2014)

  Changed paths:
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/helper.c
    M target-arm/internals.h
    M target-arm/machine.c

  Log Message:
  -----------
  target-arm: Implement setting of watchpoints

Implement support for setting QEMU watchpoints based on the
values the guest writes to the ARM architected watchpoint
registers. (We do not yet report the firing of the watchpoints
to the guest, so they will just be ignored.)

Signed-off-by: Peter Maydell <address@hidden>


  Commit: 73c5211ba93c9d636a9c0a89e1d9037b6ef1418d
      
https://github.com/qemu/qemu/commit/73c5211ba93c9d636a9c0a89e1d9037b6ef1418d
  Author: Peter Maydell <address@hidden>
  Date:   2014-09-12 (Fri, 12 Sep 2014)

  Changed paths:
    M target-arm/helper.c
    M target-arm/internals.h

  Log Message:
  -----------
  target-arm: Move extended_addresses_enabled() to internals.h

Move the utility function extended_addresses_enabled() into
internals.h; we're going to need to call it from op_helper.c.

Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3ff6fc9148d0a9e683eb6ec78523a017247e990d
      
https://github.com/qemu/qemu/commit/3ff6fc9148d0a9e683eb6ec78523a017247e990d
  Author: Peter Maydell <address@hidden>
  Date:   2014-09-12 (Fri, 12 Sep 2014)

  Changed paths:
    M target-arm/cpu.c
    M target-arm/helper.c
    M target-arm/internals.h
    M target-arm/op_helper.c

  Log Message:
  -----------
  target-arm: Implement handling of fired watchpoints

Implement the ARM debug exception handler for dealing with
fired watchpoints.

Signed-off-by: Peter Maydell <address@hidden>


  Commit: 16a906fd6ebbe894d8545ba6168cabea5ef49b1d
      
https://github.com/qemu/qemu/commit/16a906fd6ebbe894d8545ba6168cabea5ef49b1d
  Author: Peter Maydell <address@hidden>
  Date:   2014-09-12 (Fri, 12 Sep 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Set DBGDSCR.MOE for debug exceptions taken to AArch32

For debug exceptions taken to AArch32 we have to set the
DBGDSCR.MOE (Method Of Entry) bits; we can identify the
kind of debug exception from the information in
exception.syndrome.

Signed-off-by: Peter Maydell <address@hidden>


  Commit: 17a9eb53a9bd226c3352f8d55b6f2383e0f74ff9
      
https://github.com/qemu/qemu/commit/17a9eb53a9bd226c3352f8d55b6f2383e0f74ff9
  Author: Peter Maydell <address@hidden>
  Date:   2014-09-12 (Fri, 12 Sep 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Remove comment about MDSCR_EL1 being dummy implementation

MDSCR_EL1 has actual functionality now; remove the out of date
comment that claims it is a dummy implementation.

Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5e8b12ffbb8c685ee7ee7da1e3d93836c645d671
      
https://github.com/qemu/qemu/commit/5e8b12ffbb8c685ee7ee7da1e3d93836c645d671
  Author: Peter Maydell <address@hidden>
  Date:   2014-09-12 (Fri, 12 Sep 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement minimal DBGVCR, OSDLR_EL1, MDCCSR_EL0

Implement debug registers DBGVCR, OSDLR_EL1 and MDCCSR_EL0
(as dummy or limited-functionality). 32 bit Linux kernels will
access these at startup so they are required for breakpoints
and watchpoints to be supported.

Signed-off-by: Peter Maydell <address@hidden>


  Commit: 995939a650c13ad6ac51db089aeb006e0771ea61
      
https://github.com/qemu/qemu/commit/995939a650c13ad6ac51db089aeb006e0771ea61
  Author: Peter Maydell <address@hidden>
  Date:   2014-09-12 (Fri, 12 Sep 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Push legacy wildcard TLB ops back into v6

When we implemented ARMv8 in QEMU we retained our legacy loose
wildcarded decoding of the TLB maintenance operations for v7
and earlier CPUs and provided the correct stricter decode for
v8. However the loose decode is in fact wrong for v7MP, because
it doesn't correctly implement the operations which must apply
to every CPU in the Inner Shareable domain.

Move the legacy wildcarding from the not_v8 reginfo array
into the not_v7 array, and move the strictly decoded operations
from the v8 reginfo to v7 or v7mp arrays as appropriate.

Cache and TLB lockdown legacy wildcarding remains in the
not_v8 array for the moment.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Cc: address@hidden


  Commit: fa439fc5d7f9094eab4158a906b0e1498504c9cf
      
https://github.com/qemu/qemu/commit/fa439fc5d7f9094eab4158a906b0e1498504c9cf
  Author: Peter Maydell <address@hidden>
  Date:   2014-09-12 (Fri, 12 Sep 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Make *IS TLB maintenance ops affect all CPUs

The ARM architecture defines that the "IS" variants of TLB
maintenance operations must affect all TLBs in the Inner Shareable
domain, which for us means all CPUs. We were incorrectly implementing
these to only affect the current CPU, which meant that SMP TCG
operation was unstable.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Cc: address@hidden


  Commit: 0be969a2d974971628fc4ed95834d22ecf0fd497
      
https://github.com/qemu/qemu/commit/0be969a2d974971628fc4ed95834d22ecf0fd497
  Author: Peter Maydell <address@hidden>
  Date:   2014-09-12 (Fri, 12 Sep 2014)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: fix pl011 and pl031 irq flags

The pl011 and pl031 devices both use level triggered interrupts,
but the device tree we construct was incorrectly telling the
kernel to configure the GIC to treat them as edge triggered.
This meant that output from the pl011 would hang after a while.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Acked-by: Christoffer Dall <address@hidden>
Cc: address@hidden


  Commit: 4c4bf654746eae5a042bde6c150d534d8849b762
      
https://github.com/qemu/qemu/commit/4c4bf654746eae5a042bde6c150d534d8849b762
  Author: Ard Biesheuvel <address@hidden>
  Date:   2014-09-12 (Fri, 12 Sep 2014)

  Changed paths:
    M hw/arm/boot.c

  Log Message:
  -----------
  hw/arm/boot: load DTB as a ROM image

In order to make the device tree blob (DTB) available in memory not only at
first boot, but also after system reset, use rom_blob_add_fixed() to install
it into memory.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Ard Biesheuvel <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: fee8ea12eba366db5ef8f72478cb746bda375d6f
      
https://github.com/qemu/qemu/commit/fee8ea12eba366db5ef8f72478cb746bda375d6f
  Author: Ard Biesheuvel <address@hidden>
  Date:   2014-09-12 (Fri, 12 Sep 2014)

  Changed paths:
    M hw/arm/boot.c

  Log Message:
  -----------
  hw/arm/boot: pass an address limit to and return size from load_dtb()

Add an address limit input parameter to load_dtb() so that we can
tell load_dtb() how much memory the dtb is allowed to consume. If
the dtb doesn't fit, return 0, otherwise return the actual size of
the loaded dtb.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Ard Biesheuvel <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 69e7f76f6a1ed8fe13602c8b5f51cdb6ce3a3981
      
https://github.com/qemu/qemu/commit/69e7f76f6a1ed8fe13602c8b5f51cdb6ce3a3981
  Author: Ard Biesheuvel <address@hidden>
  Date:   2014-09-12 (Fri, 12 Sep 2014)

  Changed paths:
    M hw/arm/boot.c

  Log Message:
  -----------
  hw/arm/boot: load device tree to base of DRAM if no -kernel option was passed

If we are running the 'virt' machine, we may have a device tree blob but no
kernel to supply it to if no -kernel option was passed. In that case, copy it
to the base of RAM where it can be picked up by a bootloader.

Signed-off-by: Ard Biesheuvel <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 92df845070290236d1b28b03453deec1ae9c4263
      
https://github.com/qemu/qemu/commit/92df845070290236d1b28b03453deec1ae9c4263
  Author: Ard Biesheuvel <address@hidden>
  Date:   2014-09-12 (Fri, 12 Sep 2014)

  Changed paths:
    M hw/arm/boot.c

  Log Message:
  -----------
  hw/arm/boot: enable DTB support when booting ELF images

Add support for loading DTB images when booting ELF images using
-kernel. If there are no conflicts with the placement of the ELF
segments, the DTB image is loaded at the base of RAM.

Signed-off-by: Ard Biesheuvel <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4c24f4004089a308c5de8ed720cf6bd1746aedd8
      
https://github.com/qemu/qemu/commit/4c24f4004089a308c5de8ed720cf6bd1746aedd8
  Author: Peter Maydell <address@hidden>
  Date:   2014-09-12 (Fri, 12 Sep 2014)

  Changed paths:
    M cpu-exec.c
    M exec.c
    M hw/arm/boot.c
    M hw/arm/virt.c
    M hw/gpio/pl061.c
    M include/exec/exec-all.h
    M include/qom/cpu.h
    M linux-user/main.c
    M qom/cpu.c
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/helper.c
    M target-arm/internals.h
    M target-arm/machine.c
    M target-arm/op_helper.c
    M target-i386/cpu.c
    M target-i386/cpu.h
    M target-i386/helper.c
    M target-lm32/cpu.c
    M target-lm32/cpu.h
    M target-lm32/helper.c
    M target-xtensa/cpu.c
    M target-xtensa/cpu.h
    M target-xtensa/helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140912' 
into staging

target-arm:
 * add "linux,stdout-path" to the virt DTB
 * fix a long standing bug with IRQ disabling on Cortex-M CPUs
 * implement input interrupt logic in the PL061
 * fix failure to load correct SP/PC on reset of Cortex-M CPUs
   if the vector table is not in a ROM-blob-in-RAM
 * provide flash devices for boot ROMs in the virt board
 * implement architectural watchpoints
 * fix misimplementation of Inner Shareable TLB operations that
   caused instability of guests in TCG SMP configurations
 * configure PL011 and PL031 in the virt board correctly with
   level-triggered interrupts rather than edge-triggered
 * support providing a device tree blob to ROM (firmware)
   images as well as to kernels

# gpg: Signature made Fri 12 Sep 2014 14:19:08 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20140912: (23 commits)
  hw/arm/boot: enable DTB support when booting ELF images
  hw/arm/boot: load device tree to base of DRAM if no -kernel option was passed
  hw/arm/boot: pass an address limit to and return size from load_dtb()
  hw/arm/boot: load DTB as a ROM image
  hw/arm/virt: fix pl011 and pl031 irq flags
  target-arm: Make *IS TLB maintenance ops affect all CPUs
  target-arm: Push legacy wildcard TLB ops back into v6
  target-arm: Implement minimal DBGVCR, OSDLR_EL1, MDCCSR_EL0
  target-arm: Remove comment about MDSCR_EL1 being dummy implementation
  target-arm: Set DBGDSCR.MOE for debug exceptions taken to AArch32
  target-arm: Implement handling of fired watchpoints
  target-arm: Move extended_addresses_enabled() to internals.h
  target-arm: Implement setting of watchpoints
  cpu-exec: Make debug_excp_handler a QOM CPU method
  exec.c: Record watchpoint fault address and direction
  exec.c: Provide full set of dummy wp remove functions in user-mode
  exec.c: Relax restrictions on watchpoint length and alignment
  hw/arm/virt: Provide flash devices for boot ROMs
  target-arm: Fix broken indentation in arm_cpu_reest()
  target-arm: Fix resetting issues on ARMv7-M CPUs
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/6cd14054b677...4c24f4004089