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[Qemu-commits] [qemu/qemu] 05b6ca: target-tricore: fix OPC2_32_RR_DVINIT
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[Qemu-commits] [qemu/qemu] 05b6ca: target-tricore: fix OPC2_32_RR_DVINIT_HU having wr... |
Date: |
Mon, 01 Jun 2015 05:00:06 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 05b6ca9bbcaede74120050aa8e6684300c09257c
https://github.com/qemu/qemu/commit/05b6ca9bbcaede74120050aa8e6684300c09257c
Author: Bastian Koppelmann <address@hidden>
Date: 2015-05-30 (Sat, 30 May 2015)
Changed paths:
M target-tricore/translate.c
Log Message:
-----------
target-tricore: fix OPC2_32_RR_DVINIT_HU having write before use on the result
If the argument r1 was the same as the extended result register r3+1, we would
overwrite r1 and then use it.
Signed-off-by: Bastian Koppelmann <address@hidden>
Message-Id: <address@hidden>
Commit: 9bbd4843c052a0a467c7a3363046b0c95c0e5fc0
https://github.com/qemu/qemu/commit/9bbd4843c052a0a467c7a3363046b0c95c0e5fc0
Author: Bastian Koppelmann <address@hidden>
Date: 2015-05-30 (Sat, 30 May 2015)
Changed paths:
M target-tricore/translate.c
Log Message:
-----------
target-tricore: fix msub32_q producing the wrong overflow bit
The inversion of the overflow bit as a special case, which was needed for the
madd32_q instructions, does not apply for msub32_q instructions. So remove it.
Signed-off-by: Bastian Koppelmann <address@hidden>
Message-Id: <address@hidden>
Commit: 07e15486faf353260431f10e85185372c5036baa
https://github.com/qemu/qemu/commit/07e15486faf353260431f10e85185372c5036baa
Author: Bastian Koppelmann <address@hidden>
Date: 2015-05-30 (Sat, 30 May 2015)
Changed paths:
M target-tricore/translate.c
Log Message:
-----------
target-tricore: fix BOL_ST_H_LONGOFF using ld
Signed-off-by: Bastian Koppelmann <address@hidden>
Message-Id: <address@hidden>
Commit: 9657cafceb90accedd574a3accb3d344def8e764
https://github.com/qemu/qemu/commit/9657cafceb90accedd574a3accb3d344def8e764
Author: Peter Maydell <address@hidden>
Date: 2015-06-01 (Mon, 01 Jun 2015)
Changed paths:
M target-tricore/translate.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/bkoppelmann/tags/pull-tricore-20150530'
into staging
TriCore bugfixes
# gpg: Signature made Sat May 30 15:50:49 2015 BST using RSA key ID 6B69CA14
# gpg: Good signature from "Bastian Koppelmann <address@hidden>"
* remotes/bkoppelmann/tags/pull-tricore-20150530:
target-tricore: fix BOL_ST_H_LONGOFF using ld
target-tricore: fix msub32_q producing the wrong overflow bit
target-tricore: fix OPC2_32_RR_DVINIT_HU having write before use on the result
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/97af820f539e...9657cafceb90
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