[Qemu-commits] [qemu/qemu] ba890a: target-arm: Add the Cortex-M4 CPU

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: ba890a9b2509a0087bb7eafddae02ea5ecbb7bb4
      
https://github.com/qemu/qemu/commit/ba890a9b2509a0087bb7eafddae02ea5ecbb7bb4
  Author: Aurelio C. Remonda <address@hidden>
  Date:   2015-06-19 (Fri, 19 Jun 2015)

  Changed paths:
    M target-arm/cpu.c

  Log Message:
  -----------
  target-arm: Add the Cortex-M4 CPU

This patch adds the Cortex-M4 CPU. The M4 is basically the same as
the M3, the main differences being the DSP instructions and an
optional FPU.  Only no-FPU cortex-M4 is implemented here, cortex-M4F
is not because the core target-arm code doesn't support the M-profile
FPU model yet.

Signed-off-by: Aurelio C. Remonda <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: decf4f807b4498ca35a87e9de82bc9a4e64cc29a
      
https://github.com/qemu/qemu/commit/decf4f807b4498ca35a87e9de82bc9a4e64cc29a
  Author: Eric Auger <address@hidden>
  Date:   2015-06-19 (Fri, 19 Jun 2015)

  Changed paths:
    M hw/arm/sysbus-fdt.c
    M hw/arm/virt.c
    A include/hw/arm/fdt.h

  Log Message:
  -----------
  hw/arm/sysbus-fdt: enable vfio-calxeda-xgmac dynamic instantiation

This patch allows the instantiation of the vfio-calxeda-xgmac device
from the QEMU command line (-device vfio-calxeda-xgmac,host="<device>").

A specialized device tree node is created for the guest, containing
compat, dma-coherent, reg and interrupts properties.

Signed-off-by: Eric Auger <address@hidden>
Acked-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b061a82b8afcc45ce09d770d9c0acdf429401054
      
https://github.com/qemu/qemu/commit/b061a82b8afcc45ce09d770d9c0acdf429401054
  Author: Sergey Fedorov <address@hidden>
  Date:   2015-06-19 (Fri, 19 Jun 2015)

  Changed paths:
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Do not reset sysregs marked as ALIAS

cp_reg_reset() is called from g_hash_table_foreach() which does not
define a specific ordering of the hash table iteration. Thus doing reset
for registers marked as ALIAS would give an ambiguous result when
resetvalue is different for original and alias registers. Exit
cp_reg_reset() early when passed an alias register. Then clean up alias
register definitions from needless resetvalue and resetfn.

In particular, this fixes a bug in the handling of the PMCR register,
which had different resetvalues for its 32 and 64-bit views.

Signed-off-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3281af8114c6b8ead02f08b58e3c36895c1ea047
      
https://github.com/qemu/qemu/commit/3281af8114c6b8ead02f08b58e3c36895c1ea047
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-06-19 (Fri, 19 Jun 2015)

  Changed paths:
    M target-arm/cpu-qom.h
    M target-arm/cpu.c
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm/helper.c: define MPUIR register

Define the MPUIR register for MPU supporting ARMv6 and onwards.
Currently we only support unified MPU.

The size of the unified MPU is defined via the number of "dregions".
So just a single config is added to specify this size. (When split MPU
is implemented we will add an extra iregions config).

Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6cb0b013a1fa421cdfb83257cd33f855cc90649a
      
https://github.com/qemu/qemu/commit/6cb0b013a1fa421cdfb83257cd33f855cc90649a
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-06-19 (Fri, 19 Jun 2015)

  Changed paths:
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/helper.c
    M target-arm/machine.c

  Log Message:
  -----------
  target-arm: Add registers for PMSAv7

Define the arm CP registers for PMSAv7 and their accessor functions.
RGNR serves as a shared index that indexes into arrays storing the
DRBAR, DRSR and DRACR registers. DRBAR and friends have to be VMSDd
separately from the CP interface using a new PMSA specific VMSD
subsection.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f6bda88ff839e2adefe4959b7def420b90703855
      
https://github.com/qemu/qemu/commit/f6bda88ff839e2adefe4959b7def420b90703855
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-06-19 (Fri, 19 Jun 2015)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement PMSAv7 MPU

Unified MPU only. Uses ARM architecture major revision to switch
between PMSAv5 and v7 when ARM_FEATURE_MPU is set. PMSA v6 remains
unsupported and is asserted against.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d6a6b13ea1dfeb25c43a648e94cfe4395906f1da
      
https://github.com/qemu/qemu/commit/d6a6b13ea1dfeb25c43a648e94cfe4395906f1da
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-06-19 (Fri, 19 Jun 2015)

  Changed paths:
    M target-arm/cpu.c

  Log Message:
  -----------
  target-arm: Add support for Cortex-R5

Introduce a CPU model for the Cortex R5 processor. ARMv7 with MPU,
and both thumb and ARM div instructions.

Also implement dummy ATCM and BTCM. These CPs are defined for R5 but
don't have a lot of meaning in QEMU yet. Raz them so the guest can
proceed if they are read. The TCM registers will return a size of 0,
indicating no TCM.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2e5577bc5563ccf453249e884be9a223deabab5b
      
https://github.com/qemu/qemu/commit/2e5577bc5563ccf453249e884be9a223deabab5b
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-06-19 (Fri, 19 Jun 2015)

  Changed paths:
    M hw/arm/xlnx-ep108.c
    M hw/arm/xlnx-zynqmp.c
    M include/hw/arm/xlnx-zynqmp.h

  Log Message:
  -----------
  arm: xlnx-zynqmp: Preface CPU variables with "apu"

The CPUs currently supported by zynqmp are the APU (application
processing unit) CPUs. There are other CPUs in Zynqmp so unqualified
"cpus" in ambiguous. Preface the variables with "APU" accordingly, to
prepare support adding the RPU (realtime processing unit) processors.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6396a193d36e10ff38f26d4ef785aba97362f29e
      
https://github.com/qemu/qemu/commit/6396a193d36e10ff38f26d4ef785aba97362f29e
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-06-19 (Fri, 19 Jun 2015)

  Changed paths:
    M hw/arm/xlnx-ep108.c
    M hw/arm/xlnx-zynqmp.c
    M include/hw/arm/xlnx-zynqmp.h

  Log Message:
  -----------
  arm: xlnx-zynqmp: Add boot-cpu property

Add a string property that specifies the primary boot cpu. All CPUs
except the one selected will start-powered-off. This allows for elf
boots on any CPU, which prepares support for booting R5 elfs directly
on the R5 processors.

Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b58850e79d8df1185bd4999df81fbe6954cd2790
      
https://github.com/qemu/qemu/commit/b58850e79d8df1185bd4999df81fbe6954cd2790
  Author: Peter Crosthwaite <address@hidden>
  Date:   2015-06-19 (Fri, 19 Jun 2015)

  Changed paths:
    M hw/arm/xlnx-zynqmp.c
    M include/hw/arm/xlnx-zynqmp.h

  Log Message:
  -----------
  arm: xlnx-zynqmp: Add 2xCortexR5 CPUs

Add the 2xCortexR5 CPUs to zynqmp board. They are powered off on reset
(this is true of real hardware) by default or selectable as the boot
processor.

Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: cfe67cef48696e8b901aff38a82056ae64d69c98
      
https://github.com/qemu/qemu/commit/cfe67cef48696e8b901aff38a82056ae64d69c98
  Author: Leon Alrae <address@hidden>
  Date:   2015-06-19 (Fri, 19 Jun 2015)

  Changed paths:
    M gdbstub.c
    M include/exec/gdbstub.h
    A include/exec/semihost.h
    M include/sysemu/sysemu.h
    M target-arm/helper.c
    M target-lm32/helper.c
    M target-m68k/op_helper.c
    M target-xtensa/translate.c
    M vl.c

  Log Message:
  -----------
  semihosting: create SemihostingConfig structure and semihost.h

Remove semihosting_enabled and semihosting_target and replace them with
SemihostingConfig structure containing equivalent fields. The structure
is defined in vl.c where it is actually set.

Also introduce separate header file include/exec/semihost.h allowing to
access semihosting config related stuff from target specific semihosting
code.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a59d31a1ebdce796a469242800db89bf09c94580
      
https://github.com/qemu/qemu/commit/a59d31a1ebdce796a469242800db89bf09c94580
  Author: Leon Alrae <address@hidden>
  Date:   2015-06-19 (Fri, 19 Jun 2015)

  Changed paths:
    M include/exec/semihost.h
    M qemu-options.hx
    M target-arm/arm-semi.c
    M vl.c

  Log Message:
  -----------
  semihosting: add --semihosting-config arg sub-argument

Add new "arg" sub-argument to the --semihosting-config allowing the user
to pass multiple input arguments separately. It is required for example
by UHI semihosting to construct argc and argv.

Also, update ARM semihosting to support new option (at the moment it is
the only target which cares about arguments).

If the semihosting is enabled and no semihosting args have been specified,
then fall back to -kernel/-append. The -append string is split on whitespace
before initializing semihosting.argv[1..n]; this is different from what
QEMU MIPS machines' pseudo-bootloaders do (i.e. argv[1] contains the whole
-append), but is more intuitive from UHI user's point of view and Linux
kernel just does not care as it concatenates argv[1..n] into single cmdline
string anyway.

Signed-off-by: Leon Alrae <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 799810fb2810ec4cb82f12ec9b023e1bfe434d71
      
https://github.com/qemu/qemu/commit/799810fb2810ec4cb82f12ec9b023e1bfe434d71
  Author: Peter Maydell <address@hidden>
  Date:   2015-06-19 (Fri, 19 Jun 2015)

  Changed paths:
    M gdbstub.c
    M hw/arm/sysbus-fdt.c
    M hw/arm/virt.c
    M hw/arm/xlnx-ep108.c
    M hw/arm/xlnx-zynqmp.c
    M include/exec/gdbstub.h
    A include/exec/semihost.h
    A include/hw/arm/fdt.h
    M include/hw/arm/xlnx-zynqmp.h
    M include/sysemu/sysemu.h
    M qemu-options.hx
    M target-arm/arm-semi.c
    M target-arm/cpu-qom.h
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/helper.c
    M target-arm/machine.c
    M target-lm32/helper.c
    M target-m68k/op_helper.c
    M target-xtensa/translate.c
    M vl.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150619' 
into staging

target-arm queue:
 * support --semihosting-config,arg=value
 * Cortex-R5 support (including implementing them on the Zynq board)
 * Cortex-M4 support (without FPU)
 * enable vfio-calxeda-xgmac
 * don't reset ALIAS sysregs

# gpg: Signature made Fri Jun 19 14:41:54 2015 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20150619:
  semihosting: add --semihosting-config arg sub-argument
  semihosting: create SemihostingConfig structure and semihost.h
  arm: xlnx-zynqmp: Add 2xCortexR5 CPUs
  arm: xlnx-zynqmp: Add boot-cpu property
  arm: xlnx-zynqmp: Preface CPU variables with "apu"
  target-arm: Add support for Cortex-R5
  target-arm: Implement PMSAv7 MPU
  target-arm: Add registers for PMSAv7
  target-arm/helper.c: define MPUIR register
  target-arm: Do not reset sysregs marked as ALIAS
  hw/arm/sysbus-fdt: enable vfio-calxeda-xgmac dynamic instantiation
  target-arm: Add the Cortex-M4 CPU

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/ffdb1409a79c...799810fb2810