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[PATCH v4 21/33] target/nios2: Use tcg_constant_tl
From: |
Richard Henderson |
Subject: |
[PATCH v4 21/33] target/nios2: Use tcg_constant_tl |
Date: |
Mon, 7 Mar 2022 21:19:53 -1000 |
Replace current uses of tcg_const_tl, and remove the frees.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/translate.c | 36 ++++++++----------------------------
1 file changed, 8 insertions(+), 28 deletions(-)
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 38e16df459..6ff9c18502 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -98,7 +98,6 @@
typedef struct DisasContext {
DisasContextBase base;
- TCGv_i32 zero;
target_ulong pc;
int mem_idx;
const ControlRegState *cr_state;
@@ -124,31 +123,20 @@ static uint8_t get_opxcode(uint32_t code)
return instr.opx;
}
-static TCGv load_zero(DisasContext *dc)
+static TCGv load_gpr(DisasContext *dc, unsigned reg)
{
- if (!dc->zero) {
- dc->zero = tcg_const_i32(0);
- }
- return dc->zero;
-}
-
-static TCGv load_gpr(DisasContext *dc, uint8_t reg)
-{
- if (likely(reg != R_ZERO)) {
- return cpu_R[reg];
- } else {
- return load_zero(dc);
+ assert(reg < NUM_GP_REGS);
+ if (unlikely(reg == R_ZERO)) {
+ return tcg_constant_tl(0);
}
+ return cpu_R[reg];
}
static void t_gen_helper_raise_exception(DisasContext *dc,
uint32_t index)
{
- TCGv_i32 tmp = tcg_const_i32(index);
-
tcg_gen_movi_tl(cpu_pc, dc->pc);
- gen_helper_raise_exception(cpu_env, tmp);
- tcg_temp_free_i32(tmp);
+ gen_helper_raise_exception(cpu_env, tcg_constant_i32(index));
dc->base.is_jmp = DISAS_NORETURN;
}
@@ -675,8 +663,8 @@ static void divu(DisasContext *dc, uint32_t code, uint32_t
flags)
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
- TCGv t2 = tcg_const_tl(0);
- TCGv t3 = tcg_const_tl(1);
+ TCGv t2 = tcg_constant_tl(0);
+ TCGv t3 = tcg_constant_tl(1);
tcg_gen_ext32u_tl(t0, load_gpr(dc, instr.a));
tcg_gen_ext32u_tl(t1, load_gpr(dc, instr.b));
@@ -684,8 +672,6 @@ static void divu(DisasContext *dc, uint32_t code, uint32_t
flags)
tcg_gen_divu_tl(cpu_R[instr.c], t0, t1);
tcg_gen_ext32s_tl(cpu_R[instr.c], cpu_R[instr.c]);
- tcg_temp_free(t3);
- tcg_temp_free(t2);
tcg_temp_free(t1);
tcg_temp_free(t0);
}
@@ -863,14 +849,8 @@ static void nios2_tr_translate_insn(DisasContextBase
*dcbase, CPUState *cs)
return;
}
- dc->zero = NULL;
-
instr = &i_type_instructions[op];
instr->handler(dc, code, instr->flags);
-
- if (dc->zero) {
- tcg_temp_free(dc->zero);
- }
}
static void nios2_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
--
2.25.1
- [PATCH v4 24/33] target/nios2: Introduce shadow register sets, (continued)
- [PATCH v4 24/33] target/nios2: Introduce shadow register sets, Richard Henderson, 2022/03/08
- [PATCH v4 10/33] target/nios2: Clean up nios2_cpu_dump_state, Richard Henderson, 2022/03/08
- [PATCH v4 19/33] target/nios2: Implement CR_STATUS.RSIE, Richard Henderson, 2022/03/08
- [PATCH v4 20/33] target/nios2: Remove CPU_INTERRUPT_NMI, Richard Henderson, 2022/03/08
- [PATCH v4 25/33] target/nios2: Implement rdprs, wrprs, Richard Henderson, 2022/03/08
- [PATCH v4 23/33] target/nios2: Drop CR_STATUS_EH from tb->flags, Richard Henderson, 2022/03/08
- [PATCH v4 21/33] target/nios2: Use tcg_constant_tl,
Richard Henderson <=
- [PATCH v4 28/33] target/nios2: Clean up nios2_cpu_do_interrupt, Richard Henderson, 2022/03/08
- [PATCH v4 11/33] target/nios2: Use hw/registerfields.h for CR_STATUS fields, Richard Henderson, 2022/03/08
- [PATCH v4 14/33] target/nios2: Use hw/registerfields.h for CR_TLBACC fields, Richard Henderson, 2022/03/08
- [PATCH v4 26/33] target/nios2: Update helper_eret for shadow registers, Richard Henderson, 2022/03/08
- [PATCH v4 22/33] target/nios2: Introduce dest_gpr, Richard Henderson, 2022/03/08