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[PULL v2 26/45] hw/intc: Fix upper/lower mtime write calculation
From: |
Alistair Francis |
Subject: |
[PULL v2 26/45] hw/intc: Fix upper/lower mtime write calculation |
Date: |
Mon, 11 Sep 2023 16:43:01 +1000 |
From: Jason Chien <jason.chien@sifive.com>
When writing the upper mtime, we should keep the original lower mtime
whose value is given by cpu_riscv_read_rtc() instead of
cpu_riscv_read_rtc_raw(). The same logic applies to writes to lower mtime.
Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230728082502.26439-1-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/intc/riscv_aclint.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
index b466a6abaf..bf77e29a70 100644
--- a/hw/intc/riscv_aclint.c
+++ b/hw/intc/riscv_aclint.c
@@ -208,11 +208,12 @@ static void riscv_aclint_mtimer_write(void *opaque,
hwaddr addr,
return;
} else if (addr == mtimer->time_base || addr == mtimer->time_base + 4) {
uint64_t rtc_r = cpu_riscv_read_rtc_raw(mtimer->timebase_freq);
+ uint64_t rtc = cpu_riscv_read_rtc(mtimer);
if (addr == mtimer->time_base) {
if (size == 4) {
/* time_lo for RV32/RV64 */
- mtimer->time_delta = ((rtc_r & ~0xFFFFFFFFULL) | value) -
rtc_r;
+ mtimer->time_delta = ((rtc & ~0xFFFFFFFFULL) | value) - rtc_r;
} else {
/* time for RV64 */
mtimer->time_delta = value - rtc_r;
@@ -220,7 +221,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr
addr,
} else {
if (size == 4) {
/* time_hi for RV32/RV64 */
- mtimer->time_delta = (value << 32 | (rtc_r & 0xFFFFFFFF)) -
rtc_r;
+ mtimer->time_delta = (value << 32 | (rtc & 0xFFFFFFFF)) -
rtc_r;
} else {
qemu_log_mask(LOG_GUEST_ERROR,
"aclint-mtimer: invalid time_hi write: %08x",
--
2.41.0
- [PULL v2 16/45] target/riscv: Add Zvkned ISA extension support, (continued)
- [PULL v2 16/45] target/riscv: Add Zvkned ISA extension support, Alistair Francis, 2023/09/11
- [PULL v2 17/45] target/riscv: Add Zvknh ISA extension support, Alistair Francis, 2023/09/11
- [PULL v2 18/45] target/riscv: Add Zvksh ISA extension support, Alistair Francis, 2023/09/11
- [PULL v2 19/45] target/riscv: Add Zvkg ISA extension support, Alistair Francis, 2023/09/11
- [PULL v2 20/45] crypto: Create sm4_subword, Alistair Francis, 2023/09/11
- [PULL v2 21/45] crypto: Add SM4 constant parameter CK, Alistair Francis, 2023/09/11
- [PULL v2 27/45] hw/intc: Make rtc variable names consistent, Alistair Francis, 2023/09/11
- [PULL v2 29/45] target/riscv: support the AIA device emulation with KVM enabled, Alistair Francis, 2023/09/11
- [PULL v2 22/45] target/riscv: Add Zvksed ISA extension support, Alistair Francis, 2023/09/11
- [PULL v2 25/45] target/riscv: Fix zfa fleq.d and fltq.d, Alistair Francis, 2023/09/11
- [PULL v2 26/45] hw/intc: Fix upper/lower mtime write calculation,
Alistair Francis <=
- [PULL v2 23/45] target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren, Alistair Francis, 2023/09/11
- [PULL v2 28/45] linux-user/riscv: Use abi type for target_ucontext, Alistair Francis, 2023/09/11
- [PULL v2 31/45] target/riscv: Create an KVM AIA irqchip, Alistair Francis, 2023/09/11
- [PULL v2 32/45] target/riscv: update APLIC and IMSIC to support KVM AIA, Alistair Francis, 2023/09/11
- [PULL v2 33/45] target/riscv: select KVM AIA in riscv virt machine, Alistair Francis, 2023/09/11
- [PULL v2 35/45] target/riscv: Update CSR bits name for svadu extension, Alistair Francis, 2023/09/11
- [PULL v2 30/45] target/riscv: check the in-kernel irqchip support, Alistair Francis, 2023/09/11
- [PULL v2 34/45] hw/riscv: virt: Fix riscv,pmu DT node path, Alistair Francis, 2023/09/11
- [PULL v2 36/45] target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0, Alistair Francis, 2023/09/11
- [PULL v2 24/45] target/riscv: Add Zihintntl extension ISA string to DTS, Alistair Francis, 2023/09/11