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Re: [PATCH 4/4] docs/cxl: Change to lowercase as others
From: |
Fan Ni |
Subject: |
Re: [PATCH 4/4] docs/cxl: Change to lowercase as others |
Date: |
Tue, 12 Sep 2023 21:26:22 +0000 |
On Mon, Sep 04, 2023 at 02:28:06PM +0100, Jonathan Cameron wrote:
> From: Li Zhijian <lizhijian@cn.fujitsu.com>
>
> Using the same style as elsewhere for topology / topo
>
> Signed-off-by: Li Zhijian <lizhijian@cn.fujitsu.com>
> Link:
> https://urldefense.com/v3/__https://lore.kernel.org/r/20230519085802.2106900-2-lizhijian@cn.fujitsu.com__;!!EwVzqGoTKBqv-0DWAJBm!TWHVrdL5Ys7OOFU_w1CJQ5DC6mxu649kYA9GYDJ182CNPuQqpVkWYsB5mlJpVd_BAAmhxCD4Si2CkMERZI7ZE03kPz2c$
>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
Reviewed-by: Fan Ni <fan.ni@samsung.com>
> docs/system/devices/cxl.rst | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
> index f12011e230..b742120657 100644
> --- a/docs/system/devices/cxl.rst
> +++ b/docs/system/devices/cxl.rst
> @@ -157,7 +157,7 @@ responsible for allocating appropriate ranges from within
> the CFMWs
> and exposing those via normal memory configurations as would be done
> for system RAM.
>
> -Example system Topology. x marks the match in each decoder level::
> +Example system topology. x marks the match in each decoder level::
>
> |<------------------SYSTEM PHYSICAL ADDRESS MAP (1)----------------->|
> | __________ __________________________________ __________ |
> @@ -187,8 +187,8 @@ Example system Topology. x marks the match in each
> decoder level::
> ___________|___ __________|__ __|_________ ___|_________
> (3)| Root Port 0 | | Root Port 1 | | Root Port 2| | Root Port 3 |
> | Appears in | | Appears in | | Appears in | | Appear in |
> - | PCI topology | | PCI Topology| | PCI Topo | | PCI Topo |
> - | As 0c:00.0 | | as 0c:01.0 | | as de:00.0 | | as de:01.0 |
> + | PCI topology | | PCI topology| | PCI topo | | PCI topo |
> + | as 0c:00.0 | | as 0c:01.0 | | as de:00.0 | | as de:01.0 |
> |_______________| |_____________| |____________| |_____________|
> | | | |
> | | | |
> @@ -272,7 +272,7 @@ Example topology involving a switch::
> | Root Port 0 |
> | Appears in |
> | PCI topology |
> - | As 0c:00.0 |
> + | as 0c:00.0 |
> |___________x___|
> |
> |
> --
> 2.39.2
>
- [PATCH 1/4] hw/cxl: Fix CFMW config memory leak, (continued)
- [PATCH 1/4] hw/cxl: Fix CFMW config memory leak, Jonathan Cameron, 2023/09/04
- [PATCH 2/4] hw/pci-bridge/cxl_upstream: Fix bandwidth entry base unit for SSLBIS, Jonathan Cameron, 2023/09/04
- [PATCH 3/4] hw/cxl/cxl_device: Replace magic number in CXLError definition, Jonathan Cameron, 2023/09/04
- [PATCH 4/4] docs/cxl: Change to lowercase as others, Jonathan Cameron, 2023/09/04
- Re: [PATCH 0/4] hw/cxl: Minor CXL emulation fixes and cleanup, Philippe Mathieu-Daudé, 2023/09/13
- Re: [PATCH 0/4] hw/cxl: Minor CXL emulation fixes and cleanup, Michael Tokarev, 2023/09/13