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[PATCH v6 12/57] target/loongarch: check_vec support check LASX instruct
From: |
Song Gao |
Subject: |
[PATCH v6 12/57] target/loongarch: check_vec support check LASX instructions |
Date: |
Thu, 14 Sep 2023 10:26:00 +0800 |
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/cpu.h | 2 ++
target/loongarch/cpu.c | 2 ++
target/loongarch/insn_trans/trans_vec.c.inc | 6 ++++++
3 files changed, 10 insertions(+)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 347ad1c8a9..f125a8e49b 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -462,6 +462,7 @@ static inline void set_pc(CPULoongArchState *env, uint64_t
value)
#define HW_FLAGS_CRMD_PG R_CSR_CRMD_PG_MASK /* 0x10 */
#define HW_FLAGS_EUEN_FPE 0x04
#define HW_FLAGS_EUEN_SXE 0x08
+#define HW_FLAGS_EUEN_ASXE 0x10
#define HW_FLAGS_VA32 0x20
static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc,
@@ -472,6 +473,7 @@ static inline void cpu_get_tb_cpu_state(CPULoongArchState
*env, vaddr *pc,
*flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK);
*flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE;
*flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE;
+ *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_ASXE;
*flags |= is_va32(env) * HW_FLAGS_VA32;
}
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 4d72e905aa..a1d3f680d8 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -55,6 +55,7 @@ static const char * const excp_names[] = {
[EXCCODE_DBP] = "Debug breakpoint",
[EXCCODE_BCE] = "Bound Check Exception",
[EXCCODE_SXD] = "128 bit vector instructions Disable exception",
+ [EXCCODE_ASXD] = "256 bit vector instructions Disable exception",
};
const char *loongarch_exception_name(int32_t exception)
@@ -190,6 +191,7 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
case EXCCODE_FPD:
case EXCCODE_FPE:
case EXCCODE_SXD:
+ case EXCCODE_ASXD:
env->CSR_BADV = env->pc;
QEMU_FALLTHROUGH;
case EXCCODE_BCE:
diff --git a/target/loongarch/insn_trans/trans_vec.c.inc
b/target/loongarch/insn_trans/trans_vec.c.inc
index d8ab7c3417..b5ca65c250 100644
--- a/target/loongarch/insn_trans/trans_vec.c.inc
+++ b/target/loongarch/insn_trans/trans_vec.c.inc
@@ -12,6 +12,12 @@ static bool check_vec(DisasContext *ctx, uint32_t oprsz)
generate_exception(ctx, EXCCODE_SXD);
return false;
}
+
+ if ((oprsz == 32) && ((ctx->base.tb->flags & HW_FLAGS_EUEN_ASXE) == 0)) {
+ generate_exception(ctx, EXCCODE_ASXD);
+ return false;
+ }
+
return true;
}
--
2.39.1
- [PATCH v6 31/57] target/loongarch: Implement xvsigncov, (continued)
- [PATCH v6 31/57] target/loongarch: Implement xvsigncov, Song Gao, 2023/09/13
- [PATCH v6 53/57] target/loongarch: Implement xvpack xvpick xvilv{l/h}, Song Gao, 2023/09/13
- [PATCH v6 28/57] target/loongarch: Implement xvsat, Song Gao, 2023/09/13
- [PATCH v6 16/57] target/loongarch: Implement xvaddi/xvsubi, Song Gao, 2023/09/13
- [PATCH v6 10/57] target/loongarch: Replace CHECK_SXE to check_vec(ctx, 16), Song Gao, 2023/09/13
- [PATCH v6 45/57] target/loongarch: Implement xvfrstp, Song Gao, 2023/09/13
- [PATCH v6 40/57] target/loongarch: Implement xvssrln xvssran, Song Gao, 2023/09/13
- [PATCH v6 47/57] target/loongarch: Implement LASX fpu fcvt instructions, Song Gao, 2023/09/13
- [PATCH v6 29/57] target/loongarch: Implement xvexth, Song Gao, 2023/09/13
- [PATCH v6 49/57] target/loongarch: Implement xvfcmp, Song Gao, 2023/09/13
- [PATCH v6 12/57] target/loongarch: check_vec support check LASX instructions,
Song Gao <=
- [PATCH v6 14/57] target/loongarch: Implement xvadd/xvsub, Song Gao, 2023/09/13
- [PATCH v6 34/57] target/loongarch: Implement LASX logic instructions, Song Gao, 2023/09/13
- [PATCH v6 46/57] target/loongarch: Implement LASX fpu arith instructions, Song Gao, 2023/09/13
- [PATCH v6 55/57] target/loongarch: Implement xvld xvst, Song Gao, 2023/09/13