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[PATCH v4 21/21] i386: Add new property to control L2 cache topo in CPUI
From: |
Zhao Liu |
Subject: |
[PATCH v4 21/21] i386: Add new property to control L2 cache topo in CPUID.04H |
Date: |
Thu, 14 Sep 2023 15:21:59 +0800 |
From: Zhao Liu <zhao1.liu@intel.com>
The property x-l2-cache-topo will be used to change the L2 cache
topology in CPUID.04H.
Now it allows user to set the L2 cache is shared in core level or
cluster level.
If user passes "-cpu x-l2-cache-topo=[core|cluster]" then older L2 cache
topology will be overrode by the new topology setting.
Here we expose to user "cluster" instead of "module", to be consistent
with "cluster-id" naming.
Since CPUID.04H is used by intel CPUs, this property is available on
intel CPUs as for now.
When necessary, it can be extended to CPUID.8000001DH for AMD CPUs.
(Tested the cache topology in CPUID[0x04] leaf with "x-l2-cache-topo=[
core|cluster]", and tested the live migration between the QEMUs w/ &
w/o this patch series.)
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
---
Changes since v3:
* Add description about test for live migration compatibility. (Babu)
Changes since v1:
* Rename MODULE branch to CPU_TOPO_LEVEL_MODULE to match the previous
renaming changes.
---
target/i386/cpu.c | 34 +++++++++++++++++++++++++++++++++-
target/i386/cpu.h | 2 ++
2 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 3bed823dc3b7..b1282c8bd3b7 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -243,6 +243,9 @@ static uint32_t max_processor_ids_for_cache(X86CPUTopoInfo
*topo_info,
case CPU_TOPO_LEVEL_CORE:
num_ids = 1 << apicid_core_offset(topo_info);
break;
+ case CPU_TOPO_LEVEL_MODULE:
+ num_ids = 1 << apicid_module_offset(topo_info);
+ break;
case CPU_TOPO_LEVEL_DIE:
num_ids = 1 << apicid_die_offset(topo_info);
break;
@@ -251,7 +254,7 @@ static uint32_t max_processor_ids_for_cache(X86CPUTopoInfo
*topo_info,
break;
default:
/*
- * Currently there is no use case for SMT and MODULE, so use
+ * Currently there is no use case for SMT, so use
* assert directly to facilitate debugging.
*/
g_assert_not_reached();
@@ -7576,6 +7579,34 @@ static void x86_cpu_realizefn(DeviceState *dev, Error
**errp)
env->cache_info_amd.l3_cache = &legacy_l3_cache;
}
+ if (cpu->l2_cache_topo_level) {
+ /*
+ * FIXME: Currently only supports changing CPUID[4] (for intel), and
+ * will support changing CPUID[0x8000001D] when necessary.
+ */
+ if (!IS_INTEL_CPU(env)) {
+ error_setg(errp, "only intel cpus supports x-l2-cache-topo");
+ return;
+ }
+
+ if (!strcmp(cpu->l2_cache_topo_level, "core")) {
+ env->cache_info_cpuid4.l2_cache->share_level = CPU_TOPO_LEVEL_CORE;
+ } else if (!strcmp(cpu->l2_cache_topo_level, "cluster")) {
+ /*
+ * We expose to users "cluster" instead of "module", to be
+ * consistent with "cluster-id" naming.
+ */
+ env->cache_info_cpuid4.l2_cache->share_level =
+ CPU_TOPO_LEVEL_MODULE;
+ } else {
+ error_setg(errp,
+ "x-l2-cache-topo doesn't support '%s', "
+ "and it only supports 'core' or 'cluster'",
+ cpu->l2_cache_topo_level);
+ return;
+ }
+ }
+
#ifndef CONFIG_USER_ONLY
MachineState *ms = MACHINE(qdev_get_machine());
qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
@@ -8079,6 +8110,7 @@ static Property x86_cpu_properties[] = {
false),
DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level,
true),
+ DEFINE_PROP_STRING("x-l2-cache-topo", X86CPU, l2_cache_topo_level),
DEFINE_PROP_END_OF_LIST()
};
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index a13132007415..05ffc4c1cc6e 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2073,6 +2073,8 @@ struct ArchCPU {
int32_t hv_max_vps;
bool xen_vapic;
+
+ char *l2_cache_topo_level;
};
--
2.34.1
- [PATCH v4 12/21] i386: Expose module level in CPUID[0x1F], (continued)
- [PATCH v4 12/21] i386: Expose module level in CPUID[0x1F], Zhao Liu, 2023/09/14
- [PATCH v4 13/21] i386: Support module_id in X86CPUTopoIDs, Zhao Liu, 2023/09/14
- [PATCH v4 16/21] hw/i386/pc: Support smp.clusters for x86 PC machine, Zhao Liu, 2023/09/14
- [PATCH v4 14/21] i386/cpu: Introduce cluster-id to X86CPU, Zhao Liu, 2023/09/14
- [PATCH v4 15/21] tests: Add test case of APIC ID for module level parsing, Zhao Liu, 2023/09/14
- [PATCH v4 17/21] i386: Add cache topology info in CPUCacheInfo, Zhao Liu, 2023/09/14
- [PATCH v4 18/21] i386: Use CPUCacheInfo.share_level to encode CPUID[4], Zhao Liu, 2023/09/14
- [PATCH v4 19/21] i386: Use offsets get NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14], Zhao Liu, 2023/09/14
- [PATCH v4 21/21] i386: Add new property to control L2 cache topo in CPUID.04H,
Zhao Liu <=
- [PATCH v4 20/21] i386: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 25:14], Zhao Liu, 2023/09/14
- Re: [PATCH v4 00/21] Support smp.clusters for x86 in QEMU, Moger, Babu, 2023/09/22