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[PULL 12/30] target/arm: Implement FEAT_MOPS enable bits
From: |
Peter Maydell |
Subject: |
[PULL 12/30] target/arm: Implement FEAT_MOPS enable bits |
Date: |
Thu, 21 Sep 2023 18:37:02 +0100 |
FEAT_MOPS defines a handful of new enable bits:
* HCRX_EL2.MSCEn, SCTLR_EL1.MSCEn, SCTLR_EL2.MSCen:
define whether the new insns should UNDEF or not
* HCRX_EL2.MCE2: defines whether memops exceptions from
EL1 should be taken to EL1 or EL2
Since we don't sanitise what bits can be written for the SCTLR
registers, we only need to handle the new bits in HCRX_EL2, and
define SCTLR_MSCEN for the new SCTLR bit value.
The precedence of "HCRX bits acts as 0 if SCR_EL3.HXEn is 0" versus
"bit acts as 1 if EL2 disabled" is not clear from the register
definition text, but it is clear in the CheckMOPSEnabled()
pseudocode(), so we follow that. We'll have to check whether other
bits we need to implement in future follow the same logic or not.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230912140434.1333369-3-peter.maydell@linaro.org
---
target/arm/cpu.h | 6 ++++++
target/arm/helper.c | 28 +++++++++++++++++++++-------
2 files changed, 27 insertions(+), 7 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index bc7a69a8753..266c1a9ea1b 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1315,6 +1315,7 @@ void pmu_init(ARMCPU *cpu);
#define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */
#define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */
#define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */
+#define SCTLR_MSCEN (1ULL << 33) /* FEAT_MOPS */
#define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */
#define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */
#define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */
@@ -4281,6 +4282,11 @@ static inline bool isar_feature_aa64_doublelock(const
ARMISARegisters *id)
return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0;
}
+static inline bool isar_feature_aa64_mops(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, MOPS);
+}
+
/*
* Feature tests for "does this exist in either 32-bit or 64-bit?"
*/
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 594985d7c8c..83620787b45 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5980,7 +5980,10 @@ static void hcrx_write(CPUARMState *env, const
ARMCPRegInfo *ri,
{
uint64_t valid_mask = 0;
- /* No features adding bits to HCRX are implemented. */
+ /* FEAT_MOPS adds MSCEn and MCE2 */
+ if (cpu_isar_feature(aa64_mops, env_archcpu(env))) {
+ valid_mask |= HCRX_MSCEN | HCRX_MCE2;
+ }
/* Clear RES0 bits. */
env->cp15.hcrx_el2 = value & valid_mask;
@@ -6009,13 +6012,24 @@ uint64_t arm_hcrx_el2_eff(CPUARMState *env)
{
/*
* The bits in this register behave as 0 for all purposes other than
- * direct reads of the register if:
- * - EL2 is not enabled in the current security state,
- * - SCR_EL3.HXEn is 0.
+ * direct reads of the register if SCR_EL3.HXEn is 0.
+ * If EL2 is not enabled in the current security state, then the
+ * bit may behave as if 0, or as if 1, depending on the bit.
+ * For the moment, we treat the EL2-disabled case as taking
+ * priority over the HXEn-disabled case. This is true for the only
+ * bit for a feature which we implement where the answer is different
+ * for the two cases (MSCEn for FEAT_MOPS).
+ * This may need to be revisited for future bits.
*/
- if (!arm_is_el2_enabled(env)
- || (arm_feature(env, ARM_FEATURE_EL3)
- && !(env->cp15.scr_el3 & SCR_HXEN))) {
+ if (!arm_is_el2_enabled(env)) {
+ uint64_t hcrx = 0;
+ if (cpu_isar_feature(aa64_mops, env_archcpu(env))) {
+ /* MSCEn behaves as 1 if EL2 is not enabled */
+ hcrx |= HCRX_MSCEN;
+ }
+ return hcrx;
+ }
+ if (arm_feature(env, ARM_FEATURE_EL3) && !(env->cp15.scr_el3 & SCR_HXEN)) {
return 0;
}
return env->cp15.hcrx_el2;
--
2.34.1
- [PULL 00/30] target-arm queue, Peter Maydell, 2023/09/21
- [PULL 02/30] docs/devel/loads-stores: Fix git grep regexes, Peter Maydell, 2023/09/21
- [PULL 01/30] target/m68k: Add URL to semihosting spec, Peter Maydell, 2023/09/21
- [PULL 07/30] target/arm: Update AArch64 ID register field definitions, Peter Maydell, 2023/09/21
- [PULL 11/30] target/arm: Don't skip MTE checks for LDRT/STRT at EL0, Peter Maydell, 2023/09/21
- [PULL 09/30] target/arm: Implement FEAT_HBC, Peter Maydell, 2023/09/21
- [PULL 04/30] linux-user/elfload.c: Correct SME feature names reported in cpuinfo, Peter Maydell, 2023/09/21
- [PULL 03/30] hw/arm/boot: Set SCR_EL3.FGTEn when booting kernel, Peter Maydell, 2023/09/21
- [PULL 08/30] target/arm: Update user-mode ID reg mask values, Peter Maydell, 2023/09/21
- [PULL 10/30] target/arm: Remove unused allocation_tag_mem() argument, Peter Maydell, 2023/09/21
- [PULL 12/30] target/arm: Implement FEAT_MOPS enable bits,
Peter Maydell <=
- [PULL 14/30] target/arm: Define syndrome function for MOPS exceptions, Peter Maydell, 2023/09/21
- [PULL 17/30] target/arm: Implement the SET* instructions, Peter Maydell, 2023/09/21
- [PULL 05/30] linux-user/elfload.c: Add missing arm and arm64 hwcap values, Peter Maydell, 2023/09/21
- [PULL 19/30] target/arm: Implement the SETG* instructions, Peter Maydell, 2023/09/21
- [PULL 20/30] target/arm: Implement MTE tag-checking functions for FEAT_MOPS copies, Peter Maydell, 2023/09/21
- [PULL 16/30] target/arm: Implement MTE tag-checking functions for FEAT_MOPS, Peter Maydell, 2023/09/21
- [PULL 13/30] target/arm: Pass unpriv bool to get_a64_user_mem_index(), Peter Maydell, 2023/09/21
- [PULL 06/30] linux-user/elfload.c: Report previously missing arm32 hwcaps, Peter Maydell, 2023/09/21
- [PULL 23/30] audio/jackaudio: Avoid dynamic stack allocation in qjack_client_init, Peter Maydell, 2023/09/21
- [PULL 21/30] target/arm: Implement the CPY* instructions, Peter Maydell, 2023/09/21