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[PULL v2 30/53] hw/i386/acpi-build: Determine SMI command port just once
From: |
Michael S. Tsirkin |
Subject: |
[PULL v2 30/53] hw/i386/acpi-build: Determine SMI command port just once |
Date: |
Wed, 4 Oct 2023 23:44:28 -0400 |
From: Bernhard Beschow <shentey@gmail.com>
The SMI command port is currently hardcoded by means of the ACPI_PORT_SMI_CMD
macro. This hardcoding is Intel specific and doesn't match VIA, for example.
There is already the AcpiFadtData::smi_cmd attribute which is used when building
the FADT. Let's also use it when building the DSDT which confines SMI command
port determination to just one place. This allows it to become a property later,
thus resolving the Intel assumption.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230908084234.17642-7-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/i386/acpi-build.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 76581d51aa..863a939210 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1495,14 +1495,14 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
aml_append(crs,
aml_io(
AML_DECODE16,
- ACPI_PORT_SMI_CMD,
- ACPI_PORT_SMI_CMD,
+ pm->fadt.smi_cmd,
+ pm->fadt.smi_cmd,
1,
2)
);
aml_append(dev, aml_name_decl("_CRS", crs));
aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO,
- aml_int(ACPI_PORT_SMI_CMD), 2));
+ aml_int(pm->fadt.smi_cmd), 2));
field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK,
AML_WRITE_AS_ZEROS);
aml_append(field, aml_named_field("SMIC", 8));
--
MST
- [PULL v2 25/53] hw/i386/acpi-build: Use pc_madt_cpu_entry() directly, (continued)
[PULL v2 31/53] hw/acpi: Trace GPE access in all device models, not just PIIX4, Michael S. Tsirkin, 2023/10/04
[PULL v2 30/53] hw/i386/acpi-build: Determine SMI command port just once,
Michael S. Tsirkin <=
[PULL v2 32/53] hw/acpi/core: Trace enable and status registers of GPE separately, Michael S. Tsirkin, 2023/10/04
[PULL v2 34/53] vdpa net: zero vhost_vdpa iova_tree pointer at cleanup, Michael S. Tsirkin, 2023/10/04
[PULL v2 33/53] vdpa: fix gcc cvq_isolated uninitialized variable warning, Michael S. Tsirkin, 2023/10/04
[PULL v2 40/53] vdpa net: fix error message setting virtio status, Michael S. Tsirkin, 2023/10/04
[PULL v2 45/53] pcie_sriov: unregister_vfs(): fix error path, Michael S. Tsirkin, 2023/10/04
[PULL v2 39/53] hw/pci-bridge/cxl-upstream: Add serial number extended capability support, Michael S. Tsirkin, 2023/10/04
[PULL v2 42/53] vdpa net: follow VirtIO initialization properly at cvq isolation probing, Michael S. Tsirkin, 2023/10/04
[PULL v2 36/53] hw/cxl: Add utility functions decoder interleave ways and target count., Michael S. Tsirkin, 2023/10/04
[PULL v2 37/53] hw/cxl: Fix and use same calculation for HDM decoder block size everywhere, Michael S. Tsirkin, 2023/10/04
[PULL v2 35/53] hw/cxl: Push cxl_decoder_count_enc() and cxl_decode_ig() into .c, Michael S. Tsirkin, 2023/10/04