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[PATCH v8 12/29] hw/isa/piix3: Create USB controller in host device
From: |
Bernhard Beschow |
Subject: |
[PATCH v8 12/29] hw/isa/piix3: Create USB controller in host device |
Date: |
Sat, 7 Oct 2023 14:38:20 +0200 |
The USB controller is an integral part of PIIX3 (function 2). So create
it as part of the south bridge.
Note that the USB function is optional in QEMU. This is why it gets
object_initialize_child()'ed in realize rather than in instance_init.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/southbridge/piix.h | 4 ++++
hw/i386/pc_piix.c | 7 ++-----
hw/isa/piix3.c | 16 ++++++++++++++++
hw/isa/Kconfig | 1 +
4 files changed, 23 insertions(+), 5 deletions(-)
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index 1daeff397c..5cd866f1f2 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -15,6 +15,7 @@
#include "hw/pci/pci_device.h"
#include "hw/ide/pci.h"
#include "hw/rtc/mc146818rtc.h"
+#include "hw/usb/hcd-uhci.h"
/* PIRQRC[A:D]: PIRQx Route Control Registers */
#define PIIX_PIRQCA 0x60
@@ -54,12 +55,15 @@ struct PIIXState {
MC146818RtcState rtc;
PCIIDEState ide;
+ UHCIState uhci;
/* Reset Control Register contents */
uint8_t rcr;
/* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */
MemoryRegion rcr_mem;
+
+ bool has_usb;
};
typedef struct PIIXState PIIX3State;
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index c98a997482..8dcd6851d0 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -51,7 +51,6 @@
#include "exec/memory.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/piix4.h"
-#include "hw/usb/hcd-uhci.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "sysemu/xen.h"
@@ -265,6 +264,8 @@ static void pc_init1(MachineState *machine,
size_t i;
pci_dev = pci_new_multifunction(-1, TYPE_PIIX3_DEVICE);
+ object_property_set_bool(OBJECT(pci_dev), "has-usb",
+ machine_usb(machine), &error_abort);
dev = DEVICE(pci_dev);
for (i = 0; i < ISA_NUM_IRQS; i++) {
qdev_connect_gpio_out_named(dev, "isa-irqs", i, x86ms->gsi[i]);
@@ -359,10 +360,6 @@ static void pc_init1(MachineState *machine,
}
#endif
- if (pcmc->pci_enabled && machine_usb(machine)) {
- pci_create_simple(pci_bus, piix3_devfn + 2, TYPE_PIIX3_USB_UHCI);
- }
-
if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
PCIDevice *piix4_pm;
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index 3f1dabade0..aebc0da23b 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -298,6 +298,16 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp)
if (!qdev_realize(DEVICE(&d->ide), BUS(pci_bus), errp)) {
return;
}
+
+ /* USB */
+ if (d->has_usb) {
+ object_initialize_child(OBJECT(dev), "uhci", &d->uhci,
+ TYPE_PIIX3_USB_UHCI);
+ qdev_prop_set_int32(DEVICE(&d->uhci), "addr", dev->devfn + 2);
+ if (!qdev_realize(DEVICE(&d->uhci), BUS(pci_bus), errp)) {
+ return;
+ }
+ }
}
static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
@@ -332,6 +342,11 @@ static void pci_piix3_init(Object *obj)
object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE);
}
+static Property pci_piix3_props[] = {
+ DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void pci_piix3_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -352,6 +367,7 @@ static void pci_piix3_class_init(ObjectClass *klass, void
*data)
* pc_piix.c's pc_init1()
*/
dc->user_creatable = false;
+ device_class_set_props(dc, pci_piix3_props);
adevc->build_dev_aml = build_pci_isa_aml;
}
diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig
index 28345edbb3..1076df69ca 100644
--- a/hw/isa/Kconfig
+++ b/hw/isa/Kconfig
@@ -37,6 +37,7 @@ config PIIX3
select IDE_PIIX
select ISA_BUS
select MC146818RTC
+ select USB_UHCI
config PIIX4
bool
--
2.42.0
- [PATCH v8 10/29] hw/i386/pc: Wire RTC ISA IRQs in south bridges, (continued)
- [PATCH v8 10/29] hw/i386/pc: Wire RTC ISA IRQs in south bridges, Bernhard Beschow, 2023/10/07
- [PATCH v8 04/29] hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS, Bernhard Beschow, 2023/10/07
- [PATCH v8 18/29] hw/isa/piix4: Reuse struct PIIXState from PIIX3, Bernhard Beschow, 2023/10/07
- [PATCH v8 14/29] hw/isa/piix3: Drop the "3" from PIIX base class name, Bernhard Beschow, 2023/10/07
- [PATCH v8 13/29] hw/isa/piix3: Create power management controller in host device, Bernhard Beschow, 2023/10/07
- [PATCH v8 21/29] hw/isa/piix: Allow for optional PIT creation in PIIX3, Bernhard Beschow, 2023/10/07
- [PATCH v8 16/29] hw/isa/piix4: Rename "isa" attribute to "isa_irqs_in", Bernhard Beschow, 2023/10/07
- [PATCH v8 23/29] hw/isa/piix: Share PIIX3's base class with PIIX4, Bernhard Beschow, 2023/10/07
- [PATCH v8 24/29] hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4, Bernhard Beschow, 2023/10/07
- [PATCH v8 25/29] hw/isa/piix: Rename functions to be shared for PCI interrupt triggering, Bernhard Beschow, 2023/10/07
- [PATCH v8 12/29] hw/isa/piix3: Create USB controller in host device,
Bernhard Beschow <=
- [PATCH v8 26/29] hw/isa/piix: Reuse PIIX3's PCI interrupt triggering in PIIX4, Bernhard Beschow, 2023/10/07
- [PATCH v8 22/29] hw/isa/piix: Harmonize names of reset control memory regions, Bernhard Beschow, 2023/10/07
- [PATCH v8 28/29] hw/isa/piix: Implement multi-process QEMU support also for PIIX4, Bernhard Beschow, 2023/10/07
- [PATCH v8 19/29] hw/isa/piix3: Merge hw/isa/piix4.c, Bernhard Beschow, 2023/10/07
- [PATCH v8 20/29] hw/isa/piix: Allow for optional PIC creation in PIIX3, Bernhard Beschow, 2023/10/07
- [PATCH v8 29/29] hw/i386/pc_piix: Make PIIX4 south bridge usable in PC machine, Bernhard Beschow, 2023/10/07
- [PATCH v8 17/29] hw/isa/piix4: Rename reset control operations to match PIIX3, Bernhard Beschow, 2023/10/07
- [PATCH v8 15/29] hw/isa/piix4: Remove unused inbound ISA interrupt lines, Bernhard Beschow, 2023/10/07
- [PATCH v8 27/29] hw/isa/piix: Resolve duplicate code regarding PCI interrupt wiring, Bernhard Beschow, 2023/10/07
- Re: [PATCH v8 00/29] Consolidate PIIX south bridges, Chuck Zmudzinski, 2023/10/08