[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 14/54] target/riscv: make CPUCFG() macro public
From: |
Alistair Francis |
Subject: |
[PULL 14/54] target/riscv: make CPUCFG() macro public |
Date: |
Thu, 12 Oct 2023 14:10:11 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
The RISC-V KVM driver uses a CPUCFG() macro that calculates the offset
of a certain field in the struct RISCVCPUConfig. We're going to use this
macro in target/riscv/cpu.c as well in the next patches. Make it public.
Rename it to CPU_CFG_OFFSET() for more clarity while we're at it.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230912132423.268494-15-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu.c | 2 +-
target/riscv/kvm.c | 8 +++-----
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index ef9cf21c0c..cce6dee729 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -62,6 +62,8 @@
const char *riscv_get_misa_ext_name(uint32_t bit);
const char *riscv_get_misa_ext_description(uint32_t bit);
+#define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop)
+
/* Privileged specification version */
enum {
PRIV_VERSION_1_10_0 = 0,
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5287569e5a..7544fff392 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -48,7 +48,7 @@ struct isa_ext_data {
};
#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
- {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)}
+ {#_name, _min_ver, CPU_CFG_OFFSET(_prop)}
/*
* From vector_helper.c
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index c01cfb03f4..14763ec0cd 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -205,10 +205,8 @@ static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu,
CPUState *cs)
}
}
-#define CPUCFG(_prop) offsetof(struct RISCVCPUConfig, _prop)
-
#define KVM_EXT_CFG(_name, _prop, _reg_id) \
- {.name = _name, .offset = CPUCFG(_prop), \
+ {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
.kvm_reg_id = _reg_id}
static KVMCPUConfig kvm_multi_ext_cfgs[] = {
@@ -285,13 +283,13 @@ static void kvm_cpu_set_multi_ext_cfg(Object *obj,
Visitor *v,
static KVMCPUConfig kvm_cbom_blocksize = {
.name = "cbom_blocksize",
- .offset = CPUCFG(cbom_blocksize),
+ .offset = CPU_CFG_OFFSET(cbom_blocksize),
.kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicbom_block_size)
};
static KVMCPUConfig kvm_cboz_blocksize = {
.name = "cboz_blocksize",
- .offset = CPUCFG(cboz_blocksize),
+ .offset = CPU_CFG_OFFSET(cboz_blocksize),
.kvm_reg_id = KVM_REG_RISCV_CONFIG_REG(zicboz_block_size)
};
--
2.41.0
- [PULL 02/54] target/riscv/cpu.c: skip 'bool' check when filtering KVM props, (continued)
- [PULL 02/54] target/riscv/cpu.c: skip 'bool' check when filtering KVM props, Alistair Francis, 2023/10/12
- [PULL 03/54] target/riscv/cpu.c: split kvm prop handling to its own helper, Alistair Francis, 2023/10/12
- [PULL 04/54] target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[], Alistair Francis, 2023/10/12
- [PULL 05/54] target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[], Alistair Francis, 2023/10/12
- [PULL 08/54] target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array(), Alistair Francis, 2023/10/12
- [PULL 07/54] target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array(), Alistair Francis, 2023/10/12
- [PULL 11/54] avocado, risc-v: add tuxboot tests for 'max' CPU, Alistair Francis, 2023/10/12
- [PULL 10/54] target/riscv: add 'max' CPU type, Alistair Francis, 2023/10/12
- [PULL 12/54] target/riscv: deprecate the 'any' CPU type, Alistair Francis, 2023/10/12
- [PULL 13/54] target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled, Alistair Francis, 2023/10/12
- [PULL 14/54] target/riscv: make CPUCFG() macro public,
Alistair Francis <=
- [PULL 06/54] target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[], Alistair Francis, 2023/10/12
- [PULL 09/54] target/riscv/cpu.c: limit cfg->vext_spec log message, Alistair Francis, 2023/10/12
- [PULL 16/54] target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize(), Alistair Francis, 2023/10/12
- [PULL 15/54] target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update(), Alistair Francis, 2023/10/12
- [PULL 17/54] target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig, Alistair Francis, 2023/10/12
- [PULL 18/54] target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions(), Alistair Francis, 2023/10/12
- [PULL 19/54] target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update(), Alistair Francis, 2023/10/12
- [PULL 20/54] target/riscv/cpu.c: consider user option with RVG, Alistair Francis, 2023/10/12
- [PULL 21/54] target/riscv: Clear CSR values at reset and sync MPSTATE with host, Alistair Francis, 2023/10/12
- [PULL 22/54] disas/riscv: Fix the typo of inverted order of pmpaddr13 and pmpaddr14, Alistair Francis, 2023/10/12