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[PULL 16/54] target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during re
From: |
Alistair Francis |
Subject: |
[PULL 16/54] target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize() |
Date: |
Thu, 12 Oct 2023 14:10:13 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Let's change the other instances in realize() where we're enabling an
extension based on a certain criteria (e.g. it's a dependency of another
extension).
We're leaving icsr and ifencei being enabled during RVG for later -
we'll want to error out in that case. Every other extension enablement
during realize is now done via cpu_cfg_ext_auto_update().
The end goal is that only cpu init() functions will handle extension
flags directly via "cpu->cfg.ext_N = true|false".
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230912132423.268494-17-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 50 +++++++++++++++++++++++-----------------------
1 file changed, 25 insertions(+), 25 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index bd73b61d3c..25fef13ef0 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1193,7 +1193,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,
Error **errp)
}
if (cpu->cfg.ext_zfh) {
- cpu->cfg.ext_zfhmin = true;
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true);
}
if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) {
@@ -1219,17 +1219,17 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,
Error **errp)
}
/* The V vector extension depends on the Zve64d extension */
- cpu->cfg.ext_zve64d = true;
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true);
}
/* The Zve64d extension depends on the Zve64f extension */
if (cpu->cfg.ext_zve64d) {
- cpu->cfg.ext_zve64f = true;
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
}
/* The Zve64f extension depends on the Zve32f extension */
if (cpu->cfg.ext_zve64f) {
- cpu->cfg.ext_zve32f = true;
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
}
if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
@@ -1243,7 +1243,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,
Error **errp)
}
if (cpu->cfg.ext_zvfh) {
- cpu->cfg.ext_zvfhmin = true;
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true);
}
if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) {
@@ -1273,7 +1273,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,
Error **errp)
/* Set the ISA extensions, checks should have happened above */
if (cpu->cfg.ext_zhinx) {
- cpu->cfg.ext_zhinxmin = true;
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
}
if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
@@ -1294,12 +1294,12 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,
Error **errp)
}
if (cpu->cfg.ext_zce) {
- cpu->cfg.ext_zca = true;
- cpu->cfg.ext_zcb = true;
- cpu->cfg.ext_zcmp = true;
- cpu->cfg.ext_zcmt = true;
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);
if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
- cpu->cfg.ext_zcf = true;
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
}
}
@@ -1367,26 +1367,26 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,
Error **errp)
}
if (cpu->cfg.ext_zk) {
- cpu->cfg.ext_zkn = true;
- cpu->cfg.ext_zkr = true;
- cpu->cfg.ext_zkt = true;
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true);
}
if (cpu->cfg.ext_zkn) {
- cpu->cfg.ext_zbkb = true;
- cpu->cfg.ext_zbkc = true;
- cpu->cfg.ext_zbkx = true;
- cpu->cfg.ext_zkne = true;
- cpu->cfg.ext_zknd = true;
- cpu->cfg.ext_zknh = true;
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true);
}
if (cpu->cfg.ext_zks) {
- cpu->cfg.ext_zbkb = true;
- cpu->cfg.ext_zbkc = true;
- cpu->cfg.ext_zbkx = true;
- cpu->cfg.ext_zksed = true;
- cpu->cfg.ext_zksh = true;
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true);
}
/*
--
2.41.0
- [PULL 05/54] target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[], (continued)
- [PULL 05/54] target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[], Alistair Francis, 2023/10/12
- [PULL 08/54] target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array(), Alistair Francis, 2023/10/12
- [PULL 07/54] target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array(), Alistair Francis, 2023/10/12
- [PULL 11/54] avocado, risc-v: add tuxboot tests for 'max' CPU, Alistair Francis, 2023/10/12
- [PULL 10/54] target/riscv: add 'max' CPU type, Alistair Francis, 2023/10/12
- [PULL 12/54] target/riscv: deprecate the 'any' CPU type, Alistair Francis, 2023/10/12
- [PULL 13/54] target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled, Alistair Francis, 2023/10/12
- [PULL 14/54] target/riscv: make CPUCFG() macro public, Alistair Francis, 2023/10/12
- [PULL 06/54] target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[], Alistair Francis, 2023/10/12
- [PULL 09/54] target/riscv/cpu.c: limit cfg->vext_spec log message, Alistair Francis, 2023/10/12
- [PULL 16/54] target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize(),
Alistair Francis <=
- [PULL 15/54] target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update(), Alistair Francis, 2023/10/12
- [PULL 17/54] target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig, Alistair Francis, 2023/10/12
- [PULL 18/54] target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions(), Alistair Francis, 2023/10/12
- [PULL 19/54] target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update(), Alistair Francis, 2023/10/12
- [PULL 20/54] target/riscv/cpu.c: consider user option with RVG, Alistair Francis, 2023/10/12
- [PULL 21/54] target/riscv: Clear CSR values at reset and sync MPSTATE with host, Alistair Francis, 2023/10/12
- [PULL 22/54] disas/riscv: Fix the typo of inverted order of pmpaddr13 and pmpaddr14, Alistair Francis, 2023/10/12
- [PULL 23/54] target/riscv: introduce TCG AccelCPUClass, Alistair Francis, 2023/10/12
- [PULL 24/54] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn(), Alistair Francis, 2023/10/12
- [PULL 26/54] target/riscv: move riscv_tcg_ops to tcg-cpu.c, Alistair Francis, 2023/10/12