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[PULL 20/54] target/riscv/cpu.c: consider user option with RVG
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From: |
Alistair Francis |
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Subject: |
[PULL 20/54] target/riscv/cpu.c: consider user option with RVG |
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Date: |
Thu, 12 Oct 2023 14:10:17 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Enabling RVG will enable a set of extensions that we're not checking if
the user was okay enabling or not. And in this case we want to error
out, instead of ignoring, otherwise we will be inconsistent enabling RVG
without all its extensions.
After this patch, disabling ifencei or icsr while enabling RVG will
result in error:
$ ./build/qemu-system-riscv64 -M virt -cpu rv64,g=true,Zifencei=false
--nographic
qemu-system-riscv64: RVG requires Zifencei but user set Zifencei to false
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230912132423.268494-21-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d1a3ddadd0..383e5df2a7 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1153,9 +1153,23 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,
Error **errp)
riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
riscv_has_ext(env, RVD) &&
cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
+
+ if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) &&
+ !cpu->cfg.ext_icsr) {
+ error_setg(errp, "RVG requires Zicsr but user set Zicsr to false");
+ return;
+ }
+
+ if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) &&
+ !cpu->cfg.ext_ifencei) {
+ error_setg(errp, "RVG requires Zifencei but user set "
+ "Zifencei to false");
+ return;
+ }
+
warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
- cpu->cfg.ext_icsr = true;
- cpu->cfg.ext_ifencei = true;
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true);
env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD;
--
2.41.0
- [PULL 12/54] target/riscv: deprecate the 'any' CPU type, (continued)
- [PULL 12/54] target/riscv: deprecate the 'any' CPU type, Alistair Francis, 2023/10/12
- [PULL 13/54] target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled, Alistair Francis, 2023/10/12
- [PULL 14/54] target/riscv: make CPUCFG() macro public, Alistair Francis, 2023/10/12
- [PULL 06/54] target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[], Alistair Francis, 2023/10/12
- [PULL 09/54] target/riscv/cpu.c: limit cfg->vext_spec log message, Alistair Francis, 2023/10/12
- [PULL 16/54] target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize(), Alistair Francis, 2023/10/12
- [PULL 15/54] target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update(), Alistair Francis, 2023/10/12
- [PULL 17/54] target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig, Alistair Francis, 2023/10/12
- [PULL 18/54] target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions(), Alistair Francis, 2023/10/12
- [PULL 19/54] target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update(), Alistair Francis, 2023/10/12
- [PULL 20/54] target/riscv/cpu.c: consider user option with RVG,
Alistair Francis <=
- [PULL 21/54] target/riscv: Clear CSR values at reset and sync MPSTATE with host, Alistair Francis, 2023/10/12
- [PULL 22/54] disas/riscv: Fix the typo of inverted order of pmpaddr13 and pmpaddr14, Alistair Francis, 2023/10/12
- [PULL 23/54] target/riscv: introduce TCG AccelCPUClass, Alistair Francis, 2023/10/12
- [PULL 24/54] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn(), Alistair Francis, 2023/10/12
- [PULL 26/54] target/riscv: move riscv_tcg_ops to tcg-cpu.c, Alistair Francis, 2023/10/12
- [PULL 25/54] target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c, Alistair Francis, 2023/10/12
- [PULL 27/54] target/riscv/cpu.c: add .instance_post_init(), Alistair Francis, 2023/10/12
- [PULL 28/54] target/riscv: move 'host' CPU declaration to kvm.c, Alistair Francis, 2023/10/12
- [PULL 29/54] target/riscv/cpu.c: mark extensions arrays as 'const', Alistair Francis, 2023/10/12
- [PULL 30/54] target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c, Alistair Francis, 2023/10/12