[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 27/54] target/riscv/cpu.c: add .instance_post_init()
From: |
Alistair Francis |
Subject: |
[PULL 27/54] target/riscv/cpu.c: add .instance_post_init() |
Date: |
Thu, 12 Oct 2023 14:10:24 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
All generic CPUs call riscv_cpu_add_user_properties(). The 'max' CPU
calls riscv_init_max_cpu_extensions(). Both can be moved to a common
instance_post_init() callback, implemented in riscv_cpu_post_init(),
called by all CPUs. The call order then becomes:
riscv_cpu_init() -> cpu_init() of each CPU -> .instance_post_init()
In the near future riscv_cpu_post_init() will call the init() function
of the current accelerator, providing a hook for KVM and TCG accel
classes to change the init() process of the CPU.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230925175709.35696-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 43 ++++++++++++++++++++++++++++++++-----------
1 file changed, 32 insertions(+), 11 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 08cbd51ea1..a6a26c0268 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -427,8 +427,6 @@ static void riscv_max_cpu_init(Object *obj)
mlx = MXL_RV32;
#endif
set_misa(env, mlx, 0);
- riscv_cpu_add_user_properties(obj);
- riscv_init_max_cpu_extensions(obj);
env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
@@ -442,7 +440,6 @@ static void rv64_base_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
set_misa(env, MXL_RV64, 0);
- riscv_cpu_add_user_properties(obj);
/* Set latest version of privileged specification */
env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY
@@ -566,7 +563,6 @@ static void rv128_base_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
set_misa(env, MXL_RV128, 0);
- riscv_cpu_add_user_properties(obj);
/* Set latest version of privileged specification */
env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY
@@ -579,7 +575,6 @@ static void rv32_base_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
set_misa(env, MXL_RV32, 0);
- riscv_cpu_add_user_properties(obj);
/* Set latest version of privileged specification */
env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY
@@ -666,7 +661,6 @@ static void riscv_host_cpu_init(Object *obj)
#elif defined(TARGET_RISCV64)
set_misa(env, MXL_RV64, 0);
#endif
- riscv_cpu_add_user_properties(obj);
}
#endif /* CONFIG_KVM */
@@ -1215,6 +1209,37 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int
level)
}
#endif /* CONFIG_USER_ONLY */
+static bool riscv_cpu_is_dynamic(Object *cpu_obj)
+{
+ return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
+}
+
+static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
+{
+ return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
+}
+
+static bool riscv_cpu_has_user_properties(Object *cpu_obj)
+{
+ if (kvm_enabled() &&
+ object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_HOST) != NULL) {
+ return true;
+ }
+
+ return riscv_cpu_is_dynamic(cpu_obj);
+}
+
+static void riscv_cpu_post_init(Object *obj)
+{
+ if (riscv_cpu_has_user_properties(obj)) {
+ riscv_cpu_add_user_properties(obj);
+ }
+
+ if (riscv_cpu_has_max_extensions(obj)) {
+ riscv_init_max_cpu_extensions(obj);
+ }
+}
+
static void riscv_cpu_init(Object *obj)
{
#ifndef CONFIG_USER_ONLY
@@ -1764,11 +1789,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
};
#endif
-static bool riscv_cpu_is_dynamic(Object *cpu_obj)
-{
- return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
-}
-
static void cpu_set_mvendorid(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
@@ -2005,6 +2025,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.instance_size = sizeof(RISCVCPU),
.instance_align = __alignof(RISCVCPU),
.instance_init = riscv_cpu_init,
+ .instance_post_init = riscv_cpu_post_init,
.abstract = true,
.class_size = sizeof(RISCVCPUClass),
.class_init = riscv_cpu_class_init,
--
2.41.0
- [PULL 17/54] target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig, (continued)
- [PULL 17/54] target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig, Alistair Francis, 2023/10/12
- [PULL 18/54] target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions(), Alistair Francis, 2023/10/12
- [PULL 19/54] target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update(), Alistair Francis, 2023/10/12
- [PULL 20/54] target/riscv/cpu.c: consider user option with RVG, Alistair Francis, 2023/10/12
- [PULL 21/54] target/riscv: Clear CSR values at reset and sync MPSTATE with host, Alistair Francis, 2023/10/12
- [PULL 22/54] disas/riscv: Fix the typo of inverted order of pmpaddr13 and pmpaddr14, Alistair Francis, 2023/10/12
- [PULL 23/54] target/riscv: introduce TCG AccelCPUClass, Alistair Francis, 2023/10/12
- [PULL 24/54] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn(), Alistair Francis, 2023/10/12
- [PULL 26/54] target/riscv: move riscv_tcg_ops to tcg-cpu.c, Alistair Francis, 2023/10/12
- [PULL 25/54] target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c, Alistair Francis, 2023/10/12
- [PULL 27/54] target/riscv/cpu.c: add .instance_post_init(),
Alistair Francis <=
- [PULL 28/54] target/riscv: move 'host' CPU declaration to kvm.c, Alistair Francis, 2023/10/12
- [PULL 29/54] target/riscv/cpu.c: mark extensions arrays as 'const', Alistair Francis, 2023/10/12
- [PULL 30/54] target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c, Alistair Francis, 2023/10/12
- [PULL 31/54] target/riscv: make riscv_add_satp_mode_properties() public, Alistair Francis, 2023/10/12
- [PULL 32/54] target/riscv: remove kvm-stub.c, Alistair Francis, 2023/10/12
- [PULL 33/54] target/riscv: introduce KVM AccelCPUClass, Alistair Francis, 2023/10/12
- [PULL 34/54] target/riscv: move KVM only files to kvm subdir, Alistair Francis, 2023/10/12
- [PULL 35/54] target/riscv/kvm: do not use riscv_cpu_add_misa_properties(), Alistair Francis, 2023/10/12
- [PULL 36/54] target/riscv/cpu.c: export set_misa(), Alistair Francis, 2023/10/12
- [PULL 37/54] target/riscv/tcg: introduce tcg_cpu_instance_init(), Alistair Francis, 2023/10/12