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[PULL 51/54] target/riscv/tcg: remove RVG warning
From: |
Alistair Francis |
Subject: |
[PULL 51/54] target/riscv/tcg: remove RVG warning |
Date: |
Thu, 12 Oct 2023 14:10:48 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Vendor CPUs that set RVG are displaying user warnings about other
extensions that RVG must enable, one warning per CPU. E.g.:
$ ./build/qemu-system-riscv64 -smp 8 -M virt -cpu veyron-v1 -nographic
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
This happens because we decided a while ago that, for simplicity, vendor
CPUs could set RVG instead of setting each G extension individually in
their cpu_init(). Our warning isn't taking that into account, and we're
bugging users with a warning that we're causing ourselves.
In a closer look we conclude that this warning is not warranted in any
other circumstance since we're just following the ISA [1], which states
in chapter 24:
"One goal of the RISC-V project is that it be used as a stable software
development target. For this purpose, we define a combination of a base
ISA (RV32I or RV64I) plus selected standard extensions (IMAFD, Zicsr,
Zifencei) as a 'general-purpose' ISA, and we use the abbreviation G for
the IMAFDZicsr Zifencei combination of instruction-set extensions."
With this in mind, enabling IMAFD_Zicsr_Zifencei if the user explicitly
enables 'G' is an expected behavior and the warning is unneeded. Any
user caught by surprise should refer to the ISA.
Remove the warning when handling RVG.
[1]
https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf
Reported-by: Paul A. Clarke <pclarke@ventanamicro.com>
Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20231003122539.775932-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/tcg/tcg-cpu.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 2e462e7d11..a042bb6cda 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -293,7 +293,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error
**errp)
return;
}
- warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true);
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true);
--
2.41.0
- [PULL 41/54] target/riscv/cpu: move priv spec functions to tcg-cpu.c, (continued)
- [PULL 41/54] target/riscv/cpu: move priv spec functions to tcg-cpu.c, Alistair Francis, 2023/10/12
- [PULL 42/54] target/riscv: add riscv_cpu_get_name(), Alistair Francis, 2023/10/12
- [PULL 43/54] target/riscv/tcg-cpu.c: add extension properties for all cpus, Alistair Francis, 2023/10/12
- [PULL 46/54] hw/misc/sifive_test.c: replace exit calls with proper shutdown, Alistair Francis, 2023/10/12
- [PULL 45/54] softmmu: pass the main loop status to gdb "Wxx" packet, Alistair Francis, 2023/10/12
- [PULL 47/54] hw/char: riscv_htif: replace exit calls with proper shutdown, Alistair Francis, 2023/10/12
- [PULL 44/54] softmmu: add means to pass an exit code when requesting a shutdown, Alistair Francis, 2023/10/12
- [PULL 48/54] gdbstub: replace exit calls with proper shutdown for softmmu, Alistair Francis, 2023/10/12
- [PULL 49/54] target/riscv/kvm: improve 'init_multiext_cfg' error msg, Alistair Francis, 2023/10/12
- [PULL 50/54] target/riscv/kvm: support KVM_GET_REG_LIST, Alistair Francis, 2023/10/12
- [PULL 51/54] target/riscv/tcg: remove RVG warning,
Alistair Francis <=
- [PULL 52/54] target/riscv: Use env_archcpu for better performance, Alistair Francis, 2023/10/12
- [PULL 53/54] target/riscv: deprecate capital 'Z' CPU properties, Alistair Francis, 2023/10/12
- [PULL 54/54] target/riscv: Fix vfwmaccbf16.vf, Alistair Francis, 2023/10/12
- Re: [PULL 00/54] riscv-to-apply queue, Stefan Hajnoczi, 2023/10/13