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[PATCH 09/85] target/sparc: Move FBPfcc and FBfcc to decodetree
From: |
Richard Henderson |
Subject: |
[PATCH 09/85] target/sparc: Move FBPfcc and FBfcc to decodetree |
Date: |
Fri, 13 Oct 2023 14:27:30 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/insns.decode | 4 ++
target/sparc/translate.c | 105 +++++++++++++++-----------------------
2 files changed, 46 insertions(+), 63 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 838f4cdb1d..9ab3f2eb82 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -6,8 +6,12 @@
&bcc i a cond cc
BPcc 00 a:1 cond:4 001 cc:1 0 - i:s19 &bcc
Bicc 00 a:1 cond:4 010 i:s22 &bcc cc=0
+FBPfcc 00 a:1 cond:4 101 cc:2 - i:s19 &bcc
+FBfcc 00 a:1 cond:4 110 i:s22 &bcc cc=0
%d16 20:s2 0:14
BPr 00 a:1 0 cond:3 011 .. - rs1:5 .............. i=%d16
+NCP 00 - ---- 111 ---------------------- # CBcc
+
CALL 01 i:s30
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index f72e6eb756..8c15ca08c4 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -1312,44 +1312,6 @@ static void gen_compare_reg(DisasCompare *cmp, int cond,
TCGv r_src)
cmp->c2 = tcg_constant_tl(0);
}
-static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc)
-{
- unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
- target_ulong target = dc->pc + offset;
-
- if (unlikely(AM_CHECK(dc))) {
- target &= 0xffffffffULL;
- }
- if (cond == 0x0) {
- /* unconditional not taken */
- if (a) {
- dc->pc = dc->npc + 4;
- dc->npc = dc->pc + 4;
- } else {
- dc->pc = dc->npc;
- dc->npc = dc->pc + 4;
- }
- } else if (cond == 0x8) {
- /* unconditional taken */
- if (a) {
- dc->pc = target;
- dc->npc = dc->pc + 4;
- } else {
- dc->pc = dc->npc;
- dc->npc = target;
- tcg_gen_mov_tl(cpu_pc, cpu_npc);
- }
- } else {
- flush_cond(dc);
- gen_fcond(cpu_cond, cc, cond);
- if (a) {
- gen_branch_a(dc, target);
- } else {
- gen_branch_n(dc, target);
- }
- }
-}
-
#ifdef TARGET_SPARC64
static void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
{
@@ -2993,6 +2955,31 @@ static bool do_bpcc(DisasContext *dc, arg_bcc *a)
TRANS(BPcc, 64, do_bpcc, a)
TRANS(Bicc, ALL, do_bpcc, a)
+static bool do_fbpfcc(DisasContext *dc, arg_bcc *a)
+{
+ target_long target = dc->pc + a->i * 4;
+
+ if (gen_trap_ifnofpu(dc)) {
+ return true;
+ }
+ if (unlikely(AM_CHECK(dc))) {
+ target &= 0xffffffffULL;
+ }
+ switch (a->cond) {
+ case 0x0:
+ return advance_jump_uncond_never(dc, a->a);
+ case 0x8:
+ return advance_jump_uncond_always(dc, a->a, target);
+ default:
+ flush_cond(dc);
+ gen_fcond(cpu_cond, a->cc, a->cond);
+ return advance_jump_cond(dc, a->a, target);
+ }
+}
+
+TRANS(FBPfcc, 64, do_fbpfcc, a)
+TRANS(FBfcc, ALL, do_fbpfcc, a)
+
static bool trans_BPr(DisasContext *dc, arg_BPr *a)
{
target_long target;
@@ -3032,6 +3019,20 @@ static bool trans_CALL(DisasContext *dc, arg_CALL *a)
return true;
}
+static bool trans_NCP(DisasContext *dc, arg_NCP *a)
+{
+ /*
+ * For sparc32, always generate the no-coprocessor exception.
+ * For sparc64, always generate illegal instruction.
+ */
+#ifdef TARGET_SPARC64
+ return false;
+#else
+ gen_exception(dc, TT_NCP_INSN);
+ return true;
+#endif
+}
+
#define CHECK_IU_FEATURE(dc, FEATURE) \
if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
goto illegal_insn;
@@ -3055,7 +3056,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned
int insn)
case 0: /* branches/sethi */
{
unsigned int xop = GET_FIELD(insn, 7, 9);
- int32_t target;
switch (xop) {
#ifdef TARGET_SPARC64
case 0x1: /* V9 BPcc */
@@ -3063,36 +3063,15 @@ static void disas_sparc_legacy(DisasContext *dc,
unsigned int insn)
case 0x3: /* V9 BPr */
g_assert_not_reached(); /* in decodetree */
case 0x5: /* V9 FBPcc */
- {
- int cc = GET_FIELD_SP(insn, 20, 21);
- if (gen_trap_ifnofpu(dc)) {
- goto jmp_insn;
- }
- target = GET_FIELD_SP(insn, 0, 18);
- target = sign_extend(target, 19);
- target <<= 2;
- do_fbranch(dc, target, insn, cc);
- goto jmp_insn;
- }
+ g_assert_not_reached(); /* in decodetree */
#else
case 0x7: /* CBN+x */
- {
- goto ncp_insn;
- }
+ g_assert_not_reached(); /* in decodetree */
#endif
case 0x2: /* BN+x */
g_assert_not_reached(); /* in decodetree */
case 0x6: /* FBN+x */
- {
- if (gen_trap_ifnofpu(dc)) {
- goto jmp_insn;
- }
- target = GET_FIELD(insn, 10, 31);
- target = sign_extend(target, 22);
- target <<= 2;
- do_fbranch(dc, target, insn, 0);
- goto jmp_insn;
- }
+ g_assert_not_reached(); /* in decodetree */
case 0x4: /* SETHI */
/* Special-case %g0 because that's the canonical nop. */
if (rd) {
--
2.34.1
- [PATCH 00/85] target/sparc: Convert to decodetree, Richard Henderson, 2023/10/13
- [PATCH 01/85] target/sparc: Set TCG_GUEST_DEFAULT_MO, Richard Henderson, 2023/10/13
- [PATCH 02/85] configs: Enable MTTCG for sparc, sparc64, Richard Henderson, 2023/10/13
- [PATCH 03/85] target/sparc: Remove always-set cpu features, Richard Henderson, 2023/10/13
- [PATCH 04/85] target/sparc: Add decodetree infrastructure, Richard Henderson, 2023/10/13
- [PATCH 05/85] target/sparc: Define AM_CHECK for sparc32, Richard Henderson, 2023/10/13
- [PATCH 06/85] target/sparc: Move CALL to decodetree, Richard Henderson, 2023/10/13
- [PATCH 08/85] target/sparc: Move BPr to decodetree, Richard Henderson, 2023/10/13
- [PATCH 09/85] target/sparc: Move FBPfcc and FBfcc to decodetree,
Richard Henderson <=
- [PATCH 10/85] target/sparc: Merge gen_cond with only caller, Richard Henderson, 2023/10/13
- [PATCH 07/85] target/sparc: Move BPcc and Bicc to decodetree, Richard Henderson, 2023/10/13
- [PATCH 11/85] target/sparc: Merge gen_fcond with only caller, Richard Henderson, 2023/10/13
- [PATCH 12/85] target/sparc: Merge gen_branch_[an] with only caller, Richard Henderson, 2023/10/13
- [PATCH 13/85] target/sparc: Pass DisasCompare to advance_jump_cond, Richard Henderson, 2023/10/13
- [PATCH 14/85] target/sparc: Move SETHI to decodetree, Richard Henderson, 2023/10/13
- [PATCH 15/85] target/sparc: Move Tcc to decodetree, Richard Henderson, 2023/10/13
- [PATCH 16/85] target/sparc: Move RDASR, STBAR, MEMBAR to decodetree, Richard Henderson, 2023/10/13