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[PATCH 11/85] target/sparc: Merge gen_fcond with only caller
From: |
Richard Henderson |
Subject: |
[PATCH 11/85] target/sparc: Merge gen_fcond with only caller |
Date: |
Fri, 13 Oct 2023 14:27:32 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/translate.c | 22 ++++++++--------------
1 file changed, 8 insertions(+), 14 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 1ac3bdd03f..ecb485c305 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -1265,19 +1265,6 @@ static void gen_fcompare(DisasCompare *cmp, unsigned int
cc, unsigned int cond)
}
}
-static void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
-{
- DisasCompare cmp;
- gen_fcompare(&cmp, cc, cond);
-
- /* The interface is to return a boolean in r_dst. */
- if (cmp.is_bool) {
- tcg_gen_mov_tl(r_dst, cmp.c1);
- } else {
- tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
- }
-}
-
// Inverted logic
static const TCGCond gen_tcg_cond_reg[8] = {
TCG_COND_NEVER, /* reserved */
@@ -2951,6 +2938,7 @@ TRANS(Bicc, ALL, do_bpcc, a)
static bool do_fbpfcc(DisasContext *dc, arg_bcc *a)
{
target_long target = dc->pc + a->i * 4;
+ DisasCompare cmp;
if (gen_trap_ifnofpu(dc)) {
return true;
@@ -2965,7 +2953,13 @@ static bool do_fbpfcc(DisasContext *dc, arg_bcc *a)
return advance_jump_uncond_always(dc, a->a, target);
default:
flush_cond(dc);
- gen_fcond(cpu_cond, a->cc, a->cond);
+
+ gen_fcompare(&cmp, a->cc, a->cond);
+ if (cmp.is_bool) {
+ tcg_gen_mov_tl(cpu_cond, cmp.c1);
+ } else {
+ tcg_gen_setcond_tl(cmp.cond, cpu_cond, cmp.c1, cmp.c2);
+ }
return advance_jump_cond(dc, a->a, target);
}
}
--
2.34.1
- [PATCH 03/85] target/sparc: Remove always-set cpu features, (continued)
- [PATCH 03/85] target/sparc: Remove always-set cpu features, Richard Henderson, 2023/10/13
- [PATCH 04/85] target/sparc: Add decodetree infrastructure, Richard Henderson, 2023/10/13
- [PATCH 05/85] target/sparc: Define AM_CHECK for sparc32, Richard Henderson, 2023/10/13
- [PATCH 06/85] target/sparc: Move CALL to decodetree, Richard Henderson, 2023/10/13
- [PATCH 08/85] target/sparc: Move BPr to decodetree, Richard Henderson, 2023/10/13
- [PATCH 09/85] target/sparc: Move FBPfcc and FBfcc to decodetree, Richard Henderson, 2023/10/13
- [PATCH 10/85] target/sparc: Merge gen_cond with only caller, Richard Henderson, 2023/10/13
- [PATCH 07/85] target/sparc: Move BPcc and Bicc to decodetree, Richard Henderson, 2023/10/13
- [PATCH 11/85] target/sparc: Merge gen_fcond with only caller,
Richard Henderson <=
- [PATCH 12/85] target/sparc: Merge gen_branch_[an] with only caller, Richard Henderson, 2023/10/13
- [PATCH 13/85] target/sparc: Pass DisasCompare to advance_jump_cond, Richard Henderson, 2023/10/13
- [PATCH 14/85] target/sparc: Move SETHI to decodetree, Richard Henderson, 2023/10/13
- [PATCH 15/85] target/sparc: Move Tcc to decodetree, Richard Henderson, 2023/10/13
- [PATCH 16/85] target/sparc: Move RDASR, STBAR, MEMBAR to decodetree, Richard Henderson, 2023/10/13
- [PATCH 18/85] target/sparc: Move RDWIM, RDPR to decodetree, Richard Henderson, 2023/10/13
- [PATCH 17/85] target/sparc: Move RDPSR, RDHPR to decodetree, Richard Henderson, 2023/10/13
- [PATCH 19/85] target/sparc: Move RDTBR, FLUSHW to decodetree, Richard Henderson, 2023/10/13
- [PATCH 21/85] target/sparc: Move WRPSR, SAVED, RESTORED to decodetree, Richard Henderson, 2023/10/13