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[PATCH 26/85] target/sparc: Move MULX to decodetree
From: |
Richard Henderson |
Subject: |
[PATCH 26/85] target/sparc: Move MULX to decodetree |
Date: |
Fri, 13 Oct 2023 14:27:47 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/insns.decode | 1 +
target/sparc/translate.c | 6 +-----
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 87108da5da..d907a4a69f 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -174,3 +174,4 @@ XORN 10 ..... 000111 ..... . .............
@r_r_ri
XORNcc 10 ..... 010111 ..... . ............. @r_r_ri
ADDC 10 ..... 001000 ..... . ............. @r_r_ri
ADDCcc 10 ..... 011000 ..... . ............. @r_r_ri
+MULX 10 ..... 001001 ..... . ............. @r_r_ri
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 37917ad397..7a7d517fac 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -4149,6 +4149,7 @@ TRANS(SUB, ALL, do_arith, a, tcg_gen_sub_tl,
tcg_gen_subi_tl)
TRANS(ANDN, ALL, do_arith, a, tcg_gen_andc_tl, NULL)
TRANS(ORN, ALL, do_arith, a, tcg_gen_orc_tl, NULL)
TRANS(XORN, ALL, do_arith, a, tcg_gen_eqv_tl, NULL)
+TRANS(MULX, 64, do_arith, a, tcg_gen_mul_tl, tcg_gen_muli_tl)
TRANS(ADDcc, ALL, do_cc_arith, a, CC_OP_ADD, gen_op_add_cc, NULL)
TRANS(ANDcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_and_tl, tcg_gen_andi_tl)
@@ -4620,11 +4621,6 @@ static void disas_sparc_legacy(DisasContext *dc,
unsigned int insn)
cpu_src1 = get_src1(dc, insn);
cpu_src2 = get_src2(dc, insn);
switch (xop & ~0x10) {
-#ifdef TARGET_SPARC64
- case 0x9: /* V9 mulx */
- tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
- break;
-#endif
case 0xa: /* umul */
gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
if (xop & 0x10) {
--
2.34.1
- [PATCH 12/85] target/sparc: Merge gen_branch_[an] with only caller, (continued)
- [PATCH 12/85] target/sparc: Merge gen_branch_[an] with only caller, Richard Henderson, 2023/10/13
- [PATCH 13/85] target/sparc: Pass DisasCompare to advance_jump_cond, Richard Henderson, 2023/10/13
- [PATCH 14/85] target/sparc: Move SETHI to decodetree, Richard Henderson, 2023/10/13
- [PATCH 15/85] target/sparc: Move Tcc to decodetree, Richard Henderson, 2023/10/13
- [PATCH 16/85] target/sparc: Move RDASR, STBAR, MEMBAR to decodetree, Richard Henderson, 2023/10/13
- [PATCH 18/85] target/sparc: Move RDWIM, RDPR to decodetree, Richard Henderson, 2023/10/13
- [PATCH 17/85] target/sparc: Move RDPSR, RDHPR to decodetree, Richard Henderson, 2023/10/13
- [PATCH 19/85] target/sparc: Move RDTBR, FLUSHW to decodetree, Richard Henderson, 2023/10/13
- [PATCH 21/85] target/sparc: Move WRPSR, SAVED, RESTORED to decodetree, Richard Henderson, 2023/10/13
- [PATCH 22/85] target/sparc: Move WRWIM, WRPR to decodetree, Richard Henderson, 2023/10/13
- [PATCH 26/85] target/sparc: Move MULX to decodetree,
Richard Henderson <=
- [PATCH 23/85] target/sparc: Move WRTBR, WRHPR to decodetree, Richard Henderson, 2023/10/13
- [PATCH 31/85] target/sparc: Move TADD, TSUB, MULS to decodetree, Richard Henderson, 2023/10/13
- [PATCH 29/85] target/sparc: Move UDIVX, SDIVX to decodetree, Richard Henderson, 2023/10/13
- [PATCH 30/85] target/sparc: Move UDIV, SDIV to decodetree, Richard Henderson, 2023/10/13
- [PATCH 34/85] target/sparc: Move POPC to decodetree, Richard Henderson, 2023/10/13
- [PATCH 35/85] target/sparc: Convert remaining v8 coproc insns to decodetree, Richard Henderson, 2023/10/13
- [PATCH 20/85] target/sparc: Move WRASR to decodetree, Richard Henderson, 2023/10/13
- [PATCH 25/85] target/sparc: Move ADDC to decodetree, Richard Henderson, 2023/10/13
- [PATCH 24/85] target/sparc: Move basic arithmetic to decodetree, Richard Henderson, 2023/10/13
- [PATCH 27/85] target/sparc: Move UMUL, SMUL to decodetree, Richard Henderson, 2023/10/13