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[PATCH 24/85] target/sparc: Move basic arithmetic to decodetree
From: |
Richard Henderson |
Subject: |
[PATCH 24/85] target/sparc: Move basic arithmetic to decodetree |
Date: |
Fri, 13 Oct 2023 14:27:45 -0700 |
Move ADD, AND, OR, XOR, SUB, ANDN, ORN, XORN.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/insns.decode | 18 ++++
target/sparc/translate.c | 183 +++++++++++++++++---------------------
2 files changed, 98 insertions(+), 103 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 0425764973..a95f682fa7 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -28,6 +28,7 @@ CALL 01 i:s30
&r_r_ri rd rs1 rs2_or_imm imm:bool
@n_r_ri .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri rd=0
+@r_r_ri .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri
Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5
Tcc_i 10 0 cond:4 111010 rs1:5 1 cc:1 0000 i:8
@@ -154,3 +155,20 @@ WRPR_strand_status 10 11010 110010 ..... . .............
@n_r_ri
WRHPR_hintp 10 00011 110011 ..... . ............. @n_r_ri
WRHPR_htba 10 00101 110011 ..... . ............. @n_r_ri
WRHPR_hstick_cmpr 10 11111 110011 ..... . ............. @n_r_ri
+
+ADD 10 ..... 000000 ..... . ............. @r_r_ri
+ADDcc 10 ..... 010000 ..... . ............. @r_r_ri
+AND 10 ..... 000001 ..... . ............. @r_r_ri
+ANDcc 10 ..... 010001 ..... . ............. @r_r_ri
+OR 10 ..... 000010 ..... . ............. @r_r_ri
+ORcc 10 ..... 010010 ..... . ............. @r_r_ri
+XOR 10 ..... 000011 ..... . ............. @r_r_ri
+XORcc 10 ..... 010011 ..... . ............. @r_r_ri
+SUB 10 ..... 000100 ..... . ............. @r_r_ri
+SUBcc 10 ..... 010100 ..... . ............. @r_r_ri
+ANDN 10 ..... 000101 ..... . ............. @r_r_ri
+ANDNcc 10 ..... 010101 ..... . ............. @r_r_ri
+ORN 10 ..... 000110 ..... . ............. @r_r_ri
+ORNcc 10 ..... 010110 ..... . ............. @r_r_ri
+XORN 10 ..... 000111 ..... . ............. @r_r_ri
+XORNcc 10 ..... 010111 ..... . ............. @r_r_ri
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index efb3c7c570..a21c5ec329 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -4079,6 +4079,86 @@ static bool trans_NOP_v7(DisasContext *dc, arg_NOP_v7 *a)
return false;
}
+static bool do_cc_arith(DisasContext *dc, arg_r_r_ri *a, int cc_op,
+ void (*func)(TCGv, TCGv, TCGv),
+ void (*funci)(TCGv, TCGv, target_long))
+{
+ TCGv dst, src1;
+
+ /* For simplicity, we under-decoded the rs2 form. */
+ if (!a->imm && a->rs2_or_imm & ~0x1f) {
+ return false;
+ }
+
+ if (cc_op < 0) {
+ dst = gen_dest_gpr(dc, a->rd);
+ } else {
+ dst = cpu_cc_dst;
+ tcg_gen_movi_i32(cpu_cc_op, cc_op);
+ dc->cc_op = cc_op;
+ }
+ src1 = gen_load_gpr(dc, a->rs1);
+
+ if (a->imm || a->rs2_or_imm == 0) {
+ if (funci) {
+ funci(dst, src1, a->rs2_or_imm);
+ } else {
+ func(dst, src1, tcg_constant_tl(a->rs2_or_imm));
+ }
+ } else {
+ func(dst, src1, cpu_regs[a->rs2_or_imm]);
+ }
+ gen_store_gpr(dc, a->rd, dst);
+ return advance_pc(dc);
+}
+
+static bool do_arith(DisasContext *dc, arg_r_r_ri *a,
+ void (*func)(TCGv, TCGv, TCGv),
+ void (*funci)(TCGv, TCGv, target_long))
+{
+ return do_cc_arith(dc, a, -1, func, funci);
+}
+
+static bool trans_OR(DisasContext *dc, arg_r_r_ri *a)
+{
+ /* For simplicity, we under-decoded the rs2 form. */
+ if (!a->imm && a->rs2_or_imm & ~0x1f) {
+ return false;
+ }
+
+ /* OR with %g0 is the canonical alias for MOV. */
+ if (a->rs1 == 0) {
+ TCGv src2;
+
+ if (a->imm || a->rs2_or_imm == 0) {
+ src2 = tcg_constant_tl(a->rs2_or_imm);
+ } else {
+ src2 = cpu_regs[a->rs2_or_imm];
+ }
+ gen_store_gpr(dc, a->rd, src2);
+ return advance_pc(dc);
+ }
+
+ return do_arith(dc, a, tcg_gen_or_tl, tcg_gen_ori_tl);
+}
+
+TRANS(ADD, ALL, do_arith, a, tcg_gen_add_tl, tcg_gen_addi_tl)
+TRANS(AND, ALL, do_arith, a, tcg_gen_and_tl, tcg_gen_andi_tl)
+TRANS(XOR, ALL, do_arith, a, tcg_gen_xor_tl, tcg_gen_xori_tl)
+TRANS(SUB, ALL, do_arith, a, tcg_gen_sub_tl, tcg_gen_subi_tl)
+TRANS(ANDN, ALL, do_arith, a, tcg_gen_andc_tl, NULL)
+TRANS(ORN, ALL, do_arith, a, tcg_gen_orc_tl, NULL)
+TRANS(XORN, ALL, do_arith, a, tcg_gen_eqv_tl, NULL)
+
+TRANS(ADDcc, ALL, do_cc_arith, a, CC_OP_ADD, gen_op_add_cc, NULL)
+TRANS(ANDcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_and_tl, tcg_gen_andi_tl)
+TRANS(ORcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_or_tl, tcg_gen_ori_tl)
+TRANS(XORcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_xor_tl, tcg_gen_xori_tl)
+TRANS(SUBcc, ALL, do_cc_arith, a, CC_OP_SUB, gen_op_sub_cc, NULL)
+TRANS(ANDNcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_andc_tl, NULL)
+TRANS(ORNcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_orc_tl, NULL)
+TRANS(XORNcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_eqv_tl, NULL)
+
#define CHECK_IU_FEATURE(dc, FEATURE) \
if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
goto illegal_insn;
@@ -4427,43 +4507,6 @@ static void disas_sparc_legacy(DisasContext *dc,
unsigned int insn)
default:
goto illegal_insn;
}
- } else if (xop == 0x2) {
- TCGv dst = gen_dest_gpr(dc, rd);
- rs1 = GET_FIELD(insn, 13, 17);
- if (rs1 == 0) {
- /* clr/mov shortcut : or %g0, x, y -> mov x, y */
- if (IS_IMM) { /* immediate */
- simm = GET_FIELDs(insn, 19, 31);
- tcg_gen_movi_tl(dst, simm);
- gen_store_gpr(dc, rd, dst);
- } else { /* register */
- rs2 = GET_FIELD(insn, 27, 31);
- if (rs2 == 0) {
- tcg_gen_movi_tl(dst, 0);
- gen_store_gpr(dc, rd, dst);
- } else {
- cpu_src2 = gen_load_gpr(dc, rs2);
- gen_store_gpr(dc, rd, cpu_src2);
- }
- }
- } else {
- cpu_src1 = get_src1(dc, insn);
- if (IS_IMM) { /* immediate */
- simm = GET_FIELDs(insn, 19, 31);
- tcg_gen_ori_tl(dst, cpu_src1, simm);
- gen_store_gpr(dc, rd, dst);
- } else { /* register */
- rs2 = GET_FIELD(insn, 27, 31);
- if (rs2 == 0) {
- /* mov shortcut: or x, %g0, y -> mov x, y */
- gen_store_gpr(dc, rd, cpu_src1);
- } else {
- cpu_src2 = gen_load_gpr(dc, rs2);
- tcg_gen_or_tl(dst, cpu_src1, cpu_src2);
- gen_store_gpr(dc, rd, dst);
- }
- }
- }
#ifdef TARGET_SPARC64
} else if (xop == 0x25) { /* sll, V9 sllx */
cpu_src1 = get_src1(dc, insn);
@@ -4540,72 +4583,6 @@ static void disas_sparc_legacy(DisasContext *dc,
unsigned int insn)
cpu_src1 = get_src1(dc, insn);
cpu_src2 = get_src2(dc, insn);
switch (xop & ~0x10) {
- case 0x0: /* add */
- if (xop & 0x10) {
- gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
- tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD);
- dc->cc_op = CC_OP_ADD;
- } else {
- tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
- }
- break;
- case 0x1: /* and */
- tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
- if (xop & 0x10) {
- tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
- tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
- dc->cc_op = CC_OP_LOGIC;
- }
- break;
- case 0x2: /* or */
- tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
- if (xop & 0x10) {
- tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
- tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
- dc->cc_op = CC_OP_LOGIC;
- }
- break;
- case 0x3: /* xor */
- tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
- if (xop & 0x10) {
- tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
- tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
- dc->cc_op = CC_OP_LOGIC;
- }
- break;
- case 0x4: /* sub */
- if (xop & 0x10) {
- gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
- tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
- dc->cc_op = CC_OP_SUB;
- } else {
- tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
- }
- break;
- case 0x5: /* andn */
- tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2);
- if (xop & 0x10) {
- tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
- tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
- dc->cc_op = CC_OP_LOGIC;
- }
- break;
- case 0x6: /* orn */
- tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2);
- if (xop & 0x10) {
- tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
- tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
- dc->cc_op = CC_OP_LOGIC;
- }
- break;
- case 0x7: /* xorn */
- tcg_gen_eqv_tl(cpu_dst, cpu_src1, cpu_src2);
- if (xop & 0x10) {
- tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
- tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
- dc->cc_op = CC_OP_LOGIC;
- }
- break;
case 0x8: /* addx, V9 addc */
gen_op_addx_int(dc, cpu_dst, cpu_src1, cpu_src2,
(xop & 0x10));
--
2.34.1
- [PATCH 22/85] target/sparc: Move WRWIM, WRPR to decodetree, (continued)
- [PATCH 22/85] target/sparc: Move WRWIM, WRPR to decodetree, Richard Henderson, 2023/10/13
- [PATCH 26/85] target/sparc: Move MULX to decodetree, Richard Henderson, 2023/10/13
- [PATCH 23/85] target/sparc: Move WRTBR, WRHPR to decodetree, Richard Henderson, 2023/10/13
- [PATCH 31/85] target/sparc: Move TADD, TSUB, MULS to decodetree, Richard Henderson, 2023/10/13
- [PATCH 29/85] target/sparc: Move UDIVX, SDIVX to decodetree, Richard Henderson, 2023/10/13
- [PATCH 30/85] target/sparc: Move UDIV, SDIV to decodetree, Richard Henderson, 2023/10/13
- [PATCH 34/85] target/sparc: Move POPC to decodetree, Richard Henderson, 2023/10/13
- [PATCH 35/85] target/sparc: Convert remaining v8 coproc insns to decodetree, Richard Henderson, 2023/10/13
- [PATCH 20/85] target/sparc: Move WRASR to decodetree, Richard Henderson, 2023/10/13
- [PATCH 25/85] target/sparc: Move ADDC to decodetree, Richard Henderson, 2023/10/13
- [PATCH 24/85] target/sparc: Move basic arithmetic to decodetree,
Richard Henderson <=
- [PATCH 27/85] target/sparc: Move UMUL, SMUL to decodetree, Richard Henderson, 2023/10/13
- [PATCH 28/85] target/sparc: Move SUBC to decodetree, Richard Henderson, 2023/10/13
- [PATCH 32/85] target/sparc: Move SLL, SRL, SRA to decodetree, Richard Henderson, 2023/10/13
- [PATCH 33/85] target/sparc: Move MOVcc, MOVR to decodetree, Richard Henderson, 2023/10/13
- [PATCH 37/85] target/sparc: Move FLUSH, SAVE, RESTORE to decodetree, Richard Henderson, 2023/10/13
- [PATCH 36/85] target/sparc: Move JMPL, RETT, RETURN to decodetree, Richard Henderson, 2023/10/13
- [PATCH 38/85] target/sparc: Move DONE, RETRY to decodetree, Richard Henderson, 2023/10/13
- [PATCH 39/85] target/sparc: Split out resolve_asi, Richard Henderson, 2023/10/13
- [PATCH 42/85] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for GET_ASI_DTWINX, Richard Henderson, 2023/10/13
- [PATCH 44/85] target/sparc: Move asi integer load/store to decodetree, Richard Henderson, 2023/10/13