[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v2 33/90] target/sparc: Move SUBC to decodetree
From: |
Richard Henderson |
Subject: |
[PATCH v2 33/90] target/sparc: Move SUBC to decodetree |
Date: |
Mon, 16 Oct 2023 23:11:47 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/insns.decode | 2 ++
target/sparc/translate.c | 28 ++++++++++++++++++++++++----
2 files changed, 26 insertions(+), 4 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index c114a13f1d..64f5885e67 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -176,5 +176,7 @@ UMUL 10 ..... 001010 ..... . .............
@r_r_ri
UMULcc 10 ..... 011010 ..... . ............. @r_r_ri
SMUL 10 ..... 001011 ..... . ............. @r_r_ri
SMULcc 10 ..... 011011 ..... . ............. @r_r_ri
+SUBC 10 ..... 001100 ..... . ............. @r_r_ri
+SUBCcc 10 ..... 011100 ..... . ............. @r_r_ri
Tcc 10 0 cond:4 111010 rs1:5 imm:1 cc:1 00000 rs2_or_imm:7
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index b6ec7d5cfd..30eb9bf94b 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -4236,6 +4236,30 @@ static bool trans_ADDCcc(DisasContext *dc, arg_r_r_ri *a)
return advance_pc(dc);
}
+static bool trans_SUBC(DisasContext *dc, arg_r_r_ri *a)
+{
+ TCGv src2 = gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm);
+
+ if (src2 == NULL) {
+ return false;
+ }
+ gen_op_subx_int(dc, gen_dest_gpr(dc, a->rd),
+ gen_load_gpr(dc, a->rs1), src2, false);
+ return advance_pc(dc);
+}
+
+static bool trans_SUBCcc(DisasContext *dc, arg_r_r_ri *a)
+{
+ TCGv src2 = gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm);
+
+ if (src2 == NULL) {
+ return false;
+ }
+ gen_op_subx_int(dc, gen_dest_gpr(dc, a->rd),
+ gen_load_gpr(dc, a->rs1), src2, true);
+ return advance_pc(dc);
+}
+
#define CHECK_IU_FEATURE(dc, FEATURE) \
if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
goto illegal_insn;
@@ -4660,10 +4684,6 @@ static void disas_sparc_legacy(DisasContext *dc,
unsigned int insn)
cpu_src1 = get_src1(dc, insn);
cpu_src2 = get_src2(dc, insn);
switch (xop & ~0x10) {
- case 0xc: /* subx, V9 subc */
- gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2,
- (xop & 0x10));
- break;
#ifdef TARGET_SPARC64
case 0xd: /* V9 udivx */
gen_helper_udivx(cpu_dst, tcg_env, cpu_src1, cpu_src2);
--
2.34.1
- [PATCH v2 25/90] target/sparc: Move WRASR to decodetree, (continued)
- [PATCH v2 25/90] target/sparc: Move WRASR to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 29/90] target/sparc: Move basic arithmetic to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 28/90] target/sparc: Move WRTBR, WRHPR to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 32/90] target/sparc: Move UMUL, SMUL to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 30/90] target/sparc: Move ADDC to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 31/90] target/sparc: Move MULX to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 34/90] target/sparc: Move UDIVX, SDIVX to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 35/90] target/sparc: Move UDIV, SDIV to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 38/90] target/sparc: Move MOVcc, MOVR to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 39/90] target/sparc: Move POPC to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 33/90] target/sparc: Move SUBC to decodetree,
Richard Henderson <=
- [PATCH v2 36/90] target/sparc: Move TADD, TSUB, MULS to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 37/90] target/sparc: Move SLL, SRL, SRA to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 40/90] target/sparc: Convert remaining v8 coproc insns to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 42/90] target/sparc: Move FLUSH, SAVE, RESTORE to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 41/90] target/sparc: Move JMPL, RETT, RETURN to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 46/90] target/sparc: Split out ldst functions with asi pre-computed, Richard Henderson, 2023/10/17
- [PATCH v2 44/90] target/sparc: Split out resolve_asi, Richard Henderson, 2023/10/17
- [PATCH v2 43/90] target/sparc: Move DONE, RETRY to decodetree, Richard Henderson, 2023/10/17
- [PATCH v2 47/90] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for GET_ASI_DTWINX, Richard Henderson, 2023/10/17
- [PATCH v2 52/90] target/sparc: Move CASA, CASXA to decodetree, Richard Henderson, 2023/10/17