Re: [RFC PATCH 2/2] target/loongarch: Use i128 for 128-bit load/store in XVLD

[Richard Henderson]

On 10/17/23 05:38, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/loongarch/translate.c                |  6 ++++++
>   target/loongarch/insn_trans/trans_vec.c.inc | 16 +++++++---------
>   2 files changed, 13 insertions(+), 9 deletions(-)
>
> diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
> index c6edfc800f..89e35770b7 100644
> --- a/target/loongarch/translate.c
> +++ b/target/loongarch/translate.c
> @@ -67,6 +67,12 @@ static inline void get_vreg128(TCGv_i128 dest, int regno, 
> int index)
>                       offsetof(CPULoongArchState, fpr[regno].vreg.Q(index)));
>   }
>   
> +static inline void set_vreg128(TCGv_i128 src, int regno, int index)
> +{
> +    tcg_gen_st_i128(src, tcg_env,
> +                    offsetof(CPULoongArchState, fpr[regno].vreg.Q(index)));
> +}
> +
>   static inline int plus_1(DisasContext *ctx, int x)
>   {
>       return x + 1;
> diff --git a/target/loongarch/insn_trans/trans_vec.c.inc 
> b/target/loongarch/insn_trans/trans_vec.c.inc
> index dd41f5e48e..c8b7bfa67f 100644
> --- a/target/loongarch/insn_trans/trans_vec.c.inc
> +++ b/target/loongarch/insn_trans/trans_vec.c.inc
> @@ -5458,18 +5458,16 @@ static bool gen_lasx_memory(DisasContext *ctx, arg_vr_i 
> *a,
>   
>   static void gen_xvld(DisasContext *ctx, int vreg, TCGv addr)
>   {
> -    int i;
> +    MemOp mop = MO_128 | MO_TE;
>       TCGv temp = tcg_temp_new();
> -    TCGv dest = tcg_temp_new();
> +    TCGv_i128 dest = tcg_temp_new_i128();
>   
> -    tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUQ);
> -    set_vreg64(dest, vreg, 0);
> +    tcg_gen_qemu_ld_i128(dest, addr, ctx->mem_idx, mop);
> +    set_vreg128(dest, vreg, 0);
>   
> -    for (i = 1; i < 4; i++) {
> -        tcg_gen_addi_tl(temp, addr, 8 * i);
> -        tcg_gen_qemu_ld_i64(dest, temp, ctx->mem_idx, MO_TEUQ);
> -        set_vreg64(dest, vreg, i);
> -    }
> +    tcg_gen_addi_tl(temp, addr, 16);
> +    tcg_gen_qemu_ld_i128(dest, temp, ctx->mem_idx, mop);
> +    set_vreg128(dest, vreg, 1);
>   }
>   
>   static void gen_xvst(DisasContext * ctx, int vreg, TCGv addr)

Missing the matching change to trans_vld.


r~