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[PATCH 10/61] target/hppa: Fix bb_sar for hppa64
From: |
Richard Henderson |
Subject: |
[PATCH 10/61] target/hppa: Fix bb_sar for hppa64 |
Date: |
Wed, 18 Oct 2023 14:50:44 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 8ebe7523a7..119422870c 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3073,14 +3073,21 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar
*a)
{
TCGv_reg tmp, tcg_r;
DisasCond cond;
+ bool d = false;
nullify_over(ctx);
tmp = tcg_temp_new();
tcg_r = load_gpr(ctx, a->r);
- tcg_gen_shl_reg(tmp, tcg_r, cpu_sar);
+ if (cond_need_ext(ctx, d)) {
+ /* Force shift into [32,63] */
+ tcg_gen_ori_reg(tmp, cpu_sar, 32);
+ tcg_gen_shl_reg(tmp, tcg_r, tmp);
+ } else {
+ tcg_gen_shl_reg(tmp, tcg_r, cpu_sar);
+ }
- cond = cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp);
+ cond = cond_make_0_tmp(a->c ? TCG_COND_GE : TCG_COND_LT, tmp);
return do_cbranch(ctx, a->disp, a->n, &cond);
}
@@ -3088,12 +3095,15 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm
*a)
{
TCGv_reg tmp, tcg_r;
DisasCond cond;
+ bool d = false;
+ int p;
nullify_over(ctx);
tmp = tcg_temp_new();
tcg_r = load_gpr(ctx, a->r);
- tcg_gen_shli_reg(tmp, tcg_r, a->p);
+ p = a->p | (cond_need_ext(ctx, d) ? 32 : 0);
+ tcg_gen_shli_reg(tmp, tcg_r, p);
cond = cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp);
return do_cbranch(ctx, a->disp, a->n, &cond);
--
2.34.1
- [PATCH 20/61] target/hppa: Fix hppa64 addressing, (continued)
- [PATCH 20/61] target/hppa: Fix hppa64 addressing, Richard Henderson, 2023/10/18
- [PATCH 25/61] target/hppa: Pass d to do_sed_cond, Richard Henderson, 2023/10/18
- [PATCH 29/61] target/hppa: Remove TARGET_HPPA64, Richard Henderson, 2023/10/18
- [PATCH 34/61] target/hppa: Decode d for sub instructions, Richard Henderson, 2023/10/18
- [PATCH 37/61] target/hppa: Decode CMPIB double-word, Richard Henderson, 2023/10/18
- [PATCH 15/61] target/hppa: Implement hppa_cpu_class_by_name, Richard Henderson, 2023/10/18
- [PATCH 16/61] target/hppa: Update cpu_hppa_get/put_psw for hppa64, Richard Henderson, 2023/10/18
- [PATCH 22/61] target/hppa: Pass d to do_cond, Richard Henderson, 2023/10/18
- [PATCH 23/61] target/hppa: Pass d to do_sub_cond, Richard Henderson, 2023/10/18
- [PATCH 24/61] target/hppa: Pass d to do_log_cond, Richard Henderson, 2023/10/18
- [PATCH 10/61] target/hppa: Fix bb_sar for hppa64,
Richard Henderson <=
- [PATCH 21/61] target/hppa: sar register allows only 5 bits on 32-bit CPU, Richard Henderson, 2023/10/18
- [PATCH 26/61] target/hppa: Pass d to do_unit_cond, Richard Henderson, 2023/10/18
- [PATCH 33/61] target/hppa: Decode d for add instructions, Richard Henderson, 2023/10/18
- [PATCH 32/61] target/hppa: Decode d for cmpclr instructions, Richard Henderson, 2023/10/18
- [PATCH 35/61] target/hppa: Decode d for bb instructions, Richard Henderson, 2023/10/18
- [PATCH 39/61] target/hppa: Implement LDD, LDCD, LDDA, STD, STDA, Richard Henderson, 2023/10/18
- [PATCH 40/61] target/hppa: Implement DEPD, DEPDI, Richard Henderson, 2023/10/18
- [PATCH 41/61] target/hppa: Implement EXTRD, Richard Henderson, 2023/10/18
- [PATCH 44/61] target/hppa: Implement STDBY, Richard Henderson, 2023/10/18
- [PATCH 43/61] target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOM, Richard Henderson, 2023/10/18