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[PATCH 21/61] target/hppa: sar register allows only 5 bits on 32-bit CPU
From: |
Richard Henderson |
Subject: |
[PATCH 21/61] target/hppa: sar register allows only 5 bits on 32-bit CPU |
Date: |
Wed, 18 Oct 2023 14:50:55 -0700 |
From: Helge Deller <deller@gmx.de>
The sar shift amount register is limited to 5 bits when running
a 32-bit CPU. Strip off the remaining bits.
The interesting part is, that this register allows to detect at runtime
if a physical CPU is capable to execute PA2.0 (64-bit) instructions.
Signed-off-by: Helge Deller <deller@gmx.de>
---
target/hppa/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index ace6fb0ab2..e2b692a6c5 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -2155,7 +2155,7 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a)
if (ctl == CR_SAR) {
reg = load_gpr(ctx, a->r);
tmp = tcg_temp_new();
- tcg_gen_andi_reg(tmp, reg, TARGET_REGISTER_BITS - 1);
+ tcg_gen_andi_reg(tmp, reg, ctx->is_pa20 ? 63 : 31);
save_or_nullify(ctx, cpu_sar, tmp);
cond_free(&ctx->null_cond);
@@ -2216,7 +2216,7 @@ static bool trans_mtsarcm(DisasContext *ctx, arg_mtsarcm
*a)
TCGv_reg tmp = tcg_temp_new();
tcg_gen_not_reg(tmp, load_gpr(ctx, a->r));
- tcg_gen_andi_reg(tmp, tmp, TARGET_REGISTER_BITS - 1);
+ tcg_gen_andi_reg(tmp, tmp, ctx->is_pa20 ? 63 : 31);
save_or_nullify(ctx, cpu_sar, tmp);
cond_free(&ctx->null_cond);
--
2.34.1
- [PATCH 25/61] target/hppa: Pass d to do_sed_cond, (continued)
- [PATCH 25/61] target/hppa: Pass d to do_sed_cond, Richard Henderson, 2023/10/18
- [PATCH 29/61] target/hppa: Remove TARGET_HPPA64, Richard Henderson, 2023/10/18
- [PATCH 34/61] target/hppa: Decode d for sub instructions, Richard Henderson, 2023/10/18
- [PATCH 37/61] target/hppa: Decode CMPIB double-word, Richard Henderson, 2023/10/18
- [PATCH 15/61] target/hppa: Implement hppa_cpu_class_by_name, Richard Henderson, 2023/10/18
- [PATCH 16/61] target/hppa: Update cpu_hppa_get/put_psw for hppa64, Richard Henderson, 2023/10/18
- [PATCH 22/61] target/hppa: Pass d to do_cond, Richard Henderson, 2023/10/18
- [PATCH 23/61] target/hppa: Pass d to do_sub_cond, Richard Henderson, 2023/10/18
- [PATCH 24/61] target/hppa: Pass d to do_log_cond, Richard Henderson, 2023/10/18
- [PATCH 10/61] target/hppa: Fix bb_sar for hppa64, Richard Henderson, 2023/10/18
- [PATCH 21/61] target/hppa: sar register allows only 5 bits on 32-bit CPU,
Richard Henderson <=
- [PATCH 26/61] target/hppa: Pass d to do_unit_cond, Richard Henderson, 2023/10/18
- [PATCH 33/61] target/hppa: Decode d for add instructions, Richard Henderson, 2023/10/18
- [PATCH 32/61] target/hppa: Decode d for cmpclr instructions, Richard Henderson, 2023/10/18
- [PATCH 35/61] target/hppa: Decode d for bb instructions, Richard Henderson, 2023/10/18
- [PATCH 39/61] target/hppa: Implement LDD, LDCD, LDDA, STD, STDA, Richard Henderson, 2023/10/18
- [PATCH 40/61] target/hppa: Implement DEPD, DEPDI, Richard Henderson, 2023/10/18
- [PATCH 41/61] target/hppa: Implement EXTRD, Richard Henderson, 2023/10/18
- [PATCH 44/61] target/hppa: Implement STDBY, Richard Henderson, 2023/10/18
- [PATCH 43/61] target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOM, Richard Henderson, 2023/10/18
- [PATCH 45/61] target/hppa: Implement IDTLBT, IITLBT, Richard Henderson, 2023/10/18