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[PATCH 26/61] target/hppa: Pass d to do_unit_cond
From: |
Richard Henderson |
Subject: |
[PATCH 26/61] target/hppa: Pass d to do_unit_cond |
Date: |
Wed, 18 Oct 2023 14:51:00 -0700 |
Hoist the resolution of d up one level above do_unit_cond.
All computations are logical, and are simplified by using a mask of the
correct width, after which the result may be compared with zero.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 20 +++++++++++---------
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 1a51ac4869..8bea28f0fd 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -1056,11 +1056,12 @@ static DisasCond do_sed_cond(DisasContext *ctx,
unsigned orig, bool d,
/* Similar, but for unit conditions. */
-static DisasCond do_unit_cond(unsigned cf, TCGv_reg res,
+static DisasCond do_unit_cond(unsigned cf, bool d, TCGv_reg res,
TCGv_reg in1, TCGv_reg in2)
{
DisasCond cond;
TCGv_reg tmp, cb = NULL;
+ target_ureg d_repl = d ? 0x0000000100000001ull : 1;
if (cf & 8) {
/* Since we want to test lots of carry-out bits all at once, do not
@@ -1087,32 +1088,32 @@ static DisasCond do_unit_cond(unsigned cf, TCGv_reg res,
* https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord
*/
tmp = tcg_temp_new();
- tcg_gen_subi_reg(tmp, res, 0x01010101u);
+ tcg_gen_subi_reg(tmp, res, d_repl * 0x01010101u);
tcg_gen_andc_reg(tmp, tmp, res);
- tcg_gen_andi_reg(tmp, tmp, 0x80808080u);
+ tcg_gen_andi_reg(tmp, tmp, d_repl * 0x80808080u);
cond = cond_make_0(TCG_COND_NE, tmp);
break;
case 3: /* SHZ / NHZ */
tmp = tcg_temp_new();
- tcg_gen_subi_reg(tmp, res, 0x00010001u);
+ tcg_gen_subi_reg(tmp, res, d_repl * 0x00010001u);
tcg_gen_andc_reg(tmp, tmp, res);
- tcg_gen_andi_reg(tmp, tmp, 0x80008000u);
+ tcg_gen_andi_reg(tmp, tmp, d_repl * 0x80008000u);
cond = cond_make_0(TCG_COND_NE, tmp);
break;
case 4: /* SDC / NDC */
- tcg_gen_andi_reg(cb, cb, 0x88888888u);
+ tcg_gen_andi_reg(cb, cb, d_repl * 0x88888888u);
cond = cond_make_0(TCG_COND_NE, cb);
break;
case 6: /* SBC / NBC */
- tcg_gen_andi_reg(cb, cb, 0x80808080u);
+ tcg_gen_andi_reg(cb, cb, d_repl * 0x80808080u);
cond = cond_make_0(TCG_COND_NE, cb);
break;
case 7: /* SHC / NHC */
- tcg_gen_andi_reg(cb, cb, 0x80008000u);
+ tcg_gen_andi_reg(cb, cb, d_repl * 0x80008000u);
cond = cond_make_0(TCG_COND_NE, cb);
break;
@@ -1428,6 +1429,7 @@ static void do_unit(DisasContext *ctx, unsigned rt,
TCGv_reg in1,
{
TCGv_reg dest;
DisasCond cond;
+ bool d = false;
if (cf == 0) {
dest = dest_gpr(ctx, rt);
@@ -1438,7 +1440,7 @@ static void do_unit(DisasContext *ctx, unsigned rt,
TCGv_reg in1,
dest = tcg_temp_new();
fn(dest, in1, in2);
- cond = do_unit_cond(cf, dest, in1, in2);
+ cond = do_unit_cond(cf, d, dest, in1, in2);
if (is_tc) {
TCGv_reg tmp = tcg_temp_new();
--
2.34.1
- [PATCH 29/61] target/hppa: Remove TARGET_HPPA64, (continued)
- [PATCH 29/61] target/hppa: Remove TARGET_HPPA64, Richard Henderson, 2023/10/18
- [PATCH 34/61] target/hppa: Decode d for sub instructions, Richard Henderson, 2023/10/18
- [PATCH 37/61] target/hppa: Decode CMPIB double-word, Richard Henderson, 2023/10/18
- [PATCH 15/61] target/hppa: Implement hppa_cpu_class_by_name, Richard Henderson, 2023/10/18
- [PATCH 16/61] target/hppa: Update cpu_hppa_get/put_psw for hppa64, Richard Henderson, 2023/10/18
- [PATCH 22/61] target/hppa: Pass d to do_cond, Richard Henderson, 2023/10/18
- [PATCH 23/61] target/hppa: Pass d to do_sub_cond, Richard Henderson, 2023/10/18
- [PATCH 24/61] target/hppa: Pass d to do_log_cond, Richard Henderson, 2023/10/18
- [PATCH 10/61] target/hppa: Fix bb_sar for hppa64, Richard Henderson, 2023/10/18
- [PATCH 21/61] target/hppa: sar register allows only 5 bits on 32-bit CPU, Richard Henderson, 2023/10/18
- [PATCH 26/61] target/hppa: Pass d to do_unit_cond,
Richard Henderson <=
- [PATCH 33/61] target/hppa: Decode d for add instructions, Richard Henderson, 2023/10/18
- [PATCH 32/61] target/hppa: Decode d for cmpclr instructions, Richard Henderson, 2023/10/18
- [PATCH 35/61] target/hppa: Decode d for bb instructions, Richard Henderson, 2023/10/18
- [PATCH 39/61] target/hppa: Implement LDD, LDCD, LDDA, STD, STDA, Richard Henderson, 2023/10/18
- [PATCH 40/61] target/hppa: Implement DEPD, DEPDI, Richard Henderson, 2023/10/18
- [PATCH 41/61] target/hppa: Implement EXTRD, Richard Henderson, 2023/10/18
- [PATCH 44/61] target/hppa: Implement STDBY, Richard Henderson, 2023/10/18
- [PATCH 43/61] target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOM, Richard Henderson, 2023/10/18
- [PATCH 45/61] target/hppa: Implement IDTLBT, IITLBT, Richard Henderson, 2023/10/18
- [PATCH 42/61] target/hppa: Implement SHRPD, Richard Henderson, 2023/10/18