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[PULL 19/24] target/arm: Implement FEAT_HPMN0
From: |
Peter Maydell |
Subject: |
[PULL 19/24] target/arm: Implement FEAT_HPMN0 |
Date: |
Thu, 19 Oct 2023 14:35:32 +0100 |
FEAT_HPMN0 is a small feature which defines that it is valid for
MDCR_EL2.HPMN to be set to 0, meaning "no PMU event counters provided
to an EL1 guest" (previously this setting was reserved). QEMU's
implementation almost gets HPMN == 0 right, but we need to fix
one check in pmevcntr_is_64_bit(). That is enough for us to
advertise the feature in the 'max' CPU.
(We don't need to make the behaviour conditional on feature
presence, because the FEAT_HPMN0 behaviour is within the range
of permitted UNPREDICTABLE behaviour for a non-FEAT_HPMN0
implementation.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230921185445.3339214-1-peter.maydell@linaro.org
---
docs/system/arm/emulation.rst | 1 +
target/arm/helper.c | 2 +-
target/arm/tcg/cpu32.c | 4 ++++
target/arm/tcg/cpu64.c | 1 +
4 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index 965cbf84c51..47fd648035f 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -46,6 +46,7 @@ the following architecture extensions:
- FEAT_HCX (Support for the HCRX_EL2 register)
- FEAT_HPDS (Hierarchical permission disables)
- FEAT_HPDS2 (Translation table page-based hardware attributes)
+- FEAT_HPMN0 (Setting of MDCR_EL2.HPMN to zero)
- FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
- FEAT_IDST (ID space trap handling)
- FEAT_IESB (Implicit error synchronization event)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 01cd1474565..b29edb26af8 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1283,7 +1283,7 @@ static bool pmevcntr_is_64_bit(CPUARMState *env, int
counter)
bool hlp = env->cp15.mdcr_el2 & MDCR_HLP;
int hpmn = env->cp15.mdcr_el2 & MDCR_HPMN;
- if (hpmn != 0 && counter >= hpmn) {
+ if (counter >= hpmn) {
return hlp;
}
}
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index 1f918ff5375..0d5d8e307dd 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -89,6 +89,10 @@ void aa32_max_features(ARMCPU *cpu)
t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */
t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */
cpu->isar.id_dfr0 = t;
+
+ t = cpu->isar.id_dfr1;
+ t = FIELD_DP32(t, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */
+ cpu->isar.id_dfr1 = t;
}
/* CPU models. These are not needed for the AArch64 linux-user build. */
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 68928e51272..d978aa5f7ad 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -1109,6 +1109,7 @@ void aarch64_max_tcg_initfn(Object *obj)
t = cpu->isar.id_aa64dfr0;
t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */
t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */
+ t = FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* FEAT_HPMN0 */
cpu->isar.id_aa64dfr0 = t;
t = cpu->isar.id_aa64smfr0;
--
2.34.1
- [PULL 07/24] elf2dmp: limit print length for sign_rsds, (continued)
- [PULL 07/24] elf2dmp: limit print length for sign_rsds, Peter Maydell, 2023/10/19
- [PULL 09/24] target/arm: Fix CNTPCT_EL0 trapping from EL0 when HCR_EL2.E2H is 0, Peter Maydell, 2023/10/19
- [PULL 10/24] {include/}hw/arm: refactor virt PPI logic, Peter Maydell, 2023/10/19
- [PULL 13/24] arm/kvm: convert to kvm_set_one_reg, Peter Maydell, 2023/10/19
- [PULL 21/24] target/arm/common-semi-target.h: Remove unnecessary boot.h include, Peter Maydell, 2023/10/19
- [PULL 23/24] hw/timer/npcm7xx_timer: Prevent timer from counting down past zero, Peter Maydell, 2023/10/19
- [PULL 16/24] hw/arm/smmuv3: Update ID register bit field definitions, Peter Maydell, 2023/10/19
- [PULL 17/24] hw/arm/smmuv3: Sort ID register setting into field order, Peter Maydell, 2023/10/19
- [PULL 24/24] contrib/elf2dmp: Use g_malloc(), g_new() and g_free(), Peter Maydell, 2023/10/19
- [PULL 18/24] hw/arm/smmuv3: Advertise SMMUv3.1-XNX feature, Peter Maydell, 2023/10/19
- [PULL 19/24] target/arm: Implement FEAT_HPMN0,
Peter Maydell <=
- [PULL 03/24] xlnx-bbram: hw/nvram: Remove deprecated device reset, Peter Maydell, 2023/10/19
- [PULL 04/24] xlnx-zynqmp-efuse: hw/nvram: Remove deprecated device reset, Peter Maydell, 2023/10/19
- [PULL 05/24] xlnx-versal-efuse: hw/nvram: Remove deprecated device reset, Peter Maydell, 2023/10/19
- [PULL 06/24] xlnx-bbram: hw/nvram: Use dot in device type name, Peter Maydell, 2023/10/19
- [PULL 08/24] elf2dmp: check array bounds in pdb_get_file_size, Peter Maydell, 2023/10/19
- [PULL 15/24] target/arm: Permit T32 LDM with single register, Peter Maydell, 2023/10/19
- [PULL 22/24] target/arm/arm-powerctl: Correctly init CPUs when powered on to lower EL, Peter Maydell, 2023/10/19
- [PULL 20/24] target/arm/kvm64.c: Remove unused include, Peter Maydell, 2023/10/19
- Re: [PULL 00/24] target-arm queue, Stefan Hajnoczi, 2023/10/20