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[PATCH v3 73/90] target/sparc: Move gen_fop_FFF insns to decodetree
From: |
Richard Henderson |
Subject: |
[PATCH v3 73/90] target/sparc: Move gen_fop_FFF insns to decodetree |
Date: |
Fri, 20 Oct 2023 22:31:41 -0700 |
Move FADDs, FSUBs, FMULs, FDIVs.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/insns.decode | 4 +++
target/sparc/translate.c | 54 +++++++++++++++++++--------------------
2 files changed, 31 insertions(+), 27 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 6994312909..06cab099d8 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -248,6 +248,10 @@ FABSd 10 ..... 110100 00000 0 0000 1010 .....
@r_r2
FSQRTs 10 ..... 110100 00000 0 0010 1001 ..... @r_r2
FSQRTd 10 ..... 110100 00000 0 0010 1010 ..... @r_r2
FSQRTq 10 ..... 110100 00000 0 0010 1011 ..... @r_r2
+FADDs 10 ..... 110100 ..... 0 0100 0001 ..... @r_r_r
+FSUBs 10 ..... 110100 ..... 0 0100 0101 ..... @r_r_r
+FMULs 10 ..... 110100 ..... 0 0100 1001 ..... @r_r_r
+FDIVs 10 ..... 110100 ..... 0 0100 1101 ..... @r_r_r
FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2
FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2
FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 2d594ddc9f..8a0de0803b 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -1653,21 +1653,6 @@ static int gen_trap_ifnofpu(DisasContext *dc)
return 0;
}
-static void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
- void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32))
-{
- TCGv_i32 dst, src1, src2;
-
- src1 = gen_load_fpr_F(dc, rs1);
- src2 = gen_load_fpr_F(dc, rs2);
- dst = gen_dest_fpr_F(dc);
-
- gen(dst, tcg_env, src1, src2);
- gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
-
- gen_store_fpr_F(dc, rd, dst);
-}
-
static void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64))
{
@@ -5001,6 +4986,29 @@ TRANS(FXNORs, VIS1, do_fff, a, tcg_gen_eqv_i32)
TRANS(FORNOTs, VIS1, do_fff, a, tcg_gen_orc_i32)
TRANS(FORs, VIS1, do_fff, a, tcg_gen_or_i32)
+static bool do_env_fff(DisasContext *dc, arg_r_r_r *a,
+ void (*func)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32))
+{
+ TCGv_i32 src1, src2;
+
+ if (gen_trap_ifnofpu(dc)) {
+ return true;
+ }
+
+ gen_op_clear_ieee_excp_and_FTT();
+ src1 = gen_load_fpr_F(dc, a->rs1);
+ src2 = gen_load_fpr_F(dc, a->rs2);
+ func(src1, tcg_env, src1, src2);
+ gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
+ gen_store_fpr_F(dc, a->rd, src1);
+ return advance_pc(dc);
+}
+
+TRANS(FADDs, ALL, do_env_fff, a, gen_helper_fadds)
+TRANS(FSUBs, ALL, do_env_fff, a, gen_helper_fsubs)
+TRANS(FMULs, ALL, do_env_fff, a, gen_helper_fmuls)
+TRANS(FDIVs, ALL, do_env_fff, a, gen_helper_fdivs)
+
static bool do_ddd(DisasContext *dc, arg_r_r_r *a,
void (*func)(TCGv_i64, TCGv_i64, TCGv_i64))
{
@@ -5118,10 +5126,11 @@ static void disas_sparc_legacy(DisasContext *dc,
unsigned int insn)
case 0x82: /* V9 fdtox */
case 0x88: /* V9 fxtod */
case 0x2b: /* fsqrtq */
- g_assert_not_reached(); /* in decodetree */
case 0x41: /* fadds */
- gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fadds);
- break;
+ case 0x45: /* fsubs */
+ case 0x49: /* fmuls */
+ case 0x4d: /* fdivs */
+ g_assert_not_reached(); /* in decodetree */
case 0x42: /* faddd */
gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_faddd);
break;
@@ -5129,9 +5138,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned
int insn)
CHECK_FPU_FEATURE(dc, FLOAT128);
gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_faddq);
break;
- case 0x45: /* fsubs */
- gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fsubs);
- break;
case 0x46: /* fsubd */
gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fsubd);
break;
@@ -5139,9 +5145,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned
int insn)
CHECK_FPU_FEATURE(dc, FLOAT128);
gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq);
break;
- case 0x49: /* fmuls */
- gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fmuls);
- break;
case 0x4a: /* fmuld */
gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld);
break;
@@ -5149,9 +5152,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned
int insn)
CHECK_FPU_FEATURE(dc, FLOAT128);
gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq);
break;
- case 0x4d: /* fdivs */
- gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fdivs);
- break;
case 0x4e: /* fdivd */
gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fdivd);
break;
--
2.34.1
- [PATCH v3 49/90] target/sparc: Move asi integer load/store to decodetree, (continued)
- [PATCH v3 49/90] target/sparc: Move asi integer load/store to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 50/90] target/sparc: Move LDSTUB, LDSTUBA to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 53/90] target/sparc: Move PREFETCH, PREFETCHA to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 55/90] target/sparc: Move simple fp load/store to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 57/90] target/sparc: Move LDFSR, STFSR to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 58/90] target/sparc: Merge LDFSR, LDXFSR implementations, Richard Henderson, 2023/10/21
- [PATCH v3 61/90] target/sparc: Move ADDRALIGN* to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 65/90] target/sparc: Use tcg_gen_vec_{add,sub}*, Richard Henderson, 2023/10/21
- [PATCH v3 62/90] target/sparc: Move BMASK to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 71/90] target/sparc: Move gen_fop_DD insns to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 73/90] target/sparc: Move gen_fop_FFF insns to decodetree,
Richard Henderson <=
- [PATCH v3 72/90] target/sparc: Move FSQRTq to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 75/90] target/sparc: Move gen_fop_QQQ insns to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 76/90] target/sparc: Move FSMULD to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 51/90] target/sparc: Move SWAP, SWAPA to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 54/90] target/sparc: Split out fp ldst functions with asi precomputed, Richard Henderson, 2023/10/21
- [PATCH v3 63/90] target/sparc: Move FMOVS, FNEGS, FABSS, FSRC*S, FNOT*S to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 69/90] target/sparc: Move gen_gsr_fop_DDD insns to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 66/90] target/sparc: Move gen_ne_fop_FFF insns to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 67/90] target/sparc: Move gen_ne_fop_DDD insns to decodetree, Richard Henderson, 2023/10/21
- [PATCH v3 68/90] target/sparc: Move PDIST to decodetree, Richard Henderson, 2023/10/21