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[PATCH v4 16/90] target/sparc: Merge gen_fcond with only caller
From: |
Richard Henderson |
Subject: |
[PATCH v4 16/90] target/sparc: Merge gen_fcond with only caller |
Date: |
Sat, 21 Oct 2023 22:59:17 -0700 |
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/translate.c | 22 ++++++++--------------
1 file changed, 8 insertions(+), 14 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 2664db302d..b8d51d6d64 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -1309,19 +1309,6 @@ static void gen_fcompare(DisasCompare *cmp, unsigned int
cc, unsigned int cond)
}
}
-static void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
-{
- DisasCompare cmp;
- gen_fcompare(&cmp, cc, cond);
-
- /* The interface is to return a boolean in r_dst. */
- if (cmp.is_bool) {
- tcg_gen_mov_tl(r_dst, cmp.c1);
- } else {
- tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2);
- }
-}
-
// Inverted logic
static const TCGCond gen_tcg_cond_reg[8] = {
TCG_COND_NEVER, /* reserved */
@@ -2992,6 +2979,7 @@ TRANS(BPcc, 64, do_bpcc, a)
static bool do_fbpfcc(DisasContext *dc, arg_bcc *a)
{
target_long target = address_mask_i(dc, dc->pc + a->i * 4);
+ DisasCompare cmp;
if (gen_trap_ifnofpu(dc)) {
return true;
@@ -3003,7 +2991,13 @@ static bool do_fbpfcc(DisasContext *dc, arg_bcc *a)
return advance_jump_uncond_always(dc, a->a, target);
default:
flush_cond(dc);
- gen_fcond(cpu_cond, a->cc, a->cond);
+
+ gen_fcompare(&cmp, a->cc, a->cond);
+ if (cmp.is_bool) {
+ tcg_gen_mov_tl(cpu_cond, cmp.c1);
+ } else {
+ tcg_gen_setcond_tl(cmp.cond, cpu_cond, cmp.c1, cmp.c2);
+ }
return advance_jump_cond(dc, a->a, target);
}
}
--
2.34.1
- [PATCH v4 06/90] target/sparc: Define features via cpu-feature.h.inc, (continued)
- [PATCH v4 06/90] target/sparc: Define features via cpu-feature.h.inc, Richard Henderson, 2023/10/22
- [PATCH v4 08/90] target/sparc: Remove sparcv7 cpu features, Richard Henderson, 2023/10/22
- [PATCH v4 09/90] target/sparc: Add decodetree infrastructure, Richard Henderson, 2023/10/22
- [PATCH v4 12/90] target/sparc: Move BPcc and Bicc to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 03/90] target/sparc: Avoid helper_raise_exception in helper_st_asi, Richard Henderson, 2023/10/22
- [PATCH v4 10/90] target/sparc: Define AM_CHECK for sparc32, Richard Henderson, 2023/10/22
- [PATCH v4 11/90] target/sparc: Move CALL to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 13/90] target/sparc: Move BPr to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 14/90] target/sparc: Move FBPfcc and FBfcc to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 15/90] target/sparc: Merge gen_cond with only caller, Richard Henderson, 2023/10/22
- [PATCH v4 16/90] target/sparc: Merge gen_fcond with only caller,
Richard Henderson <=
- [PATCH v4 19/90] target/sparc: Move SETHI to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 18/90] target/sparc: Pass DisasCompare to advance_jump_cond, Richard Henderson, 2023/10/22
- [PATCH v4 20/90] target/sparc: Move Tcc to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 23/90] target/sparc: Move RDWIM, RDPR to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 17/90] target/sparc: Merge gen_branch_[an] with only caller, Richard Henderson, 2023/10/22
- [PATCH v4 21/90] target/sparc: Move RDASR, STBAR, MEMBAR to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 32/90] target/sparc: Move UMUL, SMUL to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 22/90] target/sparc: Move RDPSR, RDHPR to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 24/90] target/sparc: Move RDTBR, FLUSHW to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 25/90] target/sparc: Move WRASR to decodetree, Richard Henderson, 2023/10/22