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[PATCH v4 18/90] target/sparc: Pass DisasCompare to advance_jump_cond
From: |
Richard Henderson |
Subject: |
[PATCH v4 18/90] target/sparc: Pass DisasCompare to advance_jump_cond |
Date: |
Sat, 21 Oct 2023 22:59:19 -0700 |
Fold the condition into the branch or movcond when possible.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/translate.c | 31 +++++++++++++------------------
1 file changed, 13 insertions(+), 18 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 503598ed93..d12f2b4b87 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -2899,14 +2899,15 @@ static bool advance_jump_uncond_always(DisasContext
*dc, bool annul,
return true;
}
-static bool advance_jump_cond(DisasContext *dc, bool annul, target_ulong dest)
+static bool advance_jump_cond(DisasContext *dc, DisasCompare *cmp,
+ bool annul, target_ulong dest)
{
target_ulong npc = dc->npc;
if (annul) {
TCGLabel *l1 = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cond, 0, l1);
+ tcg_gen_brcond_tl(tcg_invert_cond(cmp->cond), cmp->c1, cmp->c2, l1);
gen_goto_tb(dc, 0, npc, dest);
gen_set_label(l1);
gen_goto_tb(dc, 1, npc + 4, npc + 8);
@@ -2919,8 +2920,8 @@ static bool advance_jump_cond(DisasContext *dc, bool
annul, target_ulong dest)
case DYNAMIC_PC_LOOKUP:
tcg_gen_mov_tl(cpu_pc, cpu_npc);
tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
- tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc,
- cpu_cond, tcg_constant_tl(0),
+ tcg_gen_movcond_tl(cmp->cond, cpu_npc,
+ cmp->c1, cmp->c2,
tcg_constant_tl(dest), cpu_npc);
dc->pc = npc;
break;
@@ -2932,6 +2933,11 @@ static bool advance_jump_cond(DisasContext *dc, bool
annul, target_ulong dest)
dc->jump_pc[0] = dest;
dc->jump_pc[1] = npc + 4;
dc->npc = JUMP_PC;
+ if (cmp->is_bool) {
+ tcg_gen_mov_tl(cpu_cond, cmp->c1);
+ } else {
+ tcg_gen_setcond_tl(cmp->cond, cpu_cond, cmp->c1, cmp->c2);
+ }
}
}
return true;
@@ -2951,12 +2957,7 @@ static bool do_bpcc(DisasContext *dc, arg_bcc *a)
flush_cond(dc);
gen_compare(&cmp, a->cc, a->cond, dc);
- if (cmp.is_bool) {
- tcg_gen_mov_tl(cpu_cond, cmp.c1);
- } else {
- tcg_gen_setcond_tl(cmp.cond, cpu_cond, cmp.c1, cmp.c2);
- }
- return advance_jump_cond(dc, a->a, target);
+ return advance_jump_cond(dc, &cmp, a->a, target);
}
}
@@ -2980,12 +2981,7 @@ static bool do_fbpfcc(DisasContext *dc, arg_bcc *a)
flush_cond(dc);
gen_fcompare(&cmp, a->cc, a->cond);
- if (cmp.is_bool) {
- tcg_gen_mov_tl(cpu_cond, cmp.c1);
- } else {
- tcg_gen_setcond_tl(cmp.cond, cpu_cond, cmp.c1, cmp.c2);
- }
- return advance_jump_cond(dc, a->a, target);
+ return advance_jump_cond(dc, &cmp, a->a, target);
}
}
@@ -3006,8 +3002,7 @@ static bool trans_BPr(DisasContext *dc, arg_BPr *a)
flush_cond(dc);
gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1));
- tcg_gen_setcond_tl(cmp.cond, cpu_cond, cmp.c1, cmp.c2);
- return advance_jump_cond(dc, a->a, target);
+ return advance_jump_cond(dc, &cmp, a->a, target);
}
static bool trans_CALL(DisasContext *dc, arg_CALL *a)
--
2.34.1
- [PATCH v4 09/90] target/sparc: Add decodetree infrastructure, (continued)
- [PATCH v4 09/90] target/sparc: Add decodetree infrastructure, Richard Henderson, 2023/10/22
- [PATCH v4 12/90] target/sparc: Move BPcc and Bicc to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 03/90] target/sparc: Avoid helper_raise_exception in helper_st_asi, Richard Henderson, 2023/10/22
- [PATCH v4 10/90] target/sparc: Define AM_CHECK for sparc32, Richard Henderson, 2023/10/22
- [PATCH v4 11/90] target/sparc: Move CALL to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 13/90] target/sparc: Move BPr to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 14/90] target/sparc: Move FBPfcc and FBfcc to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 15/90] target/sparc: Merge gen_cond with only caller, Richard Henderson, 2023/10/22
- [PATCH v4 16/90] target/sparc: Merge gen_fcond with only caller, Richard Henderson, 2023/10/22
- [PATCH v4 19/90] target/sparc: Move SETHI to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 18/90] target/sparc: Pass DisasCompare to advance_jump_cond,
Richard Henderson <=
- [PATCH v4 20/90] target/sparc: Move Tcc to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 23/90] target/sparc: Move RDWIM, RDPR to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 17/90] target/sparc: Merge gen_branch_[an] with only caller, Richard Henderson, 2023/10/22
- [PATCH v4 21/90] target/sparc: Move RDASR, STBAR, MEMBAR to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 32/90] target/sparc: Move UMUL, SMUL to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 22/90] target/sparc: Move RDPSR, RDHPR to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 24/90] target/sparc: Move RDTBR, FLUSHW to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 25/90] target/sparc: Move WRASR to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 29/90] target/sparc: Move basic arithmetic to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 28/90] target/sparc: Move WRTBR, WRHPR to decodetree, Richard Henderson, 2023/10/22