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[PATCH v4 32/90] target/sparc: Move UMUL, SMUL to decodetree
From: |
Richard Henderson |
Subject: |
[PATCH v4 32/90] target/sparc: Move UMUL, SMUL to decodetree |
Date: |
Sat, 21 Oct 2023 22:59:33 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/insns.decode | 2 ++
target/sparc/translate.c | 21 +++------------------
2 files changed, 5 insertions(+), 18 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 1a04a8e229..d6a7256e71 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -167,6 +167,8 @@ XORN 10 ..... 0.0111 ..... . .............
@r_r_ri_cc
ADDC 10 ..... 0.1000 ..... . ............. @r_r_ri_cc
MULX 10 ..... 001001 ..... . ............. @r_r_ri_cc0
+UMUL 10 ..... 0.1010 ..... . ............. @r_r_ri_cc
+SMUL 10 ..... 0.1011 ..... . ............. @r_r_ri_cc
Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5
{
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index be00bd00fc..d79e28ab7f 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -2882,6 +2882,7 @@ static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1,
TCGv s2)
#define avail_ASR17(C) ((C)->def->features & CPU_FEATURE_ASR17)
#define avail_GL(C) ((C)->def->features & CPU_FEATURE_GL)
#define avail_HYPV(C) ((C)->def->features & CPU_FEATURE_HYPV)
+#define avail_MUL(C) ((C)->def->features & CPU_FEATURE_MUL)
#define avail_POWERDOWN(C) ((C)->def->features & CPU_FEATURE_POWERDOWN)
/* Default case for non jump instructions. */
@@ -4211,6 +4212,8 @@ TRANS(ANDN, ALL, do_arith, a, CC_OP_LOGIC,
tcg_gen_andc_tl, NULL)
TRANS(ORN, ALL, do_arith, a, CC_OP_LOGIC, tcg_gen_orc_tl, NULL)
TRANS(XORN, ALL, do_arith, a, CC_OP_LOGIC, tcg_gen_eqv_tl, NULL)
TRANS(MULX, 64, do_arith, a, 0, tcg_gen_mul_tl, tcg_gen_muli_tl)
+TRANS(UMUL, MUL, do_arith, a, CC_OP_LOGIC, gen_op_umul, NULL)
+TRANS(SMUL, MUL, do_arith, a, CC_OP_LOGIC, gen_op_smul, NULL)
static bool trans_OR(DisasContext *dc, arg_r_r_ri_cc *a)
{
@@ -4701,24 +4704,6 @@ static void disas_sparc_legacy(DisasContext *dc,
unsigned int insn)
cpu_src1 = get_src1(dc, insn);
cpu_src2 = get_src2(dc, insn);
switch (xop & ~0x10) {
- case 0xa: /* umul */
- CHECK_IU_FEATURE(dc, MUL);
- gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
- if (xop & 0x10) {
- tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
- tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
- dc->cc_op = CC_OP_LOGIC;
- }
- break;
- case 0xb: /* smul */
- CHECK_IU_FEATURE(dc, MUL);
- gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
- if (xop & 0x10) {
- tcg_gen_mov_tl(cpu_cc_dst, cpu_dst);
- tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
- dc->cc_op = CC_OP_LOGIC;
- }
- break;
case 0xc: /* subx, V9 subc */
gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2,
(xop & 0x10));
--
2.34.1
- [PATCH v4 13/90] target/sparc: Move BPr to decodetree, (continued)
- [PATCH v4 13/90] target/sparc: Move BPr to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 14/90] target/sparc: Move FBPfcc and FBfcc to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 15/90] target/sparc: Merge gen_cond with only caller, Richard Henderson, 2023/10/22
- [PATCH v4 16/90] target/sparc: Merge gen_fcond with only caller, Richard Henderson, 2023/10/22
- [PATCH v4 19/90] target/sparc: Move SETHI to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 18/90] target/sparc: Pass DisasCompare to advance_jump_cond, Richard Henderson, 2023/10/22
- [PATCH v4 20/90] target/sparc: Move Tcc to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 23/90] target/sparc: Move RDWIM, RDPR to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 17/90] target/sparc: Merge gen_branch_[an] with only caller, Richard Henderson, 2023/10/22
- [PATCH v4 21/90] target/sparc: Move RDASR, STBAR, MEMBAR to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 32/90] target/sparc: Move UMUL, SMUL to decodetree,
Richard Henderson <=
- [PATCH v4 22/90] target/sparc: Move RDPSR, RDHPR to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 24/90] target/sparc: Move RDTBR, FLUSHW to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 25/90] target/sparc: Move WRASR to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 29/90] target/sparc: Move basic arithmetic to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 28/90] target/sparc: Move WRTBR, WRHPR to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 30/90] target/sparc: Move ADDC to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 26/90] target/sparc: Move WRPSR, SAVED, RESTORED to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 31/90] target/sparc: Move MULX to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 27/90] target/sparc: Move WRWIM, WRPR to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 34/90] target/sparc: Move UDIVX, SDIVX to decodetree, Richard Henderson, 2023/10/22