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[PATCH v4 77/90] target/sparc: Move FDMULQ to decodetree
From: |
Richard Henderson |
Subject: |
[PATCH v4 77/90] target/sparc: Move FDMULQ to decodetree |
Date: |
Sat, 21 Oct 2023 23:00:18 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/insns.decode | 1 +
target/sparc/translate.c | 41 +++++++++++++++++++++------------------
2 files changed, 23 insertions(+), 19 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 6817d52ca2..a19d191603 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -261,6 +261,7 @@ FDIVs 10 ..... 110100 ..... 0 0100 1101 .....
@r_r_r
FDIVd 10 ..... 110100 ..... 0 0100 1110 ..... @r_r_r
FDIVq 10 ..... 110100 ..... 0 0100 1111 ..... @r_r_r
FsMULd 10 ..... 110100 ..... 0 0110 1001 ..... @r_r_r
+FdMULq 10 ..... 110100 ..... 0 0110 1110 ..... @r_r_r
FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2
FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2
FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 4a6f25bdf1..6a7788133a 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -1666,21 +1666,6 @@ static void gen_ne_fop_QQ(DisasContext *dc, int rd, int
rs,
}
#endif
-static void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2,
- void (*gen)(TCGv_ptr, TCGv_i64, TCGv_i64))
-{
- TCGv_i64 src1, src2;
-
- src1 = gen_load_fpr_D(dc, rs1);
- src2 = gen_load_fpr_D(dc, rs2);
-
- gen(tcg_env, src1, src2);
- gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
-
- gen_op_store_QT0_fpr(QFPREG(rd));
- gen_update_fprs_dirty(dc, QFPREG(rd));
-}
-
#ifdef TARGET_SPARC64
static void gen_fop_DF(DisasContext *dc, int rd, int rs,
void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32))
@@ -5143,6 +5128,27 @@ TRANS(FSUBq, ALL, do_env_qqq, a, gen_helper_fsubq)
TRANS(FMULq, ALL, do_env_qqq, a, gen_helper_fmulq)
TRANS(FDIVq, ALL, do_env_qqq, a, gen_helper_fdivq)
+static bool trans_FdMULq(DisasContext *dc, arg_r_r_r *a)
+{
+ TCGv_i64 src1, src2;
+
+ if (gen_trap_ifnofpu(dc)) {
+ return true;
+ }
+ if (gen_trap_float128(dc)) {
+ return true;
+ }
+
+ gen_op_clear_ieee_excp_and_FTT();
+ src1 = gen_load_fpr_D(dc, a->rs1);
+ src2 = gen_load_fpr_D(dc, a->rs2);
+ gen_helper_fdmulq(tcg_env, src1, src2);
+ gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
+ gen_op_store_QT0_fpr(QFPREG(a->rd));
+ gen_update_fprs_dirty(dc, QFPREG(a->rd));
+ return advance_pc(dc);
+}
+
#define CHECK_IU_FEATURE(dc, FEATURE) \
if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
goto illegal_insn;
@@ -5209,11 +5215,8 @@ static void disas_sparc_legacy(DisasContext *dc,
unsigned int insn)
case 0x4b: /* fmulq */
case 0x4f: /* fdivq */
case 0x69: /* fsmuld */
- g_assert_not_reached(); /* in decodetree */
case 0x6e: /* fdmulq */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- gen_fop_QDD(dc, rd, rs1, rs2, gen_helper_fdmulq);
- break;
+ g_assert_not_reached(); /* in decodetree */
case 0xc6: /* fdtos */
gen_fop_FD(dc, rd, rs2, gen_helper_fdtos);
break;
--
2.34.1
- [PATCH v4 56/90] target/sparc: Move asi fp load/store to decodetree, (continued)
- [PATCH v4 56/90] target/sparc: Move asi fp load/store to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 52/90] target/sparc: Move CASA, CASXA to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 62/90] target/sparc: Move BMASK to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 65/90] target/sparc: Use tcg_gen_vec_{add,sub}*, Richard Henderson, 2023/10/22
- [PATCH v4 66/90] target/sparc: Move gen_ne_fop_FFF insns to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 58/90] target/sparc: Merge LDFSR, LDXFSR implementations, Richard Henderson, 2023/10/22
- [PATCH v4 60/90] target/sparc: Move ARRAY* to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 70/90] target/sparc: Move gen_fop_FF insns to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 57/90] target/sparc: Move LDFSR, STFSR to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 72/90] target/sparc: Move FSQRTq to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 77/90] target/sparc: Move FDMULQ to decodetree,
Richard Henderson <=
- [PATCH v4 73/90] target/sparc: Move gen_fop_FFF insns to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 69/90] target/sparc: Move gen_gsr_fop_DDD insns to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 76/90] target/sparc: Move FSMULD to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 68/90] target/sparc: Move PDIST to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 54/90] target/sparc: Split out fp ldst functions with asi precomputed, Richard Henderson, 2023/10/22
- [PATCH v4 53/90] target/sparc: Move PREFETCH, PREFETCHA to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 61/90] target/sparc: Move ADDRALIGN* to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 59/90] target/sparc: Move EDGE* to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 64/90] target/sparc: Move FMOVD, FNEGD, FABSD, FSRC*D, FNOT*D to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 75/90] target/sparc: Move gen_fop_QQQ insns to decodetree, Richard Henderson, 2023/10/22