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[PATCH v4 85/90] target/sparc: Move FMOVR, FMOVcc, FMOVfcc to decodetree
From: |
Richard Henderson |
Subject: |
[PATCH v4 85/90] target/sparc: Move FMOVR, FMOVcc, FMOVfcc to decodetree |
Date: |
Sat, 21 Oct 2023 23:00:26 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/insns.decode | 12 +++
target/sparc/translate.c | 192 ++++++++++++++++----------------------
2 files changed, 91 insertions(+), 113 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 807ed3f66f..d4487e326a 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -284,6 +284,18 @@ FsTOi 10 ..... 110100 00000 0 1101 0001 .....
@r_r2
FdTOi 10 ..... 110100 00000 0 1101 0010 ..... @r_r2
FqTOi 10 ..... 110100 00000 0 1101 0011 ..... @r_r2
+FMOVscc 10 rd:5 110101 0 cond:4 1 cc:1 0 000001 rs2:5
+FMOVdcc 10 rd:5 110101 0 cond:4 1 cc:1 0 000010 rs2:5
+FMOVqcc 10 rd:5 110101 0 cond:4 1 cc:1 0 000011 rs2:5
+
+FMOVsfcc 10 rd:5 110101 0 cond:4 0 cc:2 000001 rs2:5
+FMOVdfcc 10 rd:5 110101 0 cond:4 0 cc:2 000010 rs2:5
+FMOVqfcc 10 rd:5 110101 0 cond:4 0 cc:2 000011 rs2:5
+
+FMOVRs 10 rd:5 110101 rs1:5 0 cond:3 00101 rs2:5
+FMOVRd 10 rd:5 110101 rs1:5 0 cond:3 00110 rs2:5
+FMOVRq 10 rd:5 110101 rs1:5 0 cond:3 00111 rs2:5
+
{
[
EDGE8cc 10 ..... 110110 ..... 0 0000 0000 ..... @r_r_r
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 0fc888df8c..de1c18d93b 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -2425,15 +2425,9 @@ static void gen_stda_asi(DisasContext *dc, DisasASI *da,
TCGv addr, int rd)
}
}
-#ifdef TARGET_SPARC64
-static TCGv get_src1(DisasContext *dc, unsigned int insn)
-{
- unsigned int rs1 = GET_FIELD(insn, 13, 17);
- return gen_load_gpr(dc, rs1);
-}
-
static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
{
+#ifdef TARGET_SPARC64
TCGv_i32 c32, zero, dst, s1, s2;
/* We have two choices here: extend the 32 bit data and use movcond_i64,
@@ -2456,19 +2450,27 @@ static void gen_fmovs(DisasContext *dc, DisasCompare
*cmp, int rd, int rs)
tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2);
gen_store_fpr_F(dc, rd, dst);
+#else
+ qemu_build_not_reached();
+#endif
}
static void gen_fmovd(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
{
+#ifdef TARGET_SPARC64
TCGv_i64 dst = gen_dest_fpr_D(dc, rd);
tcg_gen_movcond_i64(cmp->cond, dst, cmp->c1, cmp->c2,
gen_load_fpr_D(dc, rs),
gen_load_fpr_D(dc, rd));
gen_store_fpr_D(dc, rd, dst);
+#else
+ qemu_build_not_reached();
+#endif
}
static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
{
+#ifdef TARGET_SPARC64
int qd = QFPREG(rd);
int qs = QFPREG(rs);
@@ -2478,8 +2480,12 @@ static void gen_fmovq(DisasContext *dc, DisasCompare
*cmp, int rd, int rs)
cpu_fpr[qs / 2 + 1], cpu_fpr[qd / 2 + 1]);
gen_update_fprs_dirty(dc, qd);
+#else
+ qemu_build_not_reached();
+#endif
}
+#ifdef TARGET_SPARC64
static void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr)
{
TCGv_i32 r_tl = tcg_temp_new_i32();
@@ -5214,6 +5220,72 @@ static bool trans_FdMULq(DisasContext *dc, arg_r_r_r *a)
return advance_pc(dc);
}
+static bool do_fmovr(DisasContext *dc, arg_FMOVRs *a, bool is_128,
+ void (*func)(DisasContext *, DisasCompare *, int, int))
+{
+ DisasCompare cmp;
+
+ if (gen_trap_ifnofpu(dc)) {
+ return true;
+ }
+ if (is_128 && gen_trap_float128(dc)) {
+ return true;
+ }
+
+ gen_op_clear_ieee_excp_and_FTT();
+ gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1));
+ func(dc, &cmp, a->rd, a->rs2);
+ return advance_pc(dc);
+}
+
+TRANS(FMOVRs, 64, do_fmovr, a, false, gen_fmovs)
+TRANS(FMOVRd, 64, do_fmovr, a, false, gen_fmovd)
+TRANS(FMOVRq, 64, do_fmovr, a, true, gen_fmovq)
+
+static bool do_fmovcc(DisasContext *dc, arg_FMOVscc *a, bool is_128,
+ void (*func)(DisasContext *, DisasCompare *, int, int))
+{
+ DisasCompare cmp;
+
+ if (gen_trap_ifnofpu(dc)) {
+ return true;
+ }
+ if (is_128 && gen_trap_float128(dc)) {
+ return true;
+ }
+
+ gen_op_clear_ieee_excp_and_FTT();
+ gen_compare(&cmp, a->cc, a->cond, dc);
+ func(dc, &cmp, a->rd, a->rs2);
+ return advance_pc(dc);
+}
+
+TRANS(FMOVscc, 64, do_fmovcc, a, false, gen_fmovs)
+TRANS(FMOVdcc, 64, do_fmovcc, a, false, gen_fmovd)
+TRANS(FMOVqcc, 64, do_fmovcc, a, true, gen_fmovq)
+
+static bool do_fmovfcc(DisasContext *dc, arg_FMOVsfcc *a, bool is_128,
+ void (*func)(DisasContext *, DisasCompare *, int, int))
+{
+ DisasCompare cmp;
+
+ if (gen_trap_ifnofpu(dc)) {
+ return true;
+ }
+ if (is_128 && gen_trap_float128(dc)) {
+ return true;
+ }
+
+ gen_op_clear_ieee_excp_and_FTT();
+ gen_fcompare(&cmp, a->cc, a->cond);
+ func(dc, &cmp, a->rd, a->rs2);
+ return advance_pc(dc);
+}
+
+TRANS(FMOVsfcc, 64, do_fmovfcc, a, false, gen_fmovs)
+TRANS(FMOVdfcc, 64, do_fmovfcc, a, false, gen_fmovd)
+TRANS(FMOVqfcc, 64, do_fmovfcc, a, true, gen_fmovq)
+
#define CHECK_IU_FEATURE(dc, FEATURE) \
if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
goto illegal_insn;
@@ -5247,9 +5319,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned
int insn)
if (xop == 0x34) { /* FPU Operations */
goto illegal_insn; /* in decodetree */
} else if (xop == 0x35) { /* FPU Operations */
-#ifdef TARGET_SPARC64
- int cond;
-#endif
if (gen_trap_ifnofpu(dc)) {
goto jmp_insn;
}
@@ -5258,110 +5327,7 @@ static void disas_sparc_legacy(DisasContext *dc,
unsigned int insn)
rs2 = GET_FIELD(insn, 27, 31);
xop = GET_FIELD(insn, 18, 26);
-#ifdef TARGET_SPARC64
-#define FMOVR(sz) \
- do { \
- DisasCompare cmp; \
- cond = GET_FIELD_SP(insn, 10, 12); \
- cpu_src1 = get_src1(dc, insn); \
- gen_compare_reg(&cmp, cond, cpu_src1); \
- gen_fmov##sz(dc, &cmp, rd, rs2); \
- } while (0)
-
- if ((xop & 0x11f) == 0x005) { /* V9 fmovsr */
- FMOVR(s);
- break;
- } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
- FMOVR(d);
- break;
- } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
- CHECK_FPU_FEATURE(dc, FLOAT128);
- FMOVR(q);
- break;
- }
-#undef FMOVR
-#endif
switch (xop) {
-#ifdef TARGET_SPARC64
-#define FMOVCC(fcc, sz) \
- do { \
- DisasCompare cmp; \
- cond = GET_FIELD_SP(insn, 14, 17); \
- gen_fcompare(&cmp, fcc, cond); \
- gen_fmov##sz(dc, &cmp, rd, rs2); \
- } while (0)
-
- case 0x001: /* V9 fmovscc %fcc0 */
- FMOVCC(0, s);
- break;
- case 0x002: /* V9 fmovdcc %fcc0 */
- FMOVCC(0, d);
- break;
- case 0x003: /* V9 fmovqcc %fcc0 */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- FMOVCC(0, q);
- break;
- case 0x041: /* V9 fmovscc %fcc1 */
- FMOVCC(1, s);
- break;
- case 0x042: /* V9 fmovdcc %fcc1 */
- FMOVCC(1, d);
- break;
- case 0x043: /* V9 fmovqcc %fcc1 */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- FMOVCC(1, q);
- break;
- case 0x081: /* V9 fmovscc %fcc2 */
- FMOVCC(2, s);
- break;
- case 0x082: /* V9 fmovdcc %fcc2 */
- FMOVCC(2, d);
- break;
- case 0x083: /* V9 fmovqcc %fcc2 */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- FMOVCC(2, q);
- break;
- case 0x0c1: /* V9 fmovscc %fcc3 */
- FMOVCC(3, s);
- break;
- case 0x0c2: /* V9 fmovdcc %fcc3 */
- FMOVCC(3, d);
- break;
- case 0x0c3: /* V9 fmovqcc %fcc3 */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- FMOVCC(3, q);
- break;
-#undef FMOVCC
-#define FMOVCC(xcc, sz) \
- do { \
- DisasCompare cmp; \
- cond = GET_FIELD_SP(insn, 14, 17); \
- gen_compare(&cmp, xcc, cond, dc); \
- gen_fmov##sz(dc, &cmp, rd, rs2); \
- } while (0)
-
- case 0x101: /* V9 fmovscc %icc */
- FMOVCC(0, s);
- break;
- case 0x102: /* V9 fmovdcc %icc */
- FMOVCC(0, d);
- break;
- case 0x103: /* V9 fmovqcc %icc */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- FMOVCC(0, q);
- break;
- case 0x181: /* V9 fmovscc %xcc */
- FMOVCC(1, s);
- break;
- case 0x182: /* V9 fmovdcc %xcc */
- FMOVCC(1, d);
- break;
- case 0x183: /* V9 fmovqcc %xcc */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- FMOVCC(1, q);
- break;
-#undef FMOVCC
-#endif
case 0x51: /* fcmps, V9 %fcc */
cpu_src1_32 = gen_load_fpr_F(dc, rs1);
cpu_src2_32 = gen_load_fpr_F(dc, rs2);
--
2.34.1
- [PATCH v4 71/90] target/sparc: Move gen_fop_DD insns to decodetree, (continued)
- [PATCH v4 71/90] target/sparc: Move gen_fop_DD insns to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 74/90] target/sparc: Move gen_fop_DDD insns to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 78/90] target/sparc: Move gen_fop_FD insns to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 79/90] target/sparc: Move FiTOd, FsTOd, FsTOx to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 81/90] target/sparc: Move FqTOd, FqTOx to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 83/90] target/sparc: Move FdTOq, FxTOq to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 82/90] target/sparc: Move FiTOq, FsTOq to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 90/90] target/sparc: Remove disas_sparc_legacy, Richard Henderson, 2023/10/22
- [PATCH v4 88/90] target/sparc: Move FPACK16, FPACKFIX to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 86/90] target/sparc: Convert FCMP, FCMPE to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 85/90] target/sparc: Move FMOVR, FMOVcc, FMOVfcc to decodetree,
Richard Henderson <=
- [PATCH v4 80/90] target/sparc: Move FqTOs, FqTOi to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 89/90] target/sparc: Convert FZERO, FONE to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 87/90] target/sparc: Move FPCMP* to decodetree, Richard Henderson, 2023/10/22
- [PATCH v4 84/90] target/sparc: Move FMOVq, FNEGq, FABSq to decodetree, Richard Henderson, 2023/10/22
- Re: [PATCH v4 00/90] target/sparc: Convert to decodetree, Mark Cave-Ayland, 2023/10/22