Re: [PATCH 0/5] Add LoongArch v1.1 instructions

[Jiajie Chen]

On 2023/10/24 14:10, Jiajie Chen wrote:
> On 2023/10/24 07:26, Richard Henderson wrote:
> > On 10/23/23 08:29, Jiajie Chen wrote:
> > > This patch series implements the new instructions except sc.q, 
> > > because I do not know how to match a pair of ll.d to sc.q.
> >
> > There are a couple of examples within the tree.
> >
> > See target/arm/tcg/translate-a64.c, gen_store_exclusive, TCGv_i128 
> > block.
> > See target/ppc/translate.c, gen_stqcx_.
>
>
> The situation here is slightly different: aarch64 and ppc64 have both 
> 128-bit ll and sc, however LoongArch v1.1 only has 64-bit ll and 
> 128-bit sc. I guest the intended usage of sc.q is:
>
>
> ll.d lo, base, 0
>
> ll.d hi, base, 4
>
> # do some computation
>
> sc.q lo, hi, base
>
> # try again if sc failed


Possibly use the combination of ll.d and ld.d:


ll.d lo, base, 0

ld.d hi, base, 4

# do some computation

sc.q lo, hi, base

# try again if sc failed


Then a possible implementation of gen_ll() would be: align base to 
128-bit boundary, read 128-bit from memory, save 64-bit part to rd and 
record whole 128-bit data in llval. Then, in gen_sc_q(), it uses a 
128-bit cmpxchg.


But what about the reversed instruction pattern: ll.d hi, base, 4; ld.d 
lo, base 0?


Since there are no existing code utilizing the new sc.q instruction, I 
don't know what should we consider here.


> > r~