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[PULL 51/94] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for GET_ASI_DT
From: |
Richard Henderson |
Subject: |
[PULL 51/94] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for GET_ASI_DTWINX |
Date: |
Wed, 25 Oct 2023 17:14:59 -0700 |
Perform one atomic 16-byte operation.
The atomicity is required for the LDTXA instructions.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/translate.c | 48 +++++++++++++++++++++++++++++++++-------
1 file changed, 40 insertions(+), 8 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index e24945e50e..7ce9ab66c6 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -2594,11 +2594,27 @@ static void gen_ldda_asi0(DisasContext *dc, DisasASI
*da, TCGv addr, int rd)
return;
case GET_ASI_DTWINX:
- assert(TARGET_LONG_BITS == 64);
- tcg_gen_qemu_ld_tl(hi, addr, da->mem_idx, da->memop | MO_ALIGN_16);
- tcg_gen_addi_tl(addr, addr, 8);
- tcg_gen_qemu_ld_tl(lo, addr, da->mem_idx, da->memop);
+#ifdef TARGET_SPARC64
+ {
+ MemOp mop = (da->memop & MO_BSWAP) | MO_128 | MO_ALIGN_16;
+ TCGv_i128 t = tcg_temp_new_i128();
+
+ tcg_gen_qemu_ld_i128(t, addr, da->mem_idx, mop);
+ /*
+ * Note that LE twinx acts as if each 64-bit register result is
+ * byte swapped. We perform one 128-bit LE load, so must swap
+ * the order of the writebacks.
+ */
+ if ((mop & MO_BSWAP) == MO_TE) {
+ tcg_gen_extr_i128_i64(lo, hi, t);
+ } else {
+ tcg_gen_extr_i128_i64(hi, lo, t);
+ }
+ }
break;
+#else
+ g_assert_not_reached();
+#endif
case GET_ASI_DIRECT:
{
@@ -2663,11 +2679,27 @@ static void gen_stda_asi0(DisasContext *dc, DisasASI
*da, TCGv addr, int rd)
break;
case GET_ASI_DTWINX:
- assert(TARGET_LONG_BITS == 64);
- tcg_gen_qemu_st_tl(hi, addr, da->mem_idx, da->memop | MO_ALIGN_16);
- tcg_gen_addi_tl(addr, addr, 8);
- tcg_gen_qemu_st_tl(lo, addr, da->mem_idx, da->memop);
+#ifdef TARGET_SPARC64
+ {
+ MemOp mop = (da->memop & MO_BSWAP) | MO_128 | MO_ALIGN_16;
+ TCGv_i128 t = tcg_temp_new_i128();
+
+ /*
+ * Note that LE twinx acts as if each 64-bit register result is
+ * byte swapped. We perform one 128-bit LE store, so must swap
+ * the order of the construction.
+ */
+ if ((mop & MO_BSWAP) == MO_TE) {
+ tcg_gen_concat_i64_i128(t, lo, hi);
+ } else {
+ tcg_gen_concat_i64_i128(t, hi, lo);
+ }
+ tcg_gen_qemu_st_i128(t, addr, da->mem_idx, mop);
+ }
break;
+#else
+ g_assert_not_reached();
+#endif
case GET_ASI_DIRECT:
{
--
2.34.1
- [PATCH 27/29] target/alpha: Use TCG_COND_TST{EQ,NE} for BLB{C,S}, (continued)
- [PATCH 27/29] target/alpha: Use TCG_COND_TST{EQ,NE} for BLB{C,S}, Richard Henderson, 2023/10/25
- [PULL 32/94] target/sparc: Remove cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver, Richard Henderson, 2023/10/25
- [PULL 33/94] target/sparc: Move basic arithmetic to decodetree, Richard Henderson, 2023/10/25
- [PULL 40/94] target/sparc: Move TADD, TSUB, MULS to decodetree, Richard Henderson, 2023/10/25
- [PULL 45/94] target/sparc: Move JMPL, RETT, RETURN to decodetree, Richard Henderson, 2023/10/25
- [PULL 48/94] target/sparc: Split out resolve_asi, Richard Henderson, 2023/10/25
- [PULL 42/94] target/sparc: Move MOVcc, MOVR to decodetree, Richard Henderson, 2023/10/25
- [PULL 49/94] target/sparc: Drop ifdef around get_asi and friends, Richard Henderson, 2023/10/25
- [PULL 54/94] target/sparc: Move LDSTUB, LDSTUBA to decodetree, Richard Henderson, 2023/10/25
- [PULL 56/94] target/sparc: Move CASA, CASXA to decodetree, Richard Henderson, 2023/10/25
- [PULL 51/94] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for GET_ASI_DTWINX,
Richard Henderson <=
- [PULL 57/94] target/sparc: Move PREFETCH, PREFETCHA to decodetree, Richard Henderson, 2023/10/25
- [PULL 61/94] target/sparc: Move LDFSR, STFSR to decodetree, Richard Henderson, 2023/10/25
- [PULL 60/94] target/sparc: Move asi fp load/store to decodetree, Richard Henderson, 2023/10/25
- [PULL 58/94] target/sparc: Split out fp ldst functions with asi precomputed, Richard Henderson, 2023/10/25
- [PULL 52/94] target/sparc: Move simple integer load/store to decodetree, Richard Henderson, 2023/10/25
- [PULL 53/94] target/sparc: Move asi integer load/store to decodetree, Richard Henderson, 2023/10/25
- [PULL 55/94] target/sparc: Move SWAP, SWAPA to decodetree, Richard Henderson, 2023/10/25
- [PULL 65/94] target/sparc: Move ADDRALIGN* to decodetree, Richard Henderson, 2023/10/25
- [PULL 72/94] target/sparc: Move PDIST to decodetree, Richard Henderson, 2023/10/25
- [PULL 79/94] target/sparc: Move gen_fop_QQQ insns to decodetree, Richard Henderson, 2023/10/25