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[PULL 57/94] target/sparc: Move PREFETCH, PREFETCHA to decodetree
From: |
Richard Henderson |
Subject: |
[PULL 57/94] target/sparc: Move PREFETCH, PREFETCHA to decodetree |
Date: |
Wed, 25 Oct 2023 17:15:05 -0700 |
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/insns.decode | 8 ++++++--
target/sparc/translate.c | 23 ++++++++---------------
2 files changed, 14 insertions(+), 17 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 82c484fbc7..aa452f1d00 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -231,6 +231,9 @@ RESTORE 10 ..... 111101 ..... . .............
@r_r_ri
DONE 10 00000 111110 00000 0 0000000000000
RETRY 10 00001 111110 00000 0 0000000000000
+NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1
+NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2
+
##
## Major Opcode 11 -- load and store instructions
##
@@ -299,8 +302,9 @@ CASA 11 ..... 111100 ..... . .............
@casa_imm
CASXA 11 ..... 111110 ..... . ............. @r_r_r_asi
CASXA 11 ..... 111110 ..... . ............. @casa_imm
-NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1
-NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2
+NOP_v9 11 ----- 101101 ----- 0 00000000 ----- # PREFETCH
+NOP_v9 11 ----- 101101 ----- 1 ------------- # PREFETCH
+NOP_v9 11 ----- 111101 ----- - ------------- # PREFETCHA
NCP 11 ----- 110000 ----- --------- ----- # v8 LDC
NCP 11 ----- 110001 ----- --------- ----- # v8 LDCSR
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 2175c00ded..363d8b7fc8 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -4031,17 +4031,12 @@ static bool trans_NOP(DisasContext *dc, arg_NOP *a)
return advance_pc(dc);
}
-static bool trans_NOP_v7(DisasContext *dc, arg_NOP_v7 *a)
-{
- /*
- * TODO: Need a feature bit for sparcv8.
- * In the meantime, treat all 32-bit cpus like sparcv7.
- */
- if (avail_32(dc)) {
- return advance_pc(dc);
- }
- return false;
-}
+/*
+ * TODO: Need a feature bit for sparcv8.
+ * In the meantime, treat all 32-bit cpus like sparcv7.
+ */
+TRANS(NOP_v7, 32, trans_NOP, a)
+TRANS(NOP_v9, 64, trans_NOP, a)
static bool do_arith_int(DisasContext *dc, arg_r_r_ri_cc *a, int cc_op,
void (*func)(TCGv, TCGv, TCGv),
@@ -5457,10 +5452,10 @@ static void disas_sparc_legacy(DisasContext *dc,
unsigned int insn)
case 0x0b: /* V9 ldx */
case 0x18: /* V9 ldswa */
case 0x1b: /* V9 ldxa */
+ case 0x2d: /* V9 prefetch */
+ case 0x3d: /* V9 prefetcha */
goto illegal_insn; /* in decodetree */
#ifdef TARGET_SPARC64
- case 0x2d: /* V9 prefetch, no effect */
- goto skip_move;
case 0x30: /* V9 ldfa */
if (gen_trap_ifnofpu(dc)) {
goto jmp_insn;
@@ -5475,8 +5470,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned
int insn)
gen_ldf_asi(dc, cpu_addr, insn, 8, DFPREG(rd));
gen_update_fprs_dirty(dc, DFPREG(rd));
goto skip_move;
- case 0x3d: /* V9 prefetcha, no effect */
- goto skip_move;
case 0x32: /* V9 ldqfa */
CHECK_FPU_FEATURE(dc, FLOAT128);
if (gen_trap_ifnofpu(dc)) {
--
2.34.1
- [PULL 32/94] target/sparc: Remove cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver, (continued)
- [PULL 32/94] target/sparc: Remove cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver, Richard Henderson, 2023/10/25
- [PULL 33/94] target/sparc: Move basic arithmetic to decodetree, Richard Henderson, 2023/10/25
- [PULL 40/94] target/sparc: Move TADD, TSUB, MULS to decodetree, Richard Henderson, 2023/10/25
- [PULL 45/94] target/sparc: Move JMPL, RETT, RETURN to decodetree, Richard Henderson, 2023/10/25
- [PULL 48/94] target/sparc: Split out resolve_asi, Richard Henderson, 2023/10/25
- [PULL 42/94] target/sparc: Move MOVcc, MOVR to decodetree, Richard Henderson, 2023/10/25
- [PULL 49/94] target/sparc: Drop ifdef around get_asi and friends, Richard Henderson, 2023/10/25
- [PULL 54/94] target/sparc: Move LDSTUB, LDSTUBA to decodetree, Richard Henderson, 2023/10/25
- [PULL 56/94] target/sparc: Move CASA, CASXA to decodetree, Richard Henderson, 2023/10/25
- [PULL 51/94] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for GET_ASI_DTWINX, Richard Henderson, 2023/10/25
- [PULL 57/94] target/sparc: Move PREFETCH, PREFETCHA to decodetree,
Richard Henderson <=
- [PULL 61/94] target/sparc: Move LDFSR, STFSR to decodetree, Richard Henderson, 2023/10/25
- [PULL 60/94] target/sparc: Move asi fp load/store to decodetree, Richard Henderson, 2023/10/25
- [PULL 58/94] target/sparc: Split out fp ldst functions with asi precomputed, Richard Henderson, 2023/10/25
- [PULL 52/94] target/sparc: Move simple integer load/store to decodetree, Richard Henderson, 2023/10/25
- [PULL 53/94] target/sparc: Move asi integer load/store to decodetree, Richard Henderson, 2023/10/25
- [PULL 55/94] target/sparc: Move SWAP, SWAPA to decodetree, Richard Henderson, 2023/10/25
- [PULL 65/94] target/sparc: Move ADDRALIGN* to decodetree, Richard Henderson, 2023/10/25
- [PULL 72/94] target/sparc: Move PDIST to decodetree, Richard Henderson, 2023/10/25
- [PULL 79/94] target/sparc: Move gen_fop_QQQ insns to decodetree, Richard Henderson, 2023/10/25
- [PULL 78/94] target/sparc: Move gen_fop_DDD insns to decodetree, Richard Henderson, 2023/10/25