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[PULL 04/41] target/arm: Move ID_AA64MMFR1 and ID_AA64MMFR2 tests togeth
From: |
Peter Maydell |
Subject: |
[PULL 04/41] target/arm: Move ID_AA64MMFR1 and ID_AA64MMFR2 tests together |
Date: |
Fri, 27 Oct 2023 15:39:05 +0100 |
Our list of isar_feature functions is not in any particular order,
but tests on fields of the same ID register tend to be grouped
together. A few functions that are tests of fields in ID_AA64MMFR1
and ID_AA64MMFR2 are not in the same place as the rest; move them
into their groups.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20231024163510.2972081-3-peter.maydell@linaro.org
---
target/arm/cpu-features.h | 60 +++++++++++++++++++--------------------
1 file changed, 30 insertions(+), 30 deletions(-)
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index bfc9bfafe70..fc85a8fe130 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -641,6 +641,21 @@ static inline bool isar_feature_aa64_tidcp1(const
ARMISARegisters *id)
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR1, TIDCP1) != 0;
}
+static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) != 0;
+}
+
+static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >= 2;
+}
+
+static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
+}
+
static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
@@ -676,6 +691,21 @@ static inline bool isar_feature_aa64_evt(const
ARMISARegisters *id)
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 2;
}
+static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
+}
+
+static inline bool isar_feature_aa64_lva(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0;
+}
+
+static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) != 0;
+}
+
static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
@@ -794,36 +824,6 @@ static inline bool isar_feature_aa64_fgt(const
ARMISARegisters *id)
return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0;
}
-static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
-{
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
-}
-
-static inline bool isar_feature_aa64_lva(const ARMISARegisters *id)
-{
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0;
-}
-
-static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id)
-{
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) != 0;
-}
-
-static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id)
-{
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) != 0;
-}
-
-static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id)
-{
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >= 2;
-}
-
-static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
-{
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
-}
-
static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
--
2.34.1
- [PULL 00/41] target-arm queue, Peter Maydell, 2023/10/27
- [PULL 01/41] target/arm: Correct minor errors in Cortex-A710 definition, Peter Maydell, 2023/10/27
- [PULL 04/41] target/arm: Move ID_AA64MMFR1 and ID_AA64MMFR2 tests together,
Peter Maydell <=
- [PULL 05/41] target/arm: Move ID_AA64MMFR0 tests up to before MMFR1 and MMFR2, Peter Maydell, 2023/10/27
- [PULL 10/41] hw/arm/allwinner-a10: Remove 'hw/arm/boot.h' from header, Peter Maydell, 2023/10/27
- [PULL 06/41] target/arm: Move ID_AA64ISAR* test functions together, Peter Maydell, 2023/10/27
- [PULL 02/41] target/arm: Implement Neoverse N2 CPU model, Peter Maydell, 2023/10/27
- [PULL 08/41] target/arm: Move ID_AA64DFR* feature tests together, Peter Maydell, 2023/10/27
- [PULL 11/41] hw/arm/allwinner-h3: Remove 'hw/arm/boot.h' from header, Peter Maydell, 2023/10/27
- [PULL 12/41] hw/arm/allwinner-r40: Remove 'hw/arm/boot.h' from header, Peter Maydell, 2023/10/27
- [PULL 09/41] target/arm: Fix syndrome for FGT traps on ERET, Peter Maydell, 2023/10/27
- [PULL 13/41] hw/arm/fsl-imx25: Remove 'hw/arm/boot.h' from header, Peter Maydell, 2023/10/27
- [PULL 16/41] hw/arm/fsl-imx6ul: Remove 'hw/arm/boot.h' from header, Peter Maydell, 2023/10/27