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Re: [PATCH v5 0/5] VIA PM: Implement basic ACPI support
From: |
BALATON Zoltan |
Subject: |
Re: [PATCH v5 0/5] VIA PM: Implement basic ACPI support |
Date: |
Sat, 28 Oct 2023 14:58:32 +0200 (CEST) |
Hello,
On Sat, 28 Oct 2023, Bernhard Beschow wrote:
This series is part of my work to bring the VIA south bridges to the PC machine
[1]. It implements missing ACPI functionality which ACPI-aware x86 guests
expect for a smooth experience. The implementation is heavily inspired by PIIX4.
I think first the interrupt routing should be fixed because that may
change a few things in this series so that should be the next step and
then rebase this series on top of that.
What I mean by fixing interrupt routing? You may remember this discussion:
https://patchew.org/QEMU/cover.1677004414.git.balaton@eik.bme.hu/
With pegasos2 your (over)simplification worked only because the firmware
of that machine maps everythnig to one ISA IRQ and guests were happy with
that. I told you that back then but could not convince you and Mark about
that. Now with the amigaone machine the firmware maps VIA devices and PCI
interuupt pins to different ISA IRQs so we need to go back either to my
otiginal implementation or something else you come up with. You can test
this trying to use USB devices with amigaone machine which only works
after reverting 4e5a20b6da9b1 and 422a6e8075752. So please either propose
something to fix that first or wait with this series until I can update my
pathches to solve interrupt routing. I think this series should wait until
after that because it adds more interrupt handling which should follow
whatever way we come up with for that so it's too early fir this series
yet. (If you want to try fixing it keep in mind that in both amigaone and
pegasos2 the PCI buses are in the north bridge not in the VIA south bridge
so don't try to force the IRQ mapping into the PCI bus. All the VIA chip
needs to do is mapping its PIRQ/PINT pins to ISA IRQs as the VIA is only
handling ISA IRQs and all other pci stuff is handled in the north bridge.
So I think we need a via_set_isa_irq function but we could change it
according to Mark's idea to pass the PCI device and use its function
number to select itq source instead of the enum I had in my original
series.)
I have some other comments that I'll add in reply to individual patches
for the future/
Regards,
BALATON Zoltan
Further quirks are needed in order to use the VIA south bridges in the PC
machine. These were deliberately left out for a future series. The idea for now
is to get the device model in shape for adding support for it in SeaBIOS.
The series is structured as follows: The first patch fixes ACPI events to be
signalled by SCI interrupts. The next three patches implement typical ACPI
event handling. The last patch adds software-based SMI triggering which is the
mechanism used in ACPI to transition the system into ACPI mode.
Testing done:
* `make check`
* `make check-avocado`
* `qemu-system-ppc -M pegasos2 \
-device ati-vga,romfile="" \
-cdrom morphos-3.18.iso \
-bios pegasos2.rom`
[1] https://github.com/shentok/qemu/tree/pc-via
v5:
* Implement software-based SMI triggering and handling of ACPI events based on
v3
v4:
* Alternative proposal (Zoltan)
v3: 20231005115159.81202-1-shentey@gmail.com/">https://patchew.org/QEMU/20231005115159.81202-1-shentey@gmail.com/
* Rename SCI irq attribute to sci_irq (Zoltan)
* Fix confusion about location of ACPI interrupt select register (Zoltan)
* Model SCI as named GPIO (Bernhard)
* Perform upcast via macro rather than sub structure selection (Bernhard)
v2:
* Introduce named constants for the ACPI interrupt select register at offset
0x42 (Phil)
Bernhard Beschow (5):
hw/isa/vt82c686: Respect SCI interrupt assignment
hw/isa/vt82c686: Add missing initialization of ACPI general purpose
event registers
hw/isa/vt82c686: Reuse acpi_update_sci()
hw/isa/vt82c686: Implement ACPI powerdown
hw/isa/vt82c686: Implement software-based SMI triggering
hw/isa/vt82c686.c | 179 ++++++++++++++++++++++++++++++++++++----------
1 file changed, 142 insertions(+), 37 deletions(-)
--
2.42.0
- Re: [PATCH v5 5/5] hw/isa/vt82c686: Implement software-based SMI triggering, (continued)
[PATCH v5 3/5] hw/isa/vt82c686: Reuse acpi_update_sci(), Bernhard Beschow, 2023/10/28
[PATCH v5 1/5] hw/isa/vt82c686: Respect SCI interrupt assignment, Bernhard Beschow, 2023/10/28
Re: [PATCH v5 0/5] VIA PM: Implement basic ACPI support,
BALATON Zoltan <=